git.sur5r.net Git - cc65/blob - src/ca65/instr.h

   1 /*****************************************************************************/
   2 /*                                                                           */
   3 /*                                  instr.h                                  */
   4 /*                                                                           */
   5 /*             Instruction encoding for the ca65 macroassembler              */
   6 /*                                                                           */
   7 /*                                                                           */
   8 /*                                                                           */
   9 /* (C) 1998-2000 Ullrich von Bassewitz                                       */
  10 /*               Wacholderweg 14                                             */
  11 /*               D-70597 Stuttgart                                           */
  12 /* EMail:        uz@musoftware.de                                            */
  13 /*                                                                           */
  14 /*                                                                           */
  15 /* This software is provided 'as-is', without any expressed or implied       */
  16 /* warranty.  In no event will the authors be held liable for any damages    */
  17 /* arising from the use of this software.                                    */
  18 /*                                                                           */
  19 /* Permission is granted to anyone to use this software for any purpose,     */
  20 /* including commercial applications, and to alter it and redistribute it    */
  21 /* freely, subject to the following restrictions:                            */
  22 /*                                                                           */
  23 /* 1. The origin of this software must not be misrepresented; you must not   */
  24 /*    claim that you wrote the original software. If you use this software   */
  25 /*    in a product, an acknowledgment in the product documentation would be  */
  26 /*    appreciated but is not required.                                       */
  27 /* 2. Altered source versions must be plainly marked as such, and must not   */
  28 /*    be misrepresented as being the original software.                      */
  29 /* 3. This notice may not be removed or altered from any source              */
  30 /*    distribution.                                                          */
  31 /*                                                                           */
  32 /*****************************************************************************/
  33
  34
  35
  36 #ifndef INSTR_H
  37 #define INSTR_H
  38
  39
  40
  41 /*****************************************************************************/
  42 /*                                   Data                                    */
  43 /*****************************************************************************/
  44
  45
  46
  47 /* Supported CPUs */
  48 enum CPUType {
  49     CPU_6502,
  50     CPU_65C02,
  51     CPU_65816,
  52     CPU_SUNPLUS,        /* Not in the freeware version - sorry */
  53     CPU_COUNT           /* Count of different CPUs */
  54 };
  55
  56 /* Constants for the addressing mode. If an opcode is available in zero page
  57  * and absolut adressing mode, both bits are set. When checking for valid
  58  * modes, the zeropage bit is checked first. Similar, the implicit bit is set
  59  * on accu adressing modes, so the 'A' for accu adressing is not needed (but
  60  * may be specified).
  61  * When assembling for the 6502 or 65C02, all addressing modes that are not
  62  * available on these CPUs are removed before doing any checks.
  63  */
  64 #define AM_IMPLICIT             0x00000003UL
  65 #define AM_ACCU                 0x00000002UL
  66 #define AM_DIR                  0x00000004UL
  67 #define AM_ABS                  0x00000008UL
  68 #define AM_ABS_LONG             0x00000010UL
  69 #define AM_DIR_X                0x00000020UL
  70 #define AM_ABS_X                0x00000040UL
  71 #define AM_ABS_LONG_X           0x00000080UL
  72 #define AM_DIR_Y                0x00000100UL
  73 #define AM_ABS_Y                0x00000200UL
  74 #define AM_DIR_IND              0x00000400UL
  75 #define AM_ABS_IND              0x00000800UL
  76 #define AM_DIR_IND_LONG         0x00001000UL
  77 #define AM_DIR_IND_Y            0x00002000UL
  78 #define AM_DIR_IND_LONG_Y       0x00004000UL
  79 #define AM_DIR_X_IND            0x00008000UL
  80 #define AM_ABS_X_IND            0x00010000UL
  81 #define AM_REL                  0x00020000UL
  82 #define AM_REL_LONG             0x00040000UL
  83 #define AM_STACK_REL            0x00080000UL
  84 #define AM_STACK_REL_IND_Y      0x00100000UL
  85 #define AM_IMM_ACCU             0x00200000UL
  86 #define AM_IMM_INDEX            0x00400000UL
  87 #define AM_IMM_IMPLICIT         0x00800000UL
  88 #define AM_IMM                  (AM_IMM_ACCU | AM_IMM_INDEX | AM_IMM_IMPLICIT)
  89 #define AM_BLOCKMOVE            0x01000000UL
  90
  91 /* Bitmask for all ZP operations that have correspondent ABS ops */
  92 #define AM_ZP   (AM_DIR | AM_DIR_X | AM_DIR_Y | AM_DIR_IND | AM_DIR_X_IND)
  93
  94 /* Bit numbers and count */
  95 #define AMI_IMM_ACCU            21
  96 #define AMI_IMM_INDEX           22
  97 #define AMI_COUNT               25
  98
  99
 100
 101 /* Description for one instruction */
 102 typedef struct InsDesc_ InsDesc;
 103 struct InsDesc_ {
 104     char                Mnemonic [4];
 105     unsigned long       AddrMode;               /* Valid adressing modes */
 106     unsigned char       BaseCode;               /* Base opcode */
 107     unsigned char       ExtCode;                /* Number of ext code table */
 108     void                (*Emit) (const InsDesc*);/* Handler function */
 109 };
 110
 111 /* An instruction table */
 112 typedef struct InsTable_ InsTable;
 113 struct InsTable_ {
 114     unsigned            Count;                  /* Number of intstructions */
 115     InsDesc             Ins[1];                 /* Varying length */
 116 };
 117
 118 /* The instruction table for the currently active CPU */
 119 extern const InsTable* InsTab;
 120
 121 /* Table to build the effective opcode from a base opcode and an addressing
 122  * mode.
 123  */
 124 extern unsigned char EATab [9][AMI_COUNT];
 125
 126 /* Table that encodes the additional bytes for each instruction */
 127 extern unsigned char ExtBytes [AMI_COUNT];
 128
 129
 130
 131 /*****************************************************************************/
 132 /*                                   Code                                    */
 133 /*****************************************************************************/
 134
 135
 136
 137 void SetCPU (enum CPUType NewCPU);
 138 /* Set a new CPU */
 139
 140 enum CPUType GetCPU (void);
 141 /* Return the current CPU */
 142
 143 int FindInstruction (const char* Ident);
 144 /* Check if Ident is a valid mnemonic. If so, return the index in the
 145  * instruction table. If not, return -1.
 146  */
 147
 148 void HandleInstruction (unsigned Index);
 149 /* Handle the mnemonic with the given index */
 150
 151
 152
 153 /* End of instr.h */
 154
 155 #endif
 156
 157
 158
 159