git.sur5r.net Git - cc65/blob - src/ca65/instr.h

   1 /*****************************************************************************/
   2 /*                                                                           */
   3 /*                                  instr.h                                  */
   4 /*                                                                           */
   5 /*             Instruction encoding for the ca65 macroassembler              */
   6 /*                                                                           */
   7 /*                                                                           */
   8 /*                                                                           */
   9 /* (C) 1998-2004 Ullrich von Bassewitz                                       */
  10 /*               Römerstrasse 52                                             */
  11 /*               D-70794 Filderstadt                                         */
  12 /* EMail:        uz@cc65.org                                                 */
  13 /*                                                                           */
  14 /*                                                                           */
  15 /* This software is provided 'as-is', without any expressed or implied       */
  16 /* warranty.  In no event will the authors be held liable for any damages    */
  17 /* arising from the use of this software.                                    */
  18 /*                                                                           */
  19 /* Permission is granted to anyone to use this software for any purpose,     */
  20 /* including commercial applications, and to alter it and redistribute it    */
  21 /* freely, subject to the following restrictions:                            */
  22 /*                                                                           */
  23 /* 1. The origin of this software must not be misrepresented; you must not   */
  24 /*    claim that you wrote the original software. If you use this software   */
  25 /*    in a product, an acknowledgment in the product documentation would be  */
  26 /*    appreciated but is not required.                                       */
  27 /* 2. Altered source versions must be plainly marked as such, and must not   */
  28 /*    be misrepresented as being the original software.                      */
  29 /* 3. This notice may not be removed or altered from any source              */
  30 /*    distribution.                                                          */
  31 /*                                                                           */
  32 /*****************************************************************************/
  33
  34
  35
  36 #ifndef INSTR_H
  37 #define INSTR_H
  38
  39
  40
  41 /* common */
  42 #include "cpu.h"
  43
  44
  45
  46 /*****************************************************************************/
  47 /*                       Data for 6502 and successors                        */
  48 /*****************************************************************************/
  49
  50
  51
  52 /* Constants for the addressing mode. If an opcode is available in zero page
  53  * and absolut adressing mode, both bits are set. When checking for valid
  54  * modes, the zeropage bit is checked first. Similar, the implicit bit is set
  55  * on accu adressing modes, so the 'A' for accu adressing is not needed (but
  56  * may be specified).
  57  * When assembling for the 6502 or 65C02, all addressing modes that are not
  58  * available on these CPUs are removed before doing any checks.
  59  */
  60 #define AM65_IMPLICIT                   0x00000003UL
  61 #define AM65_ACCU                       0x00000002UL
  62 #define AM65_DIR                0x00000004UL
  63 #define AM65_ABS                0x00000008UL
  64 #define AM65_ABS_LONG           0x00000010UL
  65 #define AM65_DIR_X              0x00000020UL
  66 #define AM65_ABS_X              0x00000040UL
  67 #define AM65_ABS_LONG_X         0x00000080UL
  68 #define AM65_DIR_Y                      0x00000100UL
  69 #define AM65_ABS_Y                      0x00000200UL
  70 #define AM65_DIR_IND                    0x00000400UL
  71 #define AM65_ABS_IND                    0x00000800UL
  72 #define AM65_DIR_IND_LONG               0x00001000UL
  73 #define AM65_DIR_IND_Y                  0x00002000UL
  74 #define AM65_DIR_IND_LONG_Y             0x00004000UL
  75 #define AM65_DIR_X_IND                  0x00008000UL
  76 #define AM65_ABS_X_IND                  0x00010000UL
  77 #define AM65_REL                        0x00020000UL
  78 #define AM65_REL_LONG                   0x00040000UL
  79 #define AM65_STACK_REL                  0x00080000UL
  80 #define AM65_STACK_REL_IND_Y            0x00100000UL
  81 #define AM65_IMM_ACCU           0x00200000UL
  82 #define AM65_IMM_INDEX          0x00400000UL
  83 #define AM65_IMM_IMPLICIT               0x00800000UL
  84 #define AM65_IMM                        (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT)
  85 #define AM65_BLOCKMOVE                  0x01000000UL
  86
  87 /* Bitmask for all ZP operations that have correspondent ABS ops */
  88 #define AM65_SET_ZP     (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
  89
  90 /* Bitmask for all ABS operations that have correspondent FAR ops */
  91 #define AM65_SET_ABS      (AM65_ABS | AM65_ABS_X)
  92
  93 /* Bit numbers and count */
  94 #define AM65I_IMM_ACCU          21
  95 #define AM65I_IMM_INDEX         22
  96 #define AM65I_COUNT             25
  97
  98
  99
 100 /* Description for one instruction */
 101 typedef struct InsDesc InsDesc;
 102 struct InsDesc {
 103     char                Mnemonic[5];
 104     unsigned long       AddrMode;               /* Valid adressing modes */
 105     unsigned char       BaseCode;               /* Base opcode */
 106     unsigned char       ExtCode;                /* Number of ext code table */
 107     void                (*Emit) (const InsDesc*);/* Handler function */
 108 };
 109
 110 /* An instruction table */
 111 typedef struct InsTable InsTable;
 112 struct InsTable {
 113     unsigned            Count;                  /* Number of intstructions */
 114     InsDesc             Ins[1];                 /* Varying length */
 115 };
 116
 117 /* The instruction table for the currently active CPU */
 118 extern const InsTable* InsTab;
 119
 120 /* Table that encodes the additional bytes for each instruction */
 121 extern unsigned char ExtBytes[AM65I_COUNT];
 122
 123
 124
 125 /*****************************************************************************/
 126 /*                      Data for the SWEET16 pseudo CPU                      */
 127 /*****************************************************************************/
 128
 129
 130
 131 /* SWEET16 addressing modes */
 132 #define AMSW16_IMP      0x0001          /* Implicit */
 133 #define AMSW16_BRA      0x0002          /* A branch */
 134 #define AMSW16_IMM      0x0004          /* Immediate */
 135 #define AMSW16_IND      0x0008          /* Indirect */
 136 #define AMSW16_REG      0x0010          /* Register */
 137
 138 #define AMSW16I_COUNT   5               /* Number of addressing modes */
 139
 140
 141
 142 /*****************************************************************************/
 143 /*                                   Code                                    */
 144 /*****************************************************************************/
 145
 146
 147
 148 void SetCPU (cpu_t NewCPU);
 149 /* Set a new CPU */
 150
 151 cpu_t GetCPU (void);
 152 /* Return the current CPU */
 153
 154 int FindInstruction (const char* Ident);
 155 /* Check if Ident is a valid mnemonic. If so, return the index in the
 156  * instruction table. If not, return -1.
 157  */
 158
 159 void HandleInstruction (unsigned Index);
 160 /* Handle the mnemonic with the given index */
 161
 162
 163
 164 /* End of instr.h */
 165
 166 #endif
 167
 168
 169
 170