1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
53 /* END ATMEL COPYRIGHT */
69 #include "time_support.h"
71 #define REG_NAME_WIDTH (12)
74 #define FLASH_BANK0_BASE 0x00080000
75 #define FLASH_BANK1_BASE 0x00100000
77 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
78 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
79 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
80 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
81 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
82 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
83 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
84 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
85 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
86 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
87 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
88 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
89 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
90 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
91 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
92 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
93 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
94 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
96 #define offset_EFC_FMR 0
97 #define offset_EFC_FCR 4
98 #define offset_EFC_FSR 8
99 #define offset_EFC_FRR 12
103 _tomhz(uint32_t freq_hz)
107 f = ((float)(freq_hz)) / 1000000.0;
111 // How the chip is configured.
113 uint32_t unique_id[4];
117 uint32_t mainosc_freq;
127 #define SAM3_CHIPID_CIDR (0x400E0740)
128 uint32_t CHIPID_CIDR;
129 #define SAM3_CHIPID_EXID (0x400E0744)
130 uint32_t CHIPID_EXID;
132 #define SAM3_SUPC_CR (0x400E1210)
135 #define SAM3_PMC_BASE (0x400E0400)
136 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
138 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
140 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
142 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
144 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
146 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
148 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
150 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
152 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
154 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
156 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
158 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
160 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
162 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
167 struct sam3_bank_private {
169 // DANGER: THERE ARE DRAGONS HERE..
170 // NOTE: If you add more 'ghost' pointers
171 // be aware that you must *manually* update
172 // these pointers in the function sam3_GetDetails()
173 // See the comment "Here there be dragons"
175 // so we can find the chip we belong to
176 struct sam3_chip *pChip;
177 // so we can find the orginal bank pointer
179 unsigned bank_number;
180 uint32_t controller_address;
181 uint32_t base_address;
185 unsigned sector_size;
189 struct sam3_chip_details {
190 // THERE ARE DRAGONS HERE..
191 // note: If you add pointers here
192 // becareful about them as they
193 // may need to be updated inside
194 // the function: "sam3_GetDetails()
195 // which copy/overwrites the
196 // 'runtime' copy of this structure
197 uint32_t chipid_cidr;
201 #define SAM3_N_NVM_BITS 3
202 unsigned gpnvm[SAM3_N_NVM_BITS];
203 unsigned total_flash_size;
204 unsigned total_sram_size;
206 #define SAM3_MAX_FLASH_BANKS 2
207 // these are "initialized" from the global const data
208 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
213 struct sam3_chip *next;
216 // this is "initialized" from the global const structure
217 struct sam3_chip_details details;
225 struct sam3_reg_list {
226 uint32_t address; size_t struct_offset; const char *name;
227 void (*explain_func)(struct sam3_chip *pInfo);
231 static struct sam3_chip *all_sam3_chips;
233 static struct sam3_chip *
234 get_current_sam3(struct command_context_s *cmd_ctx)
237 static struct sam3_chip *p;
239 t = get_current_target(cmd_ctx);
241 command_print(cmd_ctx, "No current target?");
247 // this should not happen
248 // the command is not registered until the chip is created?
249 command_print(cmd_ctx, "No SAM3 chips exist?");
254 if (p->target == t) {
259 command_print(cmd_ctx, "Cannot find SAM3 chip?");
264 // these are used to *initialize* the "pChip->details" structure.
265 static const struct sam3_chip_details all_sam3_details[] = {
267 .chipid_cidr = 0x28100960,
268 .name = "at91sam3u4e",
269 .total_flash_size = 256 * 1024,
270 .total_sram_size = 52 * 1024,
274 // System boots at address 0x0
275 // gpnvm[1] = selects boot code
277 // boot is via "SAMBA" (rom)
280 // Selection is via gpnvm[2]
283 // NOTE: banks 0 & 1 switch places
285 // Bank0 is the boot rom
287 // Bank1 is the boot rom
296 .base_address = FLASH_BANK0_BASE,
297 .controller_address = 0x400e0800,
299 .size_bytes = 128 * 1024,
311 .base_address = FLASH_BANK1_BASE,
312 .controller_address = 0x400e0a00,
314 .size_bytes = 128 * 1024,
323 .chipid_cidr = 0x281a0760,
324 .name = "at91sam3u2e",
325 .total_flash_size = 128 * 1024,
326 .total_sram_size = 36 * 1024,
330 // System boots at address 0x0
331 // gpnvm[1] = selects boot code
333 // boot is via "SAMBA" (rom)
336 // Selection is via gpnvm[2]
345 .base_address = FLASH_BANK0_BASE,
346 .controller_address = 0x400e0800,
348 .size_bytes = 128 * 1024,
362 .chipid_cidr = 0x28190560,
363 .name = "at91sam3u1e",
364 .total_flash_size = 64 * 1024,
365 .total_sram_size = 20 * 1024,
369 // System boots at address 0x0
370 // gpnvm[1] = selects boot code
372 // boot is via "SAMBA" (rom)
375 // Selection is via gpnvm[2]
386 .base_address = FLASH_BANK0_BASE,
387 .controller_address = 0x400e0800,
389 .size_bytes = 64 * 1024,
405 .chipid_cidr = 0x28000960,
406 .name = "at91sam3u4c",
407 .total_flash_size = 256 * 1024,
408 .total_sram_size = 52 * 1024,
412 // System boots at address 0x0
413 // gpnvm[1] = selects boot code
415 // boot is via "SAMBA" (rom)
418 // Selection is via gpnvm[2]
421 // NOTE: banks 0 & 1 switch places
423 // Bank0 is the boot rom
425 // Bank1 is the boot rom
434 .base_address = FLASH_BANK0_BASE,
435 .controller_address = 0x400e0800,
437 .size_bytes = 128 * 1024,
448 .base_address = FLASH_BANK1_BASE,
449 .controller_address = 0x400e0a00,
451 .size_bytes = 128 * 1024,
460 .chipid_cidr = 0x280a0760,
461 .name = "at91sam3u2c",
462 .total_flash_size = 128 * 1024,
463 .total_sram_size = 36 * 1024,
467 // System boots at address 0x0
468 // gpnvm[1] = selects boot code
470 // boot is via "SAMBA" (rom)
473 // Selection is via gpnvm[2]
482 .base_address = FLASH_BANK0_BASE,
483 .controller_address = 0x400e0800,
485 .size_bytes = 128 * 1024,
499 .chipid_cidr = 0x28090560,
500 .name = "at91sam3u1c",
501 .total_flash_size = 64 * 1024,
502 .total_sram_size = 20 * 1024,
506 // System boots at address 0x0
507 // gpnvm[1] = selects boot code
509 // boot is via "SAMBA" (rom)
512 // Selection is via gpnvm[2]
523 .base_address = FLASH_BANK0_BASE,
524 .controller_address = 0x400e0800,
526 .size_bytes = 64 * 1024,
549 /***********************************************************************
550 **********************************************************************
551 **********************************************************************
552 **********************************************************************
553 **********************************************************************
554 **********************************************************************/
555 /* *ATMEL* style code - from the SAM3 driver code */
558 * Get the current status of the EEFC and
559 * the value of some status bits (LOCKE, PROGE).
560 * @param pPrivate - info about the bank
561 * @param v - result goes here
564 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
567 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
568 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
570 ((unsigned int)((*v >> 2) & 1)),
571 ((unsigned int)((*v >> 1) & 1)),
572 ((unsigned int)((*v >> 0) & 1)));
578 * Get the result of the last executed command.
579 * @param pPrivate - info about the bank
580 * @param v - result goes here
583 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
587 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
591 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
596 EFC_StartCommand(struct sam3_bank_private *pPrivate,
597 unsigned command, unsigned argument)
606 // Check command & argument
609 case AT91C_EFC_FCMD_WP:
610 case AT91C_EFC_FCMD_WPL:
611 case AT91C_EFC_FCMD_EWP:
612 case AT91C_EFC_FCMD_EWPL:
613 // case AT91C_EFC_FCMD_EPL:
614 // case AT91C_EFC_FCMD_EPA:
615 case AT91C_EFC_FCMD_SLB:
616 case AT91C_EFC_FCMD_CLB:
617 n = (pPrivate->size_bytes / pPrivate->page_size);
619 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
623 case AT91C_EFC_FCMD_SFB:
624 case AT91C_EFC_FCMD_CFB:
625 if (argument >= pPrivate->pChip->details.n_gpnvms) {
626 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
627 pPrivate->pChip->details.n_gpnvms);
631 case AT91C_EFC_FCMD_GETD:
632 case AT91C_EFC_FCMD_EA:
633 case AT91C_EFC_FCMD_GLB:
634 case AT91C_EFC_FCMD_GFB:
635 case AT91C_EFC_FCMD_STUI:
636 case AT91C_EFC_FCMD_SPUI:
638 LOG_ERROR("Argument is meaningless for cmd: %d", command);
642 LOG_ERROR("Unknown command %d", command);
646 if (command == AT91C_EFC_FCMD_SPUI) {
647 // this is a very special situation.
648 // Situation (1) - error/retry - see below
649 // And we are being called recursively
650 // Situation (2) - normal, finished reading unique id
652 // it should be "ready"
653 EFC_GetStatus(pPrivate, &v);
659 // we have done this before
660 // the controller is not responding.
661 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
665 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
666 pPrivate->bank_number);
667 // we do that by issuing the *STOP* command
668 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
669 // above is recursive, and further recursion is blocked by
670 // if (command == AT91C_EFC_FCMD_SPUI) above
676 v = (0x5A << 24) | (argument << 8) | command;
677 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
678 r = target_write_u32(pPrivate->pBank->target,
679 pPrivate->controller_address + offset_EFC_FCR,
682 LOG_DEBUG("Error Write failed");
688 * Performs the given command and wait until its completion (or an error).
689 * @param pPrivate - info about the bank
690 * @param command - Command to perform.
691 * @param argument - Optional command argument.
692 * @param status - put command status bits here
695 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
703 long long ms_now, ms_end;
710 r = EFC_StartCommand(pPrivate, command, argument);
715 ms_end = 500 + timeval_ms();
719 r = EFC_GetStatus(pPrivate, &v);
723 ms_now = timeval_ms();
724 if (ms_now > ms_end) {
726 LOG_ERROR("Command timeout");
746 * Read the unique ID.
747 * @param pPrivate - info about the bank
748 * The unique ID is stored in the 'pPrivate' structure.
751 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
757 pPrivate->pChip->cfg.unique_id[0] = 0;
758 pPrivate->pChip->cfg.unique_id[1] = 0;
759 pPrivate->pChip->cfg.unique_id[2] = 0;
760 pPrivate->pChip->cfg.unique_id[3] = 0;
763 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
768 for (x = 0 ; x < 4 ; x++) {
769 r = target_read_u32(pPrivate->pChip->target,
770 pPrivate->pBank->base + (x * 4),
775 pPrivate->pChip->cfg.unique_id[x] = v;
778 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
779 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
781 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
782 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
783 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
784 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
790 * Erases the entire flash.
791 * @param pPrivate - the info about the bank.
794 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
797 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
803 * Gets current GPNVM state.
804 * @param pPrivate - info about the bank.
805 * @param gpnvm - GPNVM bit index.
806 * @param puthere - result stored here.
808 //------------------------------------------------------------------------------
810 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
816 if (pPrivate->bank_number != 0) {
817 LOG_ERROR("GPNVM only works with Bank0");
821 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
822 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
823 gpnvm,pPrivate->pChip->details.n_gpnvms);
828 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
834 r = EFC_GetResult(pPrivate, &v);
837 // Check if GPNVM is set
838 // get the bit and make it a 0/1
839 *puthere = (v >> gpnvm) & 1;
849 * Clears the selected GPNVM bit.
850 * @param pPrivate info about the bank
851 * @param gpnvm GPNVM index.
852 * @returns 0 if successful; otherwise returns an error code.
855 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
861 if (pPrivate->bank_number != 0) {
862 LOG_ERROR("GPNVM only works with Bank0");
866 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
867 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
868 gpnvm,pPrivate->pChip->details.n_gpnvms);
872 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
874 LOG_DEBUG("Failed: %d",r);
877 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
878 LOG_DEBUG("End: %d",r);
885 * Sets the selected GPNVM bit.
886 * @param pPrivate info about the bank
887 * @param gpnvm GPNVM index.
890 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
895 if (pPrivate->bank_number != 0) {
896 LOG_ERROR("GPNVM only works with Bank0");
900 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
901 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
902 gpnvm,pPrivate->pChip->details.n_gpnvms);
906 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
915 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
922 * Returns a bit field (at most 64) of locked regions within a page.
923 * @param pPrivate info about the bank
924 * @param v where to store locked bits
927 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
931 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
933 r = EFC_GetResult(pPrivate, v);
935 LOG_DEBUG("End: %d",r);
941 * Unlocks all the regions in the given address range.
942 * @param pPrivate info about the bank
943 * @param start_sector first sector to unlock
944 * @param end_sector last (inclusive) to unlock
948 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
949 unsigned start_sector,
955 uint32_t pages_per_sector;
957 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
959 /* Unlock all pages */
960 while (start_sector <= end_sector) {
961 pg = start_sector * pages_per_sector;
963 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
976 * @param pPrivate - info about the bank
977 * @param start_sector - first sector to lock
978 * @param end_sector - last sector (inclusive) to lock
981 FLASHD_Lock(struct sam3_bank_private *pPrivate,
982 unsigned start_sector,
987 uint32_t pages_per_sector;
990 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
993 while (start_sector <= end_sector) {
994 pg = start_sector * pages_per_sector;
996 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1006 /****** END SAM3 CODE ********/
1008 /* begin helpful debug code */
1011 sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
1015 if (pChip->mbuf == NULL) {
1019 membuf_vsprintf(pChip->mbuf, fmt, ap);
1023 // print the fieldname, the field value, in dec & hex, and return field value
1025 sam3_reg_fieldname(struct sam3_chip *pChip,
1026 const char *regname,
1035 // extract the field
1037 v = v & ((1 << width)-1);
1047 sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ",
1048 REG_NAME_WIDTH, regname,
1055 static const char _unknown[] = "unknown";
1056 static const char * const eproc_names[] = {
1075 #define nvpsize2 nvpsize // these two tables are identical
1076 static const char * const nvpsize[] = {
1089 "1024K bytes", // 12
1091 "2048K bytes", // 14
1096 static const char * const sramsize[] = {
1116 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1117 { 0x19, "AT91SAM9xx Series" },
1118 { 0x29, "AT91SAM9XExx Series" },
1119 { 0x34, "AT91x34 Series" },
1120 { 0x37, "CAP7 Series" },
1121 { 0x39, "CAP9 Series" },
1122 { 0x3B, "CAP11 Series" },
1123 { 0x40, "AT91x40 Series" },
1124 { 0x42, "AT91x42 Series" },
1125 { 0x55, "AT91x55 Series" },
1126 { 0x60, "AT91SAM7Axx Series" },
1127 { 0x61, "AT91SAM7AQxx Series" },
1128 { 0x63, "AT91x63 Series" },
1129 { 0x70, "AT91SAM7Sxx Series" },
1130 { 0x71, "AT91SAM7XCxx Series" },
1131 { 0x72, "AT91SAM7SExx Series" },
1132 { 0x73, "AT91SAM7Lxx Series" },
1133 { 0x75, "AT91SAM7Xxx Series" },
1134 { 0x76, "AT91SAM7SLxx Series" },
1135 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1136 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1137 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1138 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1139 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1140 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1141 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1142 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1143 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1144 { 0x92, "AT91x92 Series" },
1145 { 0xF0, "AT75Cxx Series" },
1150 static const char * const nvptype[] = {
1152 "romless or onchip flash", // 1
1153 "embedded flash memory", // 2
1154 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1155 "sram emulating flash", // 4
1162 static const char *_yes_or_no(uint32_t v)
1171 static const char * const _rc_freq[] = {
1172 "4 MHz", "8 MHz", "12 MHz", "reserved"
1176 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1181 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1182 sam3_sprintf(pChip, "(main xtal enabled: %s)\n",
1184 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1185 sam3_sprintf(pChip, "(main osc bypass: %s)\n",
1187 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1188 sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n",
1190 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1191 sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n",
1194 pChip->cfg.rc_freq = 0;
1198 pChip->cfg.rc_freq = 0;
1200 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1203 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1206 pChip->cfg.rc_freq = 12* 1000 * 1000;
1211 v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1212 sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n",
1213 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1214 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1215 sam3_sprintf(pChip, "(mainosc source: %s)\n",
1216 v ? "external xtal" : "internal RC");
1218 v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1219 sam3_sprintf(pChip, "(clock failure enabled: %s)\n",
1226 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1232 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1233 sam3_sprintf(pChip,"\n");
1235 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1236 sam3_sprintf(pChip, "%s\n", eproc_names[v]);
1238 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1239 sam3_sprintf(pChip, "%s\n", nvpsize[v]);
1241 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1242 sam3_sprintf(pChip, "%s\n", nvpsize2[v]);
1244 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1245 sam3_sprintf(pChip, "%s\n", sramsize[ v ]);
1247 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1249 for (x = 0 ; archnames[x].name ; x++) {
1250 if (v == archnames[x].value) {
1251 cp = archnames[x].name;
1256 sam3_sprintf(pChip, "%s\n", cp);
1258 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1259 sam3_sprintf(pChip, "%s\n", nvptype[ v ]);
1261 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1262 sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v));
1266 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1271 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1272 sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v));
1274 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1276 v = (v * pChip->cfg.slow_freq) / 16;
1277 pChip->cfg.mainosc_freq = v;
1279 sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1281 pChip->cfg.slow_freq / 1000,
1282 pChip->cfg.slow_freq % 1000);
1287 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1291 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1292 sam3_sprintf(pChip,"\n");
1293 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1294 sam3_sprintf(pChip,"\n");
1295 pChip->cfg.plla_freq = 0;
1297 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n");
1298 } else if (diva == 0) {
1299 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n");
1300 } else if (diva == 1) {
1301 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1302 sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n",
1303 _tomhz(pChip->cfg.plla_freq));
1309 sam3_explain_mckr(struct sam3_chip *pChip)
1311 uint32_t css, pres, fin = 0;
1313 const char *cp = NULL;
1315 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1318 fin = pChip->cfg.slow_freq;
1322 fin = pChip->cfg.mainosc_freq;
1326 fin = pChip->cfg.plla_freq;
1330 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1331 fin = 480 * 1000 * 1000;
1335 cp = "upll (*ERROR* UPLL is disabled)";
1343 sam3_sprintf(pChip, "%s (%3.03f Mhz)\n",
1346 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1347 switch (pres & 0x07) {
1350 cp = "selected clock";
1383 sam3_sprintf(pChip, "(%s)\n", cp);
1385 // sam3 has a *SINGLE* clock -
1386 // other at91 series parts have divisors for these.
1387 pChip->cfg.cpu_freq = fin;
1388 pChip->cfg.mclk_freq = fin;
1389 pChip->cfg.fclk_freq = fin;
1390 sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n",
1395 static struct sam3_chip *
1396 target2sam3(target_t *pTarget)
1398 struct sam3_chip *pChip;
1400 if (pTarget == NULL) {
1404 pChip = all_sam3_chips;
1406 if (pChip->target == pTarget) {
1407 break; // return below
1409 pChip = pChip->next;
1417 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1419 // this function exists to help
1420 // keep funky offsetof() errors
1421 // and casting from causing bugs
1423 // By using prototypes - we can detect what would
1424 // be casting errors.
1426 return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
1430 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1431 static const struct sam3_reg_list sam3_all_regs[] = {
1432 SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1433 SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1434 SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1435 SAM3_ENTRY(CKGR_UCKR , NULL),
1436 SAM3_ENTRY(PMC_FSMR , NULL),
1437 SAM3_ENTRY(PMC_FSPR , NULL),
1438 SAM3_ENTRY(PMC_IMR , NULL),
1439 SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1440 SAM3_ENTRY(PMC_PCK0 , NULL),
1441 SAM3_ENTRY(PMC_PCK1 , NULL),
1442 SAM3_ENTRY(PMC_PCK2 , NULL),
1443 SAM3_ENTRY(PMC_PCSR , NULL),
1444 SAM3_ENTRY(PMC_SCSR , NULL),
1445 SAM3_ENTRY(PMC_SR , NULL),
1446 SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1447 SAM3_ENTRY(CHIPID_EXID , NULL),
1448 SAM3_ENTRY(SUPC_CR, NULL),
1450 // TERMINATE THE LIST
1458 static struct sam3_bank_private *
1459 get_sam3_bank_private(flash_bank_t *bank)
1461 return (struct sam3_bank_private *)(bank->driver_priv);
1465 * Given a pointer to where it goes in the structure,
1466 * determine the register name, address from the all registers table.
1468 static const struct sam3_reg_list *
1469 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1471 const struct sam3_reg_list *pReg;
1473 pReg = &(sam3_all_regs[0]);
1474 while (pReg->name) {
1475 uint32_t *pPossible;
1477 // calculate where this one go..
1478 // it is "possibly" this register.
1480 pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1482 // well? Is it this register
1483 if (pPossible == goes_here) {
1491 // This is *TOTAL*PANIC* - we are totally screwed.
1492 LOG_ERROR("INVALID SAM3 REGISTER");
1498 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1500 const struct sam3_reg_list *pReg;
1503 pReg = sam3_GetReg(pChip, goes_here);
1508 r = target_read_u32(pChip->target, pReg->address, goes_here);
1509 if (r != ERROR_OK) {
1510 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1511 pReg->name, (unsigned)(pReg->address), r);
1519 sam3_ReadAllRegs(struct sam3_chip *pChip)
1522 const struct sam3_reg_list *pReg;
1524 pReg = &(sam3_all_regs[0]);
1525 while (pReg->name) {
1526 r = sam3_ReadThisReg(pChip,
1527 sam3_get_reg_ptr(&(pChip->cfg), pReg));
1528 if (r != ERROR_OK) {
1529 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1530 pReg->name, ((unsigned)(pReg->address)), r);
1542 sam3_GetInfo(struct sam3_chip *pChip)
1544 const struct sam3_reg_list *pReg;
1547 membuf_reset(pChip->mbuf);
1550 pReg = &(sam3_all_regs[0]);
1551 while (pReg->name) {
1553 LOG_DEBUG("Start: %s", pReg->name);
1554 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1555 sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n",
1560 if (pReg->explain_func) {
1561 (*(pReg->explain_func))(pChip);
1563 LOG_DEBUG("End: %s", pReg->name);
1566 sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1567 sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1568 sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1569 sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1570 sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1573 sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1574 pChip->cfg.unique_id[0],
1575 pChip->cfg.unique_id[1],
1576 pChip->cfg.unique_id[2],
1577 pChip->cfg.unique_id[3]);
1585 sam3_erase_check(struct flash_bank_s *bank)
1590 if (bank->target->state != TARGET_HALTED) {
1591 LOG_ERROR("Target not halted");
1592 return ERROR_TARGET_NOT_HALTED;
1594 if (0 == bank->num_sectors) {
1595 LOG_ERROR("Target: not supported/not probed\n");
1599 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1600 for (x = 0 ; x < bank->num_sectors ; x++) {
1601 bank->sectors[x].is_erased = 1;
1609 sam3_protect_check(struct flash_bank_s *bank)
1614 struct sam3_bank_private *pPrivate;
1617 if (bank->target->state != TARGET_HALTED) {
1618 LOG_ERROR("Target not halted");
1619 return ERROR_TARGET_NOT_HALTED;
1622 pPrivate = get_sam3_bank_private(bank);
1624 LOG_ERROR("no private for this bank?");
1627 if (!(pPrivate->probed)) {
1628 return ERROR_FLASH_BANK_NOT_PROBED;
1631 r = FLASHD_GetLockBits(pPrivate , &v);
1632 if (r != ERROR_OK) {
1633 LOG_DEBUG("Failed: %d",r);
1637 for (x = 0 ; x < pPrivate->nsectors ; x++) {
1638 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1645 sam3_flash_bank_command(struct command_context_s *cmd_ctx,
1649 struct flash_bank_s *bank)
1651 struct sam3_chip *pChip;
1653 pChip = all_sam3_chips;
1655 // is this an existing chip?
1657 if (pChip->target == bank->target) {
1660 pChip = pChip->next;
1664 // this is a *NEW* chip
1665 pChip = calloc(1, sizeof(struct sam3_chip));
1667 LOG_ERROR("NO RAM!");
1670 pChip->target = bank->target;
1672 pChip->next = all_sam3_chips;
1673 all_sam3_chips = pChip;
1674 pChip->target = bank->target;
1675 // assumption is this runs at 32khz
1676 pChip->cfg.slow_freq = 32768;
1678 pChip->mbuf = membuf_new();
1679 if (!(pChip->mbuf)) {
1680 LOG_ERROR("no memory");
1685 switch (bank->base) {
1687 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1688 ((unsigned int)(bank->base)),
1689 ((unsigned int)(FLASH_BANK0_BASE)),
1690 ((unsigned int)(FLASH_BANK1_BASE)));
1693 case FLASH_BANK0_BASE:
1694 bank->driver_priv = &(pChip->details.bank[0]);
1695 bank->bank_number = 0;
1696 pChip->details.bank[0].pChip = pChip;
1697 pChip->details.bank[0].pBank = bank;
1699 case FLASH_BANK1_BASE:
1700 bank->driver_priv = &(pChip->details.bank[1]);
1701 bank->bank_number = 1;
1702 pChip->details.bank[1].pChip = pChip;
1703 pChip->details.bank[1].pBank = bank;
1707 // we initialize after probing.
1712 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1714 const struct sam3_chip_details *pDetails;
1715 struct sam3_chip *pChip;
1717 flash_bank_t *saved_banks[SAM3_MAX_FLASH_BANKS];
1723 pDetails = all_sam3_details;
1724 while (pDetails->name) {
1725 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
1731 if (pDetails->name == NULL) {
1732 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1733 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1734 // Help the victim, print details about the chip
1735 membuf_reset(pPrivate->pChip->mbuf);
1736 membuf_sprintf(pPrivate->pChip->mbuf,
1737 "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1738 pPrivate->pChip->cfg.CHIPID_CIDR);
1739 sam3_explain_chipid_cidr(pPrivate->pChip);
1740 cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
1743 cp = membuf_strtok(NULL, "\n", &vp);
1748 // DANGER: THERE ARE DRAGONS HERE
1750 // get our pChip - it is going
1751 // to be over-written shortly
1752 pChip = pPrivate->pChip;
1754 // Note that, in reality:
1756 // pPrivate = &(pChip->details.bank[0])
1757 // or pPrivate = &(pChip->details.bank[1])
1760 // save the "bank" pointers
1761 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1762 saved_banks[ x ] = pChip->details.bank[x].pBank;
1765 // Overwrite the "details" structure.
1766 memcpy(&(pPrivate->pChip->details),
1768 sizeof(pPrivate->pChip->details));
1770 // now fix the ghosted pointers
1771 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1772 pChip->details.bank[x].pChip = pChip;
1773 pChip->details.bank[x].pBank = saved_banks[x];
1776 // update the *BANK*SIZE*
1785 _sam3_probe(struct flash_bank_s *bank, int noise)
1789 struct sam3_bank_private *pPrivate;
1792 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1793 if (bank->target->state != TARGET_HALTED)
1795 LOG_ERROR("Target not halted");
1796 return ERROR_TARGET_NOT_HALTED;
1799 pPrivate = get_sam3_bank_private(bank);
1801 LOG_ERROR("Invalid/unknown bank number\n");
1805 r = sam3_ReadAllRegs(pPrivate->pChip);
1806 if (r != ERROR_OK) {
1812 r = sam3_GetInfo(pPrivate->pChip);
1813 if (r != ERROR_OK) {
1816 if (!(pPrivate->pChip->probed)) {
1817 pPrivate->pChip->probed = 1;
1819 r = sam3_GetDetails(pPrivate);
1820 if (r != ERROR_OK) {
1825 // update the flash bank size
1826 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1827 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
1828 bank->size = pPrivate->pChip->details.bank[0].size_bytes;
1833 if (bank->sectors == NULL) {
1834 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1835 if (bank->sectors == NULL) {
1836 LOG_ERROR("No memory!");
1839 bank->num_sectors = pPrivate->nsectors;
1841 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
1842 bank->sectors[x].size = pPrivate->sector_size;
1843 bank->sectors[x].offset = x * (pPrivate->sector_size);
1845 bank->sectors[x].is_erased = -1;
1846 bank->sectors[x].is_protected = -1;
1850 pPrivate->probed = 1;
1852 r = sam3_protect_check(bank);
1853 if (r != ERROR_OK) {
1857 LOG_DEBUG("Bank = %d, nbanks = %d",
1858 pPrivate->bank_number , pPrivate->pChip->details.n_banks);
1859 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1861 // it appears to be associated with the *last* flash bank.
1862 FLASHD_ReadUniqueID(pPrivate);
1869 sam3_probe(struct flash_bank_s *bank)
1871 return _sam3_probe(bank, 1);
1875 sam3_auto_probe(struct flash_bank_s *bank)
1877 return _sam3_probe(bank, 0);
1883 sam3_erase(struct flash_bank_s *bank, int first, int last)
1885 struct sam3_bank_private *pPrivate;
1889 if (bank->target->state != TARGET_HALTED) {
1890 LOG_ERROR("Target not halted");
1891 return ERROR_TARGET_NOT_HALTED;
1894 r = sam3_auto_probe(bank);
1895 if (r != ERROR_OK) {
1896 LOG_DEBUG("Here,r=%d",r);
1900 pPrivate = get_sam3_bank_private(bank);
1901 if (!(pPrivate->probed)) {
1902 return ERROR_FLASH_BANK_NOT_PROBED;
1905 if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
1908 return FLASHD_EraseEntireBank(pPrivate);
1910 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1915 sam3_protect(struct flash_bank_s *bank, int set, int first, int last)
1917 struct sam3_bank_private *pPrivate;
1921 if (bank->target->state != TARGET_HALTED) {
1922 LOG_ERROR("Target not halted");
1923 return ERROR_TARGET_NOT_HALTED;
1926 pPrivate = get_sam3_bank_private(bank);
1927 if (!(pPrivate->probed)) {
1928 return ERROR_FLASH_BANK_NOT_PROBED;
1932 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1934 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1936 LOG_DEBUG("End: r=%d",r);
1944 sam3_info(flash_bank_t *bank, char *buf, int buf_size)
1946 if (bank->target->state != TARGET_HALTED) {
1947 LOG_ERROR("Target not halted");
1948 return ERROR_TARGET_NOT_HALTED;
1955 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1960 adr = pagenum * pPrivate->page_size;
1961 adr += adr + pPrivate->base_address;
1963 r = target_read_memory(pPrivate->pChip->target,
1965 4, /* THIS*MUST*BE* in 32bit values */
1966 pPrivate->page_size / 4,
1968 if (r != ERROR_OK) {
1969 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
1974 // The code below is basically this:
1976 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
1978 // Only the *CPU* can write to the flash buffer.
1979 // the DAP cannot... so - we download this 28byte thing
1980 // Run the algorithm - (below)
1981 // to program the device
1983 // ========================================
1984 // #include <stdint.h>
1988 // const uint32_t *src;
1990 // volatile uint32_t *base;
1995 // uint32_t sam3_function(struct foo *p)
1997 // volatile uint32_t *v;
1999 // const uint32_t *s;
2021 // ========================================
2025 static const uint8_t
2026 sam3_page_write_opcodes[] = {
2027 // 24 0000 0446 mov r4, r0
2029 // 25 0002 6168 ldr r1, [r4, #4]
2031 // 26 0004 0068 ldr r0, [r0, #0]
2033 // 27 0006 A268 ldr r2, [r4, #8]
2035 // 28 @ lr needed for prologue
2037 // 30 0008 51F8043B ldr r3, [r1], #4
2038 0x51,0xf8,0x04,0x3b,
2039 // 31 000c 12F1FF32 adds r2, r2, #-1
2040 0x12,0xf1,0xff,0x32,
2041 // 32 0010 40F8043B str r3, [r0], #4
2042 0x40,0xf8,0x04,0x3b,
2043 // 33 0014 F8D1 bne .L2
2045 // 34 0016 E268 ldr r2, [r4, #12]
2047 // 35 0018 2369 ldr r3, [r4, #16]
2049 // 36 001a 5360 str r3, [r2, #4]
2051 // 37 001c 0832 adds r2, r2, #8
2054 // 39 001e 1068 ldr r0, [r2, #0]
2056 // 40 0020 10F0010F tst r0, #1
2057 0x10,0xf0,0x01,0x0f,
2058 // 41 0024 FBD0 beq .L4
2061 // 43 0026 FEE7 b .done
2067 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2073 adr = pagenum * pPrivate->page_size;
2074 adr += (adr + pPrivate->base_address);
2076 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2077 r = target_write_memory(pPrivate->pChip->target,
2079 4, /* THIS*MUST*BE* in 32bit values */
2080 pPrivate->page_size / 4,
2082 if (r != ERROR_OK) {
2083 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2087 r = EFC_PerformCommand(pPrivate,
2088 // send Erase & Write Page
2093 if (r != ERROR_OK) {
2094 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2096 if (status & (1 << 2)) {
2097 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2100 if (status & (1 << 1)) {
2101 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2112 sam3_write(struct flash_bank_s *bank,
2121 unsigned page_offset;
2122 struct sam3_bank_private *pPrivate;
2123 uint8_t *pagebuffer;
2125 // incase we bail further below, set this to null
2128 // ignore dumb requests
2134 if (bank->target->state != TARGET_HALTED) {
2135 LOG_ERROR("Target not halted");
2136 r = ERROR_TARGET_NOT_HALTED;
2140 pPrivate = get_sam3_bank_private(bank);
2141 if (!(pPrivate->probed)) {
2142 r = ERROR_FLASH_BANK_NOT_PROBED;
2147 if ((offset + count) > pPrivate->size_bytes) {
2148 LOG_ERROR("Flash write error - past end of bank");
2149 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2150 (unsigned int)(offset),
2151 (unsigned int)(count),
2152 (unsigned int)(pPrivate->size_bytes));
2157 pagebuffer = malloc(pPrivate->page_size);
2159 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2164 // what page do we start & end in?
2165 page_cur = offset / pPrivate->page_size;
2166 page_end = (offset + count - 1) / pPrivate->page_size;
2168 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2169 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2171 // Special case: all one page
2174 // (1) non-aligned start
2176 // (3) non-aligned end.
2178 // Handle special case - all one page.
2179 if (page_cur == page_end) {
2180 LOG_DEBUG("Special case, all in one page");
2181 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2182 if (r != ERROR_OK) {
2186 page_offset = (offset & (pPrivate->page_size-1));
2187 memcpy(pagebuffer + page_offset,
2191 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2192 if (r != ERROR_OK) {
2199 // non-aligned start
2200 page_offset = offset & (pPrivate->page_size - 1);
2202 LOG_DEBUG("Not-Aligned start");
2204 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2205 if (r != ERROR_OK) {
2209 // over-write with new data
2210 n = (pPrivate->page_size - page_offset);
2211 memcpy(pagebuffer + page_offset,
2215 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2216 if (r != ERROR_OK) {
2226 // intermediate large pages
2227 // also - the final *terminal*
2228 // if that terminal page is a full page
2229 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2230 (int)page_cur, (int)page_end, (unsigned int)(count));
2232 while ((page_cur < page_end) &&
2233 (count >= pPrivate->page_size)) {
2234 r = sam3_page_write(pPrivate, page_cur, buffer);
2235 if (r != ERROR_OK) {
2238 count -= pPrivate->page_size;
2239 buffer += pPrivate->page_size;
2243 // terminal partial page?
2245 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2246 // we have a partial page
2247 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2248 if (r != ERROR_OK) {
2251 // data goes at start
2252 memcpy(pagebuffer, buffer, count);
2253 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2254 if (r != ERROR_OK) {
2269 COMMAND_HANDLER(sam3_handle_info_command)
2271 struct sam3_chip *pChip;
2277 pChip = get_current_sam3(cmd_ctx);
2284 // bank0 must exist before we can do anything
2285 if (pChip->details.bank[0].pBank == NULL) {
2288 command_print(cmd_ctx,
2289 "Please define bank %d via command: flash bank %s ... ",
2291 at91sam3_flash.name);
2295 // if bank 0 is not probed, then probe it
2296 if (!(pChip->details.bank[0].probed)) {
2297 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2298 if (r != ERROR_OK) {
2302 // above garentees the "chip details" structure is valid
2303 // and thus, bank private areas are valid
2304 // and we have a SAM3 chip, what a concept!
2307 // auto-probe other banks, 0 done above
2308 for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2309 // skip banks not present
2310 if (!(pChip->details.bank[x].present)) {
2314 if (pChip->details.bank[x].pBank == NULL) {
2318 if (pChip->details.bank[x].probed) {
2322 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2323 if (r != ERROR_OK) {
2329 r = sam3_GetInfo(pChip);
2330 if (r != ERROR_OK) {
2331 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2337 cp = membuf_strtok(pChip->mbuf, "\n", &vp);
2339 command_print(cmd_ctx,"%s", cp);
2340 cp = membuf_strtok(NULL, "\n", &vp);
2345 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2349 struct sam3_chip *pChip;
2351 pChip = get_current_sam3(cmd_ctx);
2356 if (pChip->target->state != TARGET_HALTED) {
2357 LOG_ERROR("sam3 - target not halted");
2358 return ERROR_TARGET_NOT_HALTED;
2362 if (pChip->details.bank[0].pBank == NULL) {
2363 command_print(cmd_ctx, "Bank0 must be defined first via: flash bank %s ...",
2364 at91sam3_flash.name);
2367 if (!pChip->details.bank[0].probed) {
2368 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2369 if (r != ERROR_OK) {
2377 command_print(cmd_ctx,"Too many parameters\n");
2378 return ERROR_COMMAND_SYNTAX_ERROR;
2388 if ((0 == strcmp(args[0], "show")) && (0 == strcmp(args[1], "all"))) {
2392 COMMAND_PARSE_NUMBER(u32, args[1], v32);
2398 if (0 == strcmp("show", args[0])) {
2402 for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2403 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2404 if (r != ERROR_OK) {
2407 command_print(cmd_ctx, "sam3-gpnvm%u: %u", x, v);
2411 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2412 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2413 command_print(cmd_ctx, "sam3-gpnvm%u: %u", who, v);
2416 command_print(cmd_ctx, "sam3-gpnvm invalid GPNVM: %u", who);
2417 return ERROR_COMMAND_SYNTAX_ERROR;
2422 command_print(cmd_ctx, "Missing GPNVM number");
2423 return ERROR_COMMAND_SYNTAX_ERROR;
2426 if (0 == strcmp("set", args[0])) {
2427 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2428 } else if ((0 == strcmp("clr", args[0])) ||
2429 (0 == strcmp("clear", args[0]))) { // quietly accept both
2430 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2432 command_print(cmd_ctx, "Unkown command: %s", args[0]);
2433 r = ERROR_COMMAND_SYNTAX_ERROR;
2438 COMMAND_HANDLER(sam3_handle_slowclk_command)
2440 struct sam3_chip *pChip;
2442 pChip = get_current_sam3(cmd_ctx);
2456 COMMAND_PARSE_NUMBER(u32, args[0], v);
2458 // absurd slow clock of 200Khz?
2459 command_print(cmd_ctx,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2460 return ERROR_COMMAND_SYNTAX_ERROR;
2462 pChip->cfg.slow_freq = v;
2467 command_print(cmd_ctx,"Too many parameters");
2468 return ERROR_COMMAND_SYNTAX_ERROR;
2471 command_print(cmd_ctx, "Slowclk freq: %d.%03dkhz",
2472 (int)(pChip->cfg.slow_freq/ 1000),
2473 (int)(pChip->cfg.slow_freq% 1000));
2478 static int sam3_registered;
2480 sam3_register_commands(struct command_context_s *cmd_ctx)
2484 // only register once
2485 if (!sam3_registered) {
2488 pCmd = register_command(cmd_ctx, NULL, "at91sam3", NULL, COMMAND_ANY, NULL);
2489 register_command(cmd_ctx, pCmd,
2491 sam3_handle_gpnvm_command,
2493 "at91sam3 gpnvm [action [<BIT>], by default 'show', otherwise set | clear BIT");
2494 register_command(cmd_ctx, pCmd,
2496 sam3_handle_info_command,
2498 "at91sam3 info - print information about the current sam3 chip");
2499 register_command(cmd_ctx, pCmd,
2501 sam3_handle_slowclk_command,
2503 "at91sam3 slowclk [VALUE] set the slowclock frequency (default 32768hz)");
2508 flash_driver_t at91sam3_flash = {
2510 .register_commands = &sam3_register_commands,
2511 .flash_bank_command = &sam3_flash_bank_command,
2512 .erase = &sam3_erase,
2513 .protect = &sam3_protect,
2514 .write = &sam3_write,
2515 .probe = &sam3_probe,
2516 .auto_probe = &sam3_auto_probe,
2517 .erase_check = &sam3_erase_check,
2518 .protect_check = &sam3_protect_check,