git.sur5r.net Git - openocd/blob - src/flash/cfi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28 #include "armv4_5.h"
  29 #include "binarybuffer.h"
  30
  31
  32 static int cfi_register_commands(struct command_context_s *cmd_ctx);
  33 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  34 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
  35 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  36 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  37 static int cfi_probe(struct flash_bank_s *bank);
  38 static int cfi_auto_probe(struct flash_bank_s *bank);
  39 static int cfi_protect_check(struct flash_bank_s *bank);
  40 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  41
  42 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 #define CFI_MAX_BUS_WIDTH       4
  45 #define CFI_MAX_CHIP_WIDTH      4
  46
  47 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  48 #define CFI_MAX_INTEL_CODESIZE 256
  49
  50 flash_driver_t cfi_flash =
  51 {
  52         .name = "cfi",
  53         .register_commands = cfi_register_commands,
  54         .flash_bank_command = cfi_flash_bank_command,
  55         .erase = cfi_erase,
  56         .protect = cfi_protect,
  57         .write = cfi_write,
  58         .probe = cfi_probe,
  59         .auto_probe = cfi_auto_probe,
  60         .erase_check = default_flash_blank_check,
  61         .protect_check = cfi_protect_check,
  62         .info = cfi_info
  63 };
  64
  65 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
  66 {
  67         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  68         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  69 };
  70
  71 /* CFI fixups foward declarations */
  72 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  73 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  74 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  75
  76 /* fixup after reading cmdset 0002 primary query table */
  77 static cfi_fixup_t cfi_0002_fixups[] = {
  78         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  79         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  80         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  81         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  82         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  83         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  84         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  85         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  86         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  87         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  88         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  89         {0, 0, NULL, NULL}
  90 };
  91
  92 /* fixup after reading cmdset 0001 primary query table */
  93 static cfi_fixup_t cfi_0001_fixups[] = {
  94         {0, 0, NULL, NULL}
  95 };
  96
  97 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
  98 {
  99         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 100         cfi_fixup_t *f;
 101
 102         for (f = fixups; f->fixup; f++)
 103         {
 104                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 105                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 106                 {
 107                         f->fixup(bank, f->param);
 108                 }
 109         }
 110 }
 111
 112 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 113 static __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 114 {
 115         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 116
 117         if(cfi_info->x16_as_x8) offset*=2;
 118
 119         /* while the sector list isn't built, only accesses to sector 0 work */
 120         if (sector == 0)
 121                 return bank->base + offset * bank->bus_width;
 122         else
 123         {
 124                 if (!bank->sectors)
 125                 {
 126                         LOG_ERROR("BUG: sector list not yet built");
 127                         exit(-1);
 128                 }
 129                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 130         }
 131
 132 }
 133
 134 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 135 {
 136         int i;
 137
 138         /* clear whole buffer, to ensure bits that exceed the bus_width
 139          * are set to zero
 140          */
 141         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 142                 cmd_buf[i] = 0;
 143
 144         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 145         {
 146                 for (i = bank->bus_width; i > 0; i--)
 147                 {
 148                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 149                 }
 150         }
 151         else
 152         {
 153                 for (i = 1; i <= bank->bus_width; i++)
 154                 {
 155                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 156                 }
 157         }
 158 }
 159
 160 /* read unsigned 8-bit value from the bank
 161  * flash banks are expected to be made of similar chips
 162  * the query result should be the same for all
 163  */
 164 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 165 {
 166         target_t *target = bank->target;
 167         u8 data[CFI_MAX_BUS_WIDTH];
 168
 169         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 170
 171         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 172                 return data[0];
 173         else
 174                 return data[bank->bus_width - 1];
 175 }
 176
 177 /* read unsigned 8-bit value from the bank
 178  * in case of a bank made of multiple chips,
 179  * the individual values are ORed
 180  */
 181 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 182 {
 183         target_t *target = bank->target;
 184         u8 data[CFI_MAX_BUS_WIDTH];
 185         int i;
 186
 187         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 188
 189         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 190         {
 191                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 192                         data[0] |= data[i];
 193
 194                 return data[0];
 195         }
 196         else
 197         {
 198                 u8 value = 0;
 199                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 200                         value |= data[bank->bus_width - 1 - i];
 201
 202                 return value;
 203         }
 204 }
 205
 206 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 207 {
 208         target_t *target = bank->target;
 209         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 210         u8 data[CFI_MAX_BUS_WIDTH * 2];
 211
 212         if(cfi_info->x16_as_x8)
 213         {
 214                 u8 i;
 215                 for(i=0;i<2;i++)
 216                         target_read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
 217                                 &data[i*bank->bus_width] );
 218         }
 219         else
 220                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 221
 222         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 223                 return data[0] | data[bank->bus_width] << 8;
 224         else
 225                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 226 }
 227
 228 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 229 {
 230         target_t *target = bank->target;
 231         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 232         u8 data[CFI_MAX_BUS_WIDTH * 4];
 233
 234         if(cfi_info->x16_as_x8)
 235         {
 236                 u8 i;
 237                 for(i=0;i<4;i++)
 238                         target_read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
 239                                 &data[i*bank->bus_width] );
 240         }
 241         else
 242                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 243
 244         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 245                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 246         else
 247                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 248                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 249 }
 250
 251 static void cfi_intel_clear_status_register(flash_bank_t *bank)
 252 {
 253         target_t *target = bank->target;
 254         u8 command[8];
 255
 256         if (target->state != TARGET_HALTED)
 257         {
 258                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 259                 exit(-1);
 260         }
 261
 262         cfi_command(bank, 0x50, command);
 263         target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 264 }
 265
 266 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 267 {
 268         u8 status;
 269
 270         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 271         {
 272                 LOG_DEBUG("status: 0x%x", status);
 273                 alive_sleep(1);
 274         }
 275
 276         /* mask out bit 0 (reserved) */
 277         status = status & 0xfe;
 278
 279         LOG_DEBUG("status: 0x%x", status);
 280
 281         if ((status & 0x80) != 0x80)
 282         {
 283                 LOG_ERROR("timeout while waiting for WSM to become ready");
 284         }
 285         else if (status != 0x80)
 286         {
 287                 LOG_ERROR("status register: 0x%x", status);
 288                 if (status & 0x2)
 289                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 290                 if (status & 0x4)
 291                         LOG_ERROR("Program suspended");
 292                 if (status & 0x8)
 293                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 294                 if (status & 0x10)
 295                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 296                 if (status & 0x20)
 297                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 298                 if (status & 0x40)
 299                         LOG_ERROR("Block Erase Suspended");
 300
 301                 cfi_intel_clear_status_register(bank);
 302         }
 303
 304         return status;
 305 }
 306
 307 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 308 {
 309         u8 status, oldstatus;
 310         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 311
 312         oldstatus = cfi_get_u8(bank, 0, 0x0);
 313
 314         do {
 315                 status = cfi_get_u8(bank, 0, 0x0);
 316                 if ((status ^ oldstatus) & 0x40) {
 317                         if (status & cfi_info->status_poll_mask & 0x20) {
 318                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 319                                 status = cfi_get_u8(bank, 0, 0x0);
 320                                 if ((status ^ oldstatus) & 0x40) {
 321                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 322                                         return(ERROR_FLASH_OPERATION_FAILED);
 323                                 } else {
 324                                         LOG_DEBUG("status: 0x%x", status);
 325                                         return(ERROR_OK);
 326                                 }
 327                         }
 328                 } else { /* no toggle: finished, OK */
 329                         LOG_DEBUG("status: 0x%x", status);
 330                         return(ERROR_OK);
 331                 }
 332
 333                 oldstatus = status;
 334                 alive_sleep(1);
 335         } while (timeout-- > 0);
 336
 337         LOG_ERROR("timeout, status: 0x%x", status);
 338
 339         return(ERROR_FLASH_BUSY);
 340 }
 341
 342 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
 343 {
 344         int retval;
 345         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 346         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 347         target_t *target = bank->target;
 348         u8 command[8];
 349
 350         cfi_info->pri_ext = pri_ext;
 351
 352         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 353         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 354         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 355
 356         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 357         {
 358                 cfi_command(bank, 0xf0, command);
 359                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 360                 {
 361                         return retval;
 362                 }
 363                 cfi_command(bank, 0xff, command);
 364                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 365                 {
 366                         return retval;
 367                 }
 368                 LOG_ERROR("Could not read bank flash bank information");
 369                 return ERROR_FLASH_BANK_INVALID;
 370         }
 371
 372         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 373         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 374
 375         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 376
 377         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 378         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 379         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 380
 381         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 382
 383         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 384         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 385
 386         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 387                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 388                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 389
 390         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 391         if (pri_ext->num_protection_fields != 1)
 392         {
 393                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 394         }
 395
 396         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 397         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 398         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 399
 400         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 401
 402         return ERROR_OK;
 403 }
 404
 405 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 406 {
 407         int retval;
 408         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 409         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 410         target_t *target = bank->target;
 411         u8 command[8];
 412
 413         cfi_info->pri_ext = pri_ext;
 414
 415         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 416         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 417         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 418
 419         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 420         {
 421                 cfi_command(bank, 0xf0, command);
 422                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 423                 {
 424                         return retval;
 425                 }
 426                 LOG_ERROR("Could not read spansion bank information");
 427                 return ERROR_FLASH_BANK_INVALID;
 428         }
 429
 430         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 431         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 432
 433         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 434
 435         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 436         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 437         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 438         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 439         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 440         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 441         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 442         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 443         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 444         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 445         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 446
 447         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 448               pri_ext->EraseSuspend, pri_ext->BlkProt);
 449
 450         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 451               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 452
 453         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 454
 455
 456         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 457                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 458                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 459
 460         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 461
 462         /* default values for implementation specific workarounds */
 463         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 464         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 465         pri_ext->_reversed_geometry = 0;
 466
 467         return ERROR_OK;
 468 }
 469
 470 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 471 {
 472         int retval;
 473         cfi_atmel_pri_ext_t atmel_pri_ext;
 474         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 475         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 476         target_t *target = bank->target;
 477         u8 command[8];
 478
 479         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 480          * but a different primary extended query table.
 481          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 482          */
 483
 484         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 485
 486         cfi_info->pri_ext = pri_ext;
 487
 488         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 489         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 490         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 491
 492         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 493         {
 494                 cfi_command(bank, 0xf0, command);
 495                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 496                 {
 497                         return retval;
 498                 }
 499                 LOG_ERROR("Could not read atmel bank information");
 500                 return ERROR_FLASH_BANK_INVALID;
 501         }
 502
 503         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 504         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 505         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 506
 507         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 508         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 509
 510         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 511
 512         pri_ext->major_version = atmel_pri_ext.major_version;
 513         pri_ext->minor_version = atmel_pri_ext.minor_version;
 514
 515         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 516         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 517         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 518         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 519
 520         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 521                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 522
 523         if (atmel_pri_ext.features & 0x02)
 524                 pri_ext->EraseSuspend = 2;
 525
 526         if (atmel_pri_ext.bottom_boot)
 527                 pri_ext->TopBottom = 2;
 528         else
 529                 pri_ext->TopBottom = 3;
 530
 531         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 532         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 533
 534         return ERROR_OK;
 535 }
 536
 537 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
 538 {
 539         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 540
 541         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 542         {
 543                 return cfi_read_atmel_pri_ext(bank);
 544         }
 545         else
 546         {
 547                 return cfi_read_spansion_pri_ext(bank);
 548         }
 549 }
 550
 551 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 552 {
 553         int printed;
 554         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 555         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 556
 557         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 558         buf += printed;
 559         buf_size -= printed;
 560
 561         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 562                            pri_ext->pri[1], pri_ext->pri[2],
 563                            pri_ext->major_version, pri_ext->minor_version);
 564         buf += printed;
 565         buf_size -= printed;
 566
 567         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 568                            (pri_ext->SiliconRevision) >> 2,
 569                            (pri_ext->SiliconRevision) & 0x03);
 570         buf += printed;
 571         buf_size -= printed;
 572
 573         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 574                            pri_ext->EraseSuspend,
 575                            pri_ext->BlkProt);
 576         buf += printed;
 577         buf_size -= printed;
 578
 579         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 580                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 581                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 582
 583         return ERROR_OK;
 584 }
 585
 586 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 587 {
 588         int printed;
 589         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 590         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 591
 592         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 593         buf += printed;
 594         buf_size -= printed;
 595
 596         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 597         buf += printed;
 598         buf_size -= printed;
 599
 600         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 601         buf += printed;
 602         buf_size -= printed;
 603
 604         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 605                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 606                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 607         buf += printed;
 608         buf_size -= printed;
 609
 610         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 611
 612         return ERROR_OK;
 613 }
 614
 615 static int cfi_register_commands(struct command_context_s *cmd_ctx)
 616 {
 617         /*command_t *cfi_cmd = */
 618         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 619         /*
 620         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 621                                          "print part id of cfi flash bank <num>");
 622         */
 623         return ERROR_OK;
 624 }
 625
 626 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 627  */
 628 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 629 {
 630         cfi_flash_bank_t *cfi_info;
 631         int i;
 632         (void) cmd_ctx;
 633         (void) cmd;
 634
 635         if (argc < 6)
 636         {
 637                 LOG_WARNING("incomplete flash_bank cfi configuration");
 638                 return ERROR_FLASH_BANK_INVALID;
 639         }
 640
 641         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 642                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 643         {
 644                 LOG_ERROR("chip and bus width have to specified in bytes");
 645                 return ERROR_FLASH_BANK_INVALID;
 646         }
 647
 648         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 649         cfi_info->probed = 0;
 650         bank->driver_priv = cfi_info;
 651
 652         cfi_info->write_algorithm = NULL;
 653
 654         cfi_info->x16_as_x8 = 0;
 655         cfi_info->jedec_probe = 0;
 656         cfi_info->not_cfi = 0;
 657
 658         for (i = 6; i < argc; i++)
 659         {
 660                 if (strcmp(args[i], "x16_as_x8") == 0)
 661                 {
 662                         cfi_info->x16_as_x8 = 1;
 663                 }
 664                 else if (strcmp(args[i], "jedec_probe") == 0)
 665                 {
 666                         cfi_info->jedec_probe = 1;
 667                 }
 668         }
 669
 670         cfi_info->write_algorithm = NULL;
 671
 672         /* bank wasn't probed yet */
 673         cfi_info->qry[0] = -1;
 674
 675         return ERROR_OK;
 676 }
 677
 678 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 679 {
 680         int retval;
 681         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 682         target_t *target = bank->target;
 683         u8 command[8];
 684         int i;
 685
 686         cfi_intel_clear_status_register(bank);
 687
 688         for (i = first; i <= last; i++)
 689         {
 690                 cfi_command(bank, 0x20, command);
 691                 if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 692                 {
 693                         return retval;
 694                 }
 695
 696                 cfi_command(bank, 0xd0, command);
 697                 if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 698                 {
 699                         return retval;
 700                 }
 701
 702                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 703                         bank->sectors[i].is_erased = 1;
 704                 else
 705                 {
 706                         cfi_command(bank, 0xff, command);
 707                         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 708                         {
 709                                 return retval;
 710                         }
 711
 712                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 713                         return ERROR_FLASH_OPERATION_FAILED;
 714                 }
 715         }
 716
 717         cfi_command(bank, 0xff, command);
 718         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 719
 720 }
 721
 722 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 723 {
 724         int retval;
 725         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 726         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 727         target_t *target = bank->target;
 728         u8 command[8];
 729         int i;
 730
 731         for (i = first; i <= last; i++)
 732         {
 733                 cfi_command(bank, 0xaa, command);
 734                 if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 735                 {
 736                         return retval;
 737                 }
 738
 739                 cfi_command(bank, 0x55, command);
 740                 if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 741                 {
 742                         return retval;
 743                 }
 744
 745                 cfi_command(bank, 0x80, command);
 746                 if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 747                 {
 748                         return retval;
 749                 }
 750
 751                 cfi_command(bank, 0xaa, command);
 752                 if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 753                 {
 754                         return retval;
 755                 }
 756
 757                 cfi_command(bank, 0x55, command);
 758                 if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 759                 {
 760                         return retval;
 761                 }
 762
 763                 cfi_command(bank, 0x30, command);
 764                 if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 765                 {
 766                         return retval;
 767                 }
 768
 769                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 770                         bank->sectors[i].is_erased = 1;
 771                 else
 772                 {
 773                         cfi_command(bank, 0xf0, command);
 774                         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 775                         {
 776                                 return retval;
 777                         }
 778
 779                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 780                         return ERROR_FLASH_OPERATION_FAILED;
 781                 }
 782         }
 783
 784         cfi_command(bank, 0xf0, command);
 785         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 786 }
 787
 788 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
 789 {
 790         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 791
 792         if (bank->target->state != TARGET_HALTED)
 793         {
 794                 LOG_ERROR("Target not halted");
 795                 return ERROR_TARGET_NOT_HALTED;
 796         }
 797
 798         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 799         {
 800                 return ERROR_FLASH_SECTOR_INVALID;
 801         }
 802
 803         if (cfi_info->qry[0] != 'Q')
 804                 return ERROR_FLASH_BANK_NOT_PROBED;
 805
 806         switch(cfi_info->pri_id)
 807         {
 808                 case 1:
 809                 case 3:
 810                         return cfi_intel_erase(bank, first, last);
 811                         break;
 812                 case 2:
 813                         return cfi_spansion_erase(bank, first, last);
 814                         break;
 815                 default:
 816                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 817                         break;
 818         }
 819
 820         return ERROR_OK;
 821 }
 822
 823 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 824 {
 825         int retval;
 826         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 827         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 828         target_t *target = bank->target;
 829         u8 command[8];
 830         int retry = 0;
 831         int i;
 832
 833         /* if the device supports neither legacy lock/unlock (bit 3) nor
 834          * instant individual block locking (bit 5).
 835          */
 836         if (!(pri_ext->feature_support & 0x28))
 837                 return ERROR_FLASH_OPERATION_FAILED;
 838
 839         cfi_intel_clear_status_register(bank);
 840
 841         for (i = first; i <= last; i++)
 842         {
 843                 cfi_command(bank, 0x60, command);
 844                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 845                 if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 846                 {
 847                         return retval;
 848                 }
 849                 if (set)
 850                 {
 851                         cfi_command(bank, 0x01, command);
 852                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 853                         if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 854                         {
 855                                 return retval;
 856                         }
 857                         bank->sectors[i].is_protected = 1;
 858                 }
 859                 else
 860                 {
 861                         cfi_command(bank, 0xd0, command);
 862                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 863                         if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 864                         {
 865                                 return retval;
 866                         }
 867                         bank->sectors[i].is_protected = 0;
 868                 }
 869
 870                 /* instant individual block locking doesn't require reading of the status register */
 871                 if (!(pri_ext->feature_support & 0x20))
 872                 {
 873                         /* Clear lock bits operation may take up to 1.4s */
 874                         cfi_intel_wait_status_busy(bank, 1400);
 875                 }
 876                 else
 877                 {
 878                         u8 block_status;
 879                         /* read block lock bit, to verify status */
 880                         cfi_command(bank, 0x90, command);
 881                         if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 882                         {
 883                                 return retval;
 884                         }
 885                         block_status = cfi_get_u8(bank, i, 0x2);
 886
 887                         if ((block_status & 0x1) != set)
 888                         {
 889                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 890                                 cfi_command(bank, 0x70, command);
 891                                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 892                                 {
 893                                         return retval;
 894                                 }
 895                                 cfi_intel_wait_status_busy(bank, 10);
 896
 897                                 if (retry > 10)
 898                                         return ERROR_FLASH_OPERATION_FAILED;
 899                                 else
 900                                 {
 901                                         i--;
 902                                         retry++;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         /* if the device doesn't support individual block lock bits set/clear,
 909          * all blocks have been unlocked in parallel, so we set those that should be protected
 910          */
 911         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 912         {
 913                 for (i = 0; i < bank->num_sectors; i++)
 914                 {
 915                         if (bank->sectors[i].is_protected == 1)
 916                         {
 917                                 cfi_intel_clear_status_register(bank);
 918
 919                                 cfi_command(bank, 0x60, command);
 920                                 if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 921                                 {
 922                                         return retval;
 923                                 }
 924
 925                                 cfi_command(bank, 0x01, command);
 926                                 if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 927                                 {
 928                                         return retval;
 929                                 }
 930
 931                                 cfi_intel_wait_status_busy(bank, 100);
 932                         }
 933                 }
 934         }
 935
 936         cfi_command(bank, 0xff, command);
 937         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 938 }
 939
 940 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 941 {
 942         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 943
 944         if (bank->target->state != TARGET_HALTED)
 945         {
 946                 LOG_ERROR("Target not halted");
 947                 return ERROR_TARGET_NOT_HALTED;
 948         }
 949
 950         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 951         {
 952                 return ERROR_FLASH_SECTOR_INVALID;
 953         }
 954
 955         if (cfi_info->qry[0] != 'Q')
 956                 return ERROR_FLASH_BANK_NOT_PROBED;
 957
 958         switch(cfi_info->pri_id)
 959         {
 960                 case 1:
 961                 case 3:
 962                         cfi_intel_protect(bank, set, first, last);
 963                         break;
 964                 default:
 965                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 966                         break;
 967         }
 968
 969         return ERROR_OK;
 970 }
 971
 972 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 973 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 974 {
 975         /* target_t *target = bank->target; */
 976
 977         int i;
 978
 979         /* NOTE:
 980          * The data to flash must not be changed in endian! We write a bytestrem in
 981          * target byte order already. Only the control and status byte lane of the flash
 982          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 983          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 984          */
 985
 986 #if 0
 987         if (target->endianness == TARGET_LITTLE_ENDIAN)
 988         {
 989 #endif
 990                 /* shift bytes */
 991                 for (i = 0; i < bank->bus_width - 1; i++)
 992                         word[i] = word[i + 1];
 993                 word[bank->bus_width - 1] = byte;
 994 #if 0
 995         }
 996         else
 997         {
 998                 /* shift bytes */
 999                 for (i = bank->bus_width - 1; i > 0; i--)
1000                         word[i] = word[i - 1];
1001                 word[0] = byte;
1002         }
1003 #endif
1004 }
1005
1006 /* Convert code image to target endian */
1007 /* FIXME create general block conversion fcts in target.c?) */
1008 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
1009 {
1010         u32 i;
1011         for (i=0; i< count; i++)
1012         {
1013                 target_buffer_set_u32(target, dest, *src);
1014                 dest+=4;
1015                 src++;
1016         }
1017 }
1018
1019 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1020 {
1021         target_t *target = bank->target;
1022
1023         u8 buf[CFI_MAX_BUS_WIDTH];
1024         cfi_command(bank, cmd, buf);
1025         switch (bank->bus_width)
1026         {
1027         case 1 :
1028                 return buf[0];
1029                 break;
1030         case 2 :
1031                 return target_buffer_get_u16(target, buf);
1032                 break;
1033         case 4 :
1034                 return target_buffer_get_u32(target, buf);
1035                 break;
1036         default :
1037                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1038                 return 0;
1039         }
1040 }
1041
1042 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1043 {
1044         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1045         target_t *target = bank->target;
1046         reg_param_t reg_params[7];
1047         armv4_5_algorithm_t armv4_5_info;
1048         working_area_t *source;
1049         u32 buffer_size = 32768;
1050         u32 write_command_val, busy_pattern_val, error_pattern_val;
1051
1052         /* algorithm register usage:
1053          * r0: source address (in RAM)
1054          * r1: target address (in Flash)
1055          * r2: count
1056          * r3: flash write command
1057          * r4: status byte (returned to host)
1058          * r5: busy test pattern
1059          * r6: error test pattern
1060          */
1061
1062         static const u32 word_32_code[] = {
1063                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1064                 0xe5813000,   /*                str r3, [r1] */
1065                 0xe5814000,   /*                str r4, [r1] */
1066                 0xe5914000,   /* busy:  ldr r4, [r1] */
1067                 0xe0047005,   /*                and r7, r4, r5 */
1068                 0xe1570005,   /*                cmp r7, r5 */
1069                 0x1afffffb,   /*                bne busy */
1070                 0xe1140006,   /*                tst r4, r6 */
1071                 0x1a000003,   /*                bne done */
1072                 0xe2522001,   /*                subs r2, r2, #1 */
1073                 0x0a000001,   /*                beq done */
1074                 0xe2811004,   /*                add r1, r1 #4 */
1075                 0xeafffff2,   /*                b loop */
1076                 0xeafffffe    /* done:  b -2 */
1077         };
1078
1079         static const u32 word_16_code[] = {
1080                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1081                 0xe1c130b0,   /*                strh r3, [r1] */
1082                 0xe1c140b0,   /*                strh r4, [r1] */
1083                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1084                 0xe0047005,   /*                and r7, r4, r5 */
1085                 0xe1570005,   /*                cmp r7, r5 */
1086                 0x1afffffb,   /*                bne busy */
1087                 0xe1140006,   /*                tst r4, r6 */
1088                 0x1a000003,   /*                bne done */
1089                 0xe2522001,   /*                subs r2, r2, #1 */
1090                 0x0a000001,   /*                beq done */
1091                 0xe2811002,   /*                add r1, r1 #2 */
1092                 0xeafffff2,   /*                b loop */
1093                 0xeafffffe    /* done:  b -2 */
1094         };
1095
1096         static const u32 word_8_code[] = {
1097                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1098                 0xe5c13000,   /*                strb r3, [r1] */
1099                 0xe5c14000,   /*                strb r4, [r1] */
1100                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1101                 0xe0047005,   /*                and r7, r4, r5 */
1102                 0xe1570005,   /*                cmp r7, r5 */
1103                 0x1afffffb,   /*                bne busy */
1104                 0xe1140006,   /*                tst r4, r6 */
1105                 0x1a000003,   /*                bne done */
1106                 0xe2522001,   /*                subs r2, r2, #1 */
1107                 0x0a000001,   /*                beq done */
1108                 0xe2811001,   /*                add r1, r1 #1 */
1109                 0xeafffff2,   /*                b loop */
1110                 0xeafffffe    /* done:  b -2 */
1111         };
1112         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1113         const u32 *target_code_src;
1114         u32 target_code_size;
1115         int retval = ERROR_OK;
1116
1117
1118         cfi_intel_clear_status_register(bank);
1119
1120         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1121         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1122         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1123
1124         /* If we are setting up the write_algorith, we need target_code_src */
1125         /* if not we only need target_code_size.                                                                                                                */
1126         /*                                                                                                                                                                                                                                                                      */
1127         /* However, we don't want to create multiple code paths, so we                  */
1128         /* do the unecessary evaluation of target_code_src, which the                   */
1129         /* compiler will probably nicely optimize away if not needed                            */
1130
1131         /* prepare algorithm code for target endian */
1132         switch (bank->bus_width)
1133         {
1134         case 1 :
1135                 target_code_src = word_8_code;
1136                 target_code_size = sizeof(word_8_code);
1137                 break;
1138         case 2 :
1139                 target_code_src = word_16_code;
1140                 target_code_size = sizeof(word_16_code);
1141                 break;
1142         case 4 :
1143                 target_code_src = word_32_code;
1144                 target_code_size = sizeof(word_32_code);
1145                 break;
1146         default:
1147                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1148                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1149         }
1150
1151         /* flash write code */
1152         if (!cfi_info->write_algorithm)
1153         {
1154                 if ( target_code_size > sizeof(target_code) )
1155                 {
1156                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1157                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1158                 }
1159                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1160
1161                 /* Get memory for block write handler */
1162                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1163                 if (retval != ERROR_OK)
1164                 {
1165                         LOG_WARNING("No working area available, can't do block memory writes");
1166                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1167                 };
1168
1169                 /* write algorithm code to working area */
1170                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1171                 if (retval != ERROR_OK)
1172                 {
1173                         LOG_ERROR("Unable to write block write code to target");
1174                         goto cleanup;
1175                 }
1176         }
1177
1178         /* Get a workspace buffer for the data to flash starting with 32k size.
1179            Half size until buffer would be smaller 256 Bytem then fail back */
1180         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1181         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1182         {
1183                 buffer_size /= 2;
1184                 if (buffer_size <= 256)
1185                 {
1186                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1187                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1188                         goto cleanup;
1189                 }
1190         };
1191
1192         /* setup algo registers */
1193         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1194         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1195         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1196         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1197         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1198         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1199         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1200
1201         /* prepare command and status register patterns */
1202         write_command_val = cfi_command_val(bank, 0x40);
1203         busy_pattern_val  = cfi_command_val(bank, 0x80);
1204         error_pattern_val = cfi_command_val(bank, 0x7e);
1205
1206         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1207
1208         /* Programming main loop */
1209         while (count > 0)
1210         {
1211                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1212                 u32 wsm_error;
1213
1214                 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1215                 {
1216                         goto cleanup;
1217                 }
1218
1219                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1220                 buf_set_u32(reg_params[1].value, 0, 32, address);
1221                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1222
1223                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1224                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1225                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1226
1227                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1228
1229                 /* Execute algorithm, assume breakpoint for last instruction */
1230                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1231                         cfi_info->write_algorithm->address,
1232                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1233                         10000, /* 10s should be enough for max. 32k of data */
1234                         &armv4_5_info);
1235
1236                 /* On failure try a fall back to direct word writes */
1237                 if (retval != ERROR_OK)
1238                 {
1239                         cfi_intel_clear_status_register(bank);
1240                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1241                         retval = ERROR_FLASH_OPERATION_FAILED;
1242                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1243                         /* FIXME To allow fall back or recovery, we must save the actual status
1244                            somewhere, so that a higher level code can start recovery. */
1245                         goto cleanup;
1246                 }
1247
1248                 /* Check return value from algo code */
1249                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1250                 if (wsm_error)
1251                 {
1252                         /* read status register (outputs debug inforation) */
1253                         cfi_intel_wait_status_busy(bank, 100);
1254                         cfi_intel_clear_status_register(bank);
1255                         retval = ERROR_FLASH_OPERATION_FAILED;
1256                         goto cleanup;
1257                 }
1258
1259                 buffer += thisrun_count;
1260                 address += thisrun_count;
1261                 count -= thisrun_count;
1262         }
1263
1264         /* free up resources */
1265 cleanup:
1266         if (source)
1267                 target_free_working_area(target, source);
1268
1269         if (cfi_info->write_algorithm)
1270         {
1271                 target_free_working_area(target, cfi_info->write_algorithm);
1272                 cfi_info->write_algorithm = NULL;
1273         }
1274
1275         destroy_reg_param(&reg_params[0]);
1276         destroy_reg_param(&reg_params[1]);
1277         destroy_reg_param(&reg_params[2]);
1278         destroy_reg_param(&reg_params[3]);
1279         destroy_reg_param(&reg_params[4]);
1280         destroy_reg_param(&reg_params[5]);
1281         destroy_reg_param(&reg_params[6]);
1282
1283         return retval;
1284 }
1285
1286 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1287 {
1288         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1289         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1290         target_t *target = bank->target;
1291         reg_param_t reg_params[10];
1292         armv4_5_algorithm_t armv4_5_info;
1293         working_area_t *source;
1294         u32 buffer_size = 32768;
1295         u32 status;
1296         int retval, retvaltemp;
1297         int exit_code = ERROR_OK;
1298
1299         /* input parameters - */
1300         /*      R0 = source address */
1301         /*      R1 = destination address */
1302         /*      R2 = number of writes */
1303         /*      R3 = flash write command */
1304         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1305         /* output parameters - */
1306         /*      R5 = 0x80 ok 0x00 bad */
1307         /* temp registers - */
1308         /*      R6 = value read from flash to test status */
1309         /*      R7 = holding register */
1310         /* unlock registers - */
1311         /*  R8 = unlock1_addr */
1312         /*  R9 = unlock1_cmd */
1313         /*  R10 = unlock2_addr */
1314         /*  R11 = unlock2_cmd */
1315
1316         static const u32 word_32_code[] = {
1317                                                 /* 00008100 <sp_32_code>:               */
1318                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1319                 0xe5889000,     /* str  r9, [r8]                                */
1320                 0xe58ab000,     /* str  r11, [r10]                              */
1321                 0xe5883000,     /* str  r3, [r8]                                */
1322                 0xe5815000,     /* str  r5, [r1]                                */
1323                 0xe1a00000,     /* nop                                                  */
1324                                                 /*                                                              */
1325                                                 /* 00008110 <sp_32_busy>:               */
1326                 0xe5916000,     /* ldr  r6, [r1]                                */
1327                 0xe0257006,     /* eor  r7, r5, r6                              */
1328                 0xe0147007,     /* ands r7, r4, r7                              */
1329                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1330                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1331                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1332                 0xe5916000,     /* ldr  r6, [r1]                                */
1333                 0xe0257006,     /* eor  r7, r5, r6                              */
1334                 0xe0147007,     /* ands r7, r4, r7                              */
1335                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1336                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1337                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1338                                                 /*                                                              */
1339                                 /* 00008140 <sp_32_cont>:                               */
1340                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1341                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1342                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1343                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1344                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1345                                                 /*                                                              */
1346                                                 /* 00008154 <sp_32_done>:               */
1347                 0xeafffffe              /* b    8154 <sp_32_done>               */
1348                 };
1349
1350                 static const u32 word_16_code[] = {
1351                                 /* 00008158 <sp_16_code>:              */
1352                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1353                 0xe1c890b0,     /* strh r9, [r8]                                */
1354                 0xe1cab0b0,     /* strh r11, [r10]                              */
1355                 0xe1c830b0,     /* strh r3, [r8]                                */
1356                 0xe1c150b0,     /* strh r5, [r1]                       */
1357                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1358                                 /*                                     */
1359                                 /* 00008168 <sp_16_busy>:              */
1360                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1361                 0xe0257006,     /* eor  r7, r5, r6                     */
1362                 0xe0147007,     /* ands r7, r4, r7                     */
1363                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1364                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1365                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1366                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1367                 0xe0257006,     /* eor  r7, r5, r6                     */
1368                 0xe0147007,     /* ands r7, r4, r7                     */
1369                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1370                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1371                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1372                                 /*                                     */
1373                                 /* 00008198 <sp_16_cont>:              */
1374                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1375                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1376                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1377                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1378                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1379                                 /*                                     */
1380                                 /* 000081ac <sp_16_done>:              */
1381                 0xeafffffe      /* b    81ac <sp_16_done>              */
1382                 };
1383
1384                 static const u32 word_8_code[] = {
1385                                 /* 000081b0 <sp_16_code_end>:          */
1386                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1387                 0xe5c89000,     /* strb r9, [r8]                                */
1388                 0xe5cab000,     /* strb r11, [r10]                              */
1389                 0xe5c83000,     /* strb r3, [r8]                                */
1390                 0xe5c15000,     /* strb r5, [r1]                       */
1391                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1392                                 /*                                     */
1393                                 /* 000081c0 <sp_8_busy>:               */
1394                 0xe5d16000,     /* ldrb r6, [r1]                       */
1395                 0xe0257006,     /* eor  r7, r5, r6                     */
1396                 0xe0147007,     /* ands r7, r4, r7                     */
1397                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1398                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1399                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1400                 0xe5d16000,     /* ldrb r6, [r1]                       */
1401                 0xe0257006,     /* eor  r7, r5, r6                     */
1402                 0xe0147007,     /* ands r7, r4, r7                     */
1403                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1404                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1405                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1406                                 /*                                     */
1407                                 /* 000081f0 <sp_8_cont>:               */
1408                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1409                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1410                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1411                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1412                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1413                                 /*                                     */
1414                                 /* 00008204 <sp_8_done>:               */
1415                 0xeafffffe      /* b    8204 <sp_8_done>               */
1416         };
1417
1418         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1419         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1420         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1421
1422         /* flash write code */
1423         if (!cfi_info->write_algorithm)
1424         {
1425                 u8 *target_code;
1426                 int target_code_size;
1427                 const u32 *src;
1428
1429                 /* convert bus-width dependent algorithm code to correct endiannes */
1430                 switch (bank->bus_width)
1431                 {
1432                 case 1:
1433                         src = word_8_code;
1434                         target_code_size = sizeof(word_8_code);
1435                         break;
1436                 case 2:
1437                         src = word_16_code;
1438                         target_code_size = sizeof(word_16_code);
1439                         break;
1440                 case 4:
1441                         src = word_32_code;
1442                         target_code_size = sizeof(word_32_code);
1443                         break;
1444                 default:
1445                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1446                         return ERROR_FLASH_OPERATION_FAILED;
1447                 }
1448                 target_code = malloc(target_code_size);
1449                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1450
1451                 /* allocate working area */
1452                 retval=target_alloc_working_area(target, target_code_size,
1453                                 &cfi_info->write_algorithm);
1454                 if (retval != ERROR_OK)
1455                 {
1456                         free(target_code);
1457                         return retval;
1458                 }
1459
1460                 /* write algorithm code to working area */
1461                 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1462                                     target_code_size, target_code)) != ERROR_OK)
1463                 {
1464                         free(target_code);
1465                         return retval;
1466                 }
1467
1468                 free(target_code);
1469         }
1470         /* the following code still assumes target code is fixed 24*4 bytes */
1471
1472         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1473         {
1474                 buffer_size /= 2;
1475                 if (buffer_size <= 256)
1476                 {
1477                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1478                         if (cfi_info->write_algorithm)
1479                                 target_free_working_area(target, cfi_info->write_algorithm);
1480
1481                         LOG_WARNING("not enough working area available, can't do block memory writes");
1482                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1483                 }
1484         };
1485
1486         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1487         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1488         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1489         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1490         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1491         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1492         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1493         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1494         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1495         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1496
1497         while (count > 0)
1498         {
1499                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1500
1501                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1502
1503                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1504                 buf_set_u32(reg_params[1].value, 0, 32, address);
1505                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1506                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1507                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1508                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1509                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1510                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1511                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1512
1513                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1514                                                      cfi_info->write_algorithm->address,
1515                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1516                                                      10000, &armv4_5_info);
1517
1518                 status = buf_get_u32(reg_params[5].value, 0, 32);
1519
1520                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1521                 {
1522                         LOG_DEBUG("status: 0x%x", status);
1523                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1524                         break;
1525                 }
1526
1527                 buffer += thisrun_count;
1528                 address += thisrun_count;
1529                 count -= thisrun_count;
1530         }
1531
1532         target_free_working_area(target, source);
1533
1534         destroy_reg_param(&reg_params[0]);
1535         destroy_reg_param(&reg_params[1]);
1536         destroy_reg_param(&reg_params[2]);
1537         destroy_reg_param(&reg_params[3]);
1538         destroy_reg_param(&reg_params[4]);
1539         destroy_reg_param(&reg_params[5]);
1540         destroy_reg_param(&reg_params[6]);
1541         destroy_reg_param(&reg_params[7]);
1542         destroy_reg_param(&reg_params[8]);
1543         destroy_reg_param(&reg_params[9]);
1544
1545         return exit_code;
1546 }
1547
1548 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1549 {
1550         int retval;
1551         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1552         target_t *target = bank->target;
1553         u8 command[8];
1554
1555         cfi_intel_clear_status_register(bank);
1556         cfi_command(bank, 0x40, command);
1557         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1558         {
1559                 return retval;
1560         }
1561
1562         if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1563         {
1564                 return retval;
1565         }
1566
1567         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1568         {
1569                 cfi_command(bank, 0xff, command);
1570                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1571                 {
1572                         return retval;
1573                 }
1574
1575                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1576                 return ERROR_FLASH_OPERATION_FAILED;
1577         }
1578
1579         return ERROR_OK;
1580 }
1581
1582 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1583 {
1584         int retval;
1585         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1586         target_t *target = bank->target;
1587         u8 command[8];
1588
1589         /* Calculate buffer size and boundary mask */
1590         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1591         u32 buffermask = buffersize-1;
1592         u32 bufferwsize;
1593
1594         /* Check for valid range */
1595         if (address & buffermask)
1596         {
1597                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1598                 return ERROR_FLASH_OPERATION_FAILED;
1599         }
1600         switch(bank->chip_width)
1601         {
1602         case 4 : bufferwsize = buffersize / 4; break;
1603         case 2 : bufferwsize = buffersize / 2; break;
1604         case 1 : bufferwsize = buffersize; break;
1605         default:
1606                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1607                 return ERROR_FLASH_OPERATION_FAILED;
1608         }
1609
1610         bufferwsize/=(bank->bus_width / bank->chip_width);
1611
1612
1613         /* Check for valid size */
1614         if (wordcount > bufferwsize)
1615         {
1616                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1617                 return ERROR_FLASH_OPERATION_FAILED;
1618         }
1619
1620         /* Write to flash buffer */
1621         cfi_intel_clear_status_register(bank);
1622
1623         /* Initiate buffer operation _*/
1624         cfi_command(bank, 0xE8, command);
1625         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1626         {
1627                 return retval;
1628         }
1629         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1630         {
1631                 cfi_command(bank, 0xff, command);
1632                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1633                 {
1634                         return retval;
1635                 }
1636
1637                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1638                 return ERROR_FLASH_OPERATION_FAILED;
1639         }
1640
1641         /* Write buffer wordcount-1 and data words */
1642         cfi_command(bank, bufferwsize-1, command);
1643         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1644         {
1645                 return retval;
1646         }
1647
1648         if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1649         {
1650                 return retval;
1651         }
1652
1653         /* Commit write operation */
1654         cfi_command(bank, 0xd0, command);
1655         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1656         {
1657                 return retval;
1658         }
1659         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1660         {
1661                 cfi_command(bank, 0xff, command);
1662                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1663                 {
1664                         return retval;
1665                 }
1666
1667                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1668                 return ERROR_FLASH_OPERATION_FAILED;
1669         }
1670
1671         return ERROR_OK;
1672 }
1673
1674 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1675 {
1676         int retval;
1677         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1678         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1679         target_t *target = bank->target;
1680         u8 command[8];
1681
1682         cfi_command(bank, 0xaa, command);
1683         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1684         {
1685                 return retval;
1686         }
1687
1688         cfi_command(bank, 0x55, command);
1689         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1690         {
1691                 return retval;
1692         }
1693
1694         cfi_command(bank, 0xa0, command);
1695         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1696         {
1697                 return retval;
1698         }
1699
1700         if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1701         {
1702                 return retval;
1703         }
1704
1705         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1706         {
1707                 cfi_command(bank, 0xf0, command);
1708                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1709                 {
1710                         return retval;
1711                 }
1712
1713                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1714                 return ERROR_FLASH_OPERATION_FAILED;
1715         }
1716
1717         return ERROR_OK;
1718 }
1719
1720 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1721 {
1722         int retval;
1723         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1724         target_t *target = bank->target;
1725         u8 command[8];
1726         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1727
1728         /* Calculate buffer size and boundary mask */
1729         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1730         u32 buffermask = buffersize-1;
1731         u32 bufferwsize;
1732
1733         /* Check for valid range */
1734         if (address & buffermask)
1735         {
1736                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1737                 return ERROR_FLASH_OPERATION_FAILED;
1738         }
1739         switch(bank->chip_width)
1740         {
1741         case 4 : bufferwsize = buffersize / 4; break;
1742         case 2 : bufferwsize = buffersize / 2; break;
1743         case 1 : bufferwsize = buffersize; break;
1744         default:
1745                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1746                 return ERROR_FLASH_OPERATION_FAILED;
1747         }
1748
1749         bufferwsize/=(bank->bus_width / bank->chip_width);
1750
1751         /* Check for valid size */
1752         if (wordcount > bufferwsize)
1753         {
1754                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1755                 return ERROR_FLASH_OPERATION_FAILED;
1756         }
1757
1758         // Unlock
1759         cfi_command(bank, 0xaa, command);
1760         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1761         {
1762                 return retval;
1763         }
1764
1765         cfi_command(bank, 0x55, command);
1766         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1767         {
1768                 return retval;
1769         }
1770
1771         // Buffer load command
1772         cfi_command(bank, 0x25, command);
1773         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1774         {
1775                 return retval;
1776         }
1777
1778         /* Write buffer wordcount-1 and data words */
1779         cfi_command(bank, bufferwsize-1, command);
1780         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1781         {
1782                 return retval;
1783         }
1784
1785         if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1786         {
1787                 return retval;
1788         }
1789
1790         /* Commit write operation */
1791         cfi_command(bank, 0x29, command);
1792         if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1793         {
1794                 return retval;
1795         }
1796
1797         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1798         {
1799                 cfi_command(bank, 0xf0, command);
1800                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1801                 {
1802                         return retval;
1803                 }
1804
1805                 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1806                 return ERROR_FLASH_OPERATION_FAILED;
1807         }
1808
1809         return ERROR_OK;
1810 }
1811
1812 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1813 {
1814         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1815
1816         switch(cfi_info->pri_id)
1817         {
1818                 case 1:
1819                 case 3:
1820                         return cfi_intel_write_word(bank, word, address);
1821                         break;
1822                 case 2:
1823                         return cfi_spansion_write_word(bank, word, address);
1824                         break;
1825                 default:
1826                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1827                         break;
1828         }
1829
1830         return ERROR_FLASH_OPERATION_FAILED;
1831 }
1832
1833 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1834 {
1835         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1836
1837         switch(cfi_info->pri_id)
1838         {
1839                 case 1:
1840                 case 3:
1841                         return cfi_intel_write_words(bank, word, wordcount, address);
1842                         break;
1843                 case 2:
1844                         return cfi_spansion_write_words(bank, word, wordcount, address);
1845                         break;
1846                 default:
1847                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1848                         break;
1849         }
1850
1851         return ERROR_FLASH_OPERATION_FAILED;
1852 }
1853
1854 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1855 {
1856         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1857         target_t *target = bank->target;
1858         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1859         u32 write_p, copy_p;
1860         int align;      /* number of unaligned bytes */
1861         int blk_count; /* number of bus_width bytes for block copy */
1862         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1863         int i;
1864         int retval;
1865
1866         if (bank->target->state != TARGET_HALTED)
1867         {
1868                 LOG_ERROR("Target not halted");
1869                 return ERROR_TARGET_NOT_HALTED;
1870         }
1871
1872         if (offset + count > bank->size)
1873                 return ERROR_FLASH_DST_OUT_OF_BANK;
1874
1875         if (cfi_info->qry[0] != 'Q')
1876                 return ERROR_FLASH_BANK_NOT_PROBED;
1877
1878         /* start at the first byte of the first word (bus_width size) */
1879         write_p = address & ~(bank->bus_width - 1);
1880         if ((align = address - write_p) != 0)
1881         {
1882                 LOG_INFO("Fixup %d unaligned head bytes", align );
1883
1884                 for (i = 0; i < bank->bus_width; i++)
1885                         current_word[i] = 0;
1886                 copy_p = write_p;
1887
1888                 /* copy bytes before the first write address */
1889                 for (i = 0; i < align; ++i, ++copy_p)
1890                 {
1891                         u8 byte;
1892                         if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1893                         {
1894                                 return retval;
1895                         }
1896                         cfi_add_byte(bank, current_word, byte);
1897                 }
1898
1899                 /* add bytes from the buffer */
1900                 for (; (i < bank->bus_width) && (count > 0); i++)
1901                 {
1902                         cfi_add_byte(bank, current_word, *buffer++);
1903                         count--;
1904                         copy_p++;
1905                 }
1906
1907                 /* if the buffer is already finished, copy bytes after the last write address */
1908                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1909                 {
1910                         u8 byte;
1911                         if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1912                         {
1913                                 return retval;
1914                         }
1915                         cfi_add_byte(bank, current_word, byte);
1916                 }
1917
1918                 retval = cfi_write_word(bank, current_word, write_p);
1919                 if (retval != ERROR_OK)
1920                         return retval;
1921                 write_p = copy_p;
1922         }
1923
1924         /* handle blocks of bus_size aligned bytes */
1925         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1926         switch(cfi_info->pri_id)
1927         {
1928                 /* try block writes (fails without working area) */
1929                 case 1:
1930                 case 3:
1931                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1932                         break;
1933                 case 2:
1934                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1935                         break;
1936                 default:
1937                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1938                         retval = ERROR_FLASH_OPERATION_FAILED;
1939                         break;
1940         }
1941         if (retval == ERROR_OK)
1942         {
1943                 /* Increment pointers and decrease count on succesful block write */
1944                 buffer += blk_count;
1945                 write_p += blk_count;
1946                 count -= blk_count;
1947         }
1948         else
1949         {
1950                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1951                 {
1952                         //adjust buffersize for chip width
1953                         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1954                         u32 buffermask = buffersize-1;
1955                         u32 bufferwsize;
1956
1957                         switch(bank->chip_width)
1958                         {
1959                         case 4 : bufferwsize = buffersize / 4; break;
1960                         case 2 : bufferwsize = buffersize / 2; break;
1961                         case 1 : bufferwsize = buffersize; break;
1962                         default:
1963                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1964                                 return ERROR_FLASH_OPERATION_FAILED;
1965                         }
1966
1967                         bufferwsize/=(bank->bus_width / bank->chip_width);
1968
1969                         /* fall back to memory writes */
1970                         while (count >= (u32)bank->bus_width)
1971                         {
1972                                 int fallback;
1973                                 if ((write_p & 0xff) == 0)
1974                                 {
1975                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1976                                 }
1977                                 fallback = 1;
1978                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1979                                 {
1980                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1981                                         if (retval == ERROR_OK)
1982                                         {
1983                                                 buffer += buffersize;
1984                                                 write_p += buffersize;
1985                                                 count -= buffersize;
1986                                                 fallback=0;
1987                                         }
1988                                 }
1989                                 /* try the slow way? */
1990                                 if (fallback)
1991                                 {
1992                                         for (i = 0; i < bank->bus_width; i++)
1993                                                 current_word[i] = 0;
1994
1995                                         for (i = 0; i < bank->bus_width; i++)
1996                                         {
1997                                                 cfi_add_byte(bank, current_word, *buffer++);
1998                                         }
1999
2000                                         retval = cfi_write_word(bank, current_word, write_p);
2001                                         if (retval != ERROR_OK)
2002                                                 return retval;
2003
2004                                         write_p += bank->bus_width;
2005                                         count -= bank->bus_width;
2006                                 }
2007                         }
2008                 }
2009                 else
2010                         return retval;
2011         }
2012
2013         /* return to read array mode, so we can read from flash again for padding */
2014         cfi_command(bank, 0xf0, current_word);
2015         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2016         {
2017                 return retval;
2018         }
2019         cfi_command(bank, 0xff, current_word);
2020         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2021         {
2022                 return retval;
2023         }
2024
2025         /* handle unaligned tail bytes */
2026         if (count > 0)
2027         {
2028                 LOG_INFO("Fixup %d unaligned tail bytes", count );
2029
2030                 copy_p = write_p;
2031                 for (i = 0; i < bank->bus_width; i++)
2032                         current_word[i] = 0;
2033
2034                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2035                 {
2036                         cfi_add_byte(bank, current_word, *buffer++);
2037                         count--;
2038                 }
2039                 for (; i < bank->bus_width; ++i, ++copy_p)
2040                 {
2041                         u8 byte;
2042                         if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2043                         {
2044                                 return retval;
2045                         }
2046                         cfi_add_byte(bank, current_word, byte);
2047                 }
2048                 retval = cfi_write_word(bank, current_word, write_p);
2049                 if (retval != ERROR_OK)
2050                         return retval;
2051         }
2052
2053         /* return to read array mode */
2054         cfi_command(bank, 0xf0, current_word);
2055         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2056         {
2057                 return retval;
2058         }
2059         cfi_command(bank, 0xff, current_word);
2060         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2061 }
2062
2063 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2064 {
2065         (void) param;
2066         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2067         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2068
2069         pri_ext->_reversed_geometry = 1;
2070 }
2071
2072 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2073 {
2074         int i;
2075         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2076         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2077         (void) param;
2078
2079         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2080         {
2081                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2082
2083                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2084                 {
2085                         int j = (cfi_info->num_erase_regions - 1) - i;
2086                         u32 swap;
2087
2088                         swap = cfi_info->erase_region_info[i];
2089                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2090                         cfi_info->erase_region_info[j] = swap;
2091                 }
2092         }
2093 }
2094
2095 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2096 {
2097         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2098         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2099         cfi_unlock_addresses_t *unlock_addresses = param;
2100
2101         pri_ext->_unlock1 = unlock_addresses->unlock1;
2102         pri_ext->_unlock2 = unlock_addresses->unlock2;
2103 }
2104
2105 static int cfi_probe(struct flash_bank_s *bank)
2106 {
2107         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2108         target_t *target = bank->target;
2109         u8 command[8];
2110         int num_sectors = 0;
2111         int i;
2112         int sector = 0;
2113         u32 unlock1 = 0x555;
2114         u32 unlock2 = 0x2aa;
2115         int retval;
2116
2117         if (bank->target->state != TARGET_HALTED)
2118         {
2119                 LOG_ERROR("Target not halted");
2120                 return ERROR_TARGET_NOT_HALTED;
2121         }
2122
2123         cfi_info->probed = 0;
2124
2125         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2126          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2127          */
2128         if (cfi_info->jedec_probe)
2129         {
2130                 unlock1 = 0x5555;
2131                 unlock2 = 0x2aaa;
2132         }
2133
2134         /* switch to read identifier codes mode ("AUTOSELECT") */
2135         cfi_command(bank, 0xaa, command);
2136         if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2137         {
2138                 return retval;
2139         }
2140         cfi_command(bank, 0x55, command);
2141         if((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2142         {
2143                 return retval;
2144         }
2145         cfi_command(bank, 0x90, command);
2146         if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2147         {
2148                 return retval;
2149         }
2150
2151         if (bank->chip_width == 1)
2152         {
2153                 u8 manufacturer, device_id;
2154                 if((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2155                 {
2156                         return retval;
2157                 }
2158                 if((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2159                 {
2160                         return retval;
2161                 }
2162                 cfi_info->manufacturer = manufacturer;
2163                 cfi_info->device_id = device_id;
2164         }
2165         else if (bank->chip_width == 2)
2166         {
2167                 if((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2168                 {
2169                         return retval;
2170                 }
2171                 if((retval = target_read_u16(target, flash_address(bank, 0, 0x02), &cfi_info->device_id)) != ERROR_OK)
2172                 {
2173                         return retval;
2174                 }
2175         }
2176
2177         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2178         /* switch back to read array mode */
2179         cfi_command(bank, 0xf0, command);
2180         if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2181         {
2182                 return retval;
2183         }
2184         cfi_command(bank, 0xff, command);
2185         if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2186         {
2187                 return retval;
2188         }
2189
2190         /* check device/manufacturer ID for known non-CFI flashes. */
2191         cfi_fixup_non_cfi(bank);
2192
2193         /* query only if this is a CFI compatible flash,
2194          * otherwise the relevant info has already been filled in
2195          */
2196         if (cfi_info->not_cfi == 0)
2197         {
2198                 /* enter CFI query mode
2199                  * according to JEDEC Standard No. 68.01,
2200                  * a single bus sequence with address = 0x55, data = 0x98 should put
2201                  * the device into CFI query mode.
2202                  *
2203                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2204                  */
2205                 cfi_command(bank, 0x98, command);
2206                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2207                 {
2208                         return retval;
2209                 }
2210
2211                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2212                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2213                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2214
2215                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2216
2217                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2218                 {
2219                         cfi_command(bank, 0xf0, command);
2220                         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2221                         {
2222                                 return retval;
2223                         }
2224                         cfi_command(bank, 0xff, command);
2225                         if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2226                         {
2227                                 return retval;
2228                         }
2229                         LOG_ERROR("Could not probe bank: no QRY");
2230                         return ERROR_FLASH_BANK_INVALID;
2231                 }
2232
2233                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2234                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2235                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2236                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2237
2238                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2239
2240                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2241                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2242                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2243                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2244                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2245                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2246                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2247                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2248                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2249                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2250                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2251                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2252
2253                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2254                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2255                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2256                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2257                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2258                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2259                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2260                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2261                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2262                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2263                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2264
2265                 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2266                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2267                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2268                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2269
2270                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2271
2272                 if (cfi_info->num_erase_regions)
2273                 {
2274                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2275                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2276                         {
2277                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2278                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2279                         }
2280                 }
2281                 else
2282                 {
2283                         cfi_info->erase_region_info = NULL;
2284                 }
2285
2286                 /* We need to read the primary algorithm extended query table before calculating
2287                  * the sector layout to be able to apply fixups
2288                  */
2289                 switch(cfi_info->pri_id)
2290                 {
2291                         /* Intel command set (standard and extended) */
2292                         case 0x0001:
2293                         case 0x0003:
2294                                 cfi_read_intel_pri_ext(bank);
2295                                 break;
2296                         /* AMD/Spansion, Atmel, ... command set */
2297                         case 0x0002:
2298                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2299                                 cfi_read_0002_pri_ext(bank);
2300                                 break;
2301                         default:
2302                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2303                                 break;
2304                 }
2305
2306                 /* return to read array mode
2307                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2308                  */
2309                 cfi_command(bank, 0xf0, command);
2310                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2311                 {
2312                         return retval;
2313                 }
2314                 cfi_command(bank, 0xff, command);
2315                 if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2316                 {
2317                         return retval;
2318                 }
2319         } /* end CFI case */
2320
2321         /* apply fixups depending on the primary command set */
2322         switch(cfi_info->pri_id)
2323         {
2324                 /* Intel command set (standard and extended) */
2325                 case 0x0001:
2326                 case 0x0003:
2327                         cfi_fixup(bank, cfi_0001_fixups);
2328                         break;
2329                 /* AMD/Spansion, Atmel, ... command set */
2330                 case 0x0002:
2331                         cfi_fixup(bank, cfi_0002_fixups);
2332                         break;
2333                 default:
2334                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2335                         break;
2336         }
2337
2338         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2339         {
2340                 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2341         }
2342
2343         if (cfi_info->num_erase_regions == 0)
2344         {
2345                 /* a device might have only one erase block, spanning the whole device */
2346                 bank->num_sectors = 1;
2347                 bank->sectors = malloc(sizeof(flash_sector_t));
2348
2349                 bank->sectors[sector].offset = 0x0;
2350                 bank->sectors[sector].size = bank->size;
2351                 bank->sectors[sector].is_erased = -1;
2352                 bank->sectors[sector].is_protected = -1;
2353         }
2354         else
2355         {
2356                 u32 offset = 0;
2357
2358                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2359                 {
2360                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2361                 }
2362
2363                 bank->num_sectors = num_sectors;
2364                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2365
2366                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2367                 {
2368                         u32 j;
2369                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2370                         {
2371                                 bank->sectors[sector].offset = offset;
2372                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2373                                 offset += bank->sectors[sector].size;
2374                                 bank->sectors[sector].is_erased = -1;
2375                                 bank->sectors[sector].is_protected = -1;
2376                                 sector++;
2377                         }
2378                 }
2379                 if (offset != cfi_info->dev_size)
2380                 {
2381                         LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2382                 }
2383         }
2384
2385         cfi_info->probed = 1;
2386
2387         return ERROR_OK;
2388 }
2389
2390 static int cfi_auto_probe(struct flash_bank_s *bank)
2391 {
2392         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2393         if (cfi_info->probed)
2394                 return ERROR_OK;
2395         return cfi_probe(bank);
2396 }
2397
2398
2399 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2400 {
2401         int retval;
2402         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2403         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2404         target_t *target = bank->target;
2405         u8 command[CFI_MAX_BUS_WIDTH];
2406         int i;
2407
2408         /* check if block lock bits are supported on this device */
2409         if (!(pri_ext->blk_status_reg_mask & 0x1))
2410                 return ERROR_FLASH_OPERATION_FAILED;
2411
2412         cfi_command(bank, 0x90, command);
2413         if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2414         {
2415                 return retval;
2416         }
2417
2418         for (i = 0; i < bank->num_sectors; i++)
2419         {
2420                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2421
2422                 if (block_status & 1)
2423                         bank->sectors[i].is_protected = 1;
2424                 else
2425                         bank->sectors[i].is_protected = 0;
2426         }
2427
2428         cfi_command(bank, 0xff, command);
2429         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2430 }
2431
2432 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2433 {
2434         int retval;
2435         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2436         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2437         target_t *target = bank->target;
2438         u8 command[8];
2439         int i;
2440
2441         cfi_command(bank, 0xaa, command);
2442         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2443         {
2444                 return retval;
2445         }
2446
2447         cfi_command(bank, 0x55, command);
2448         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2449         {
2450                 return retval;
2451         }
2452
2453         cfi_command(bank, 0x90, command);
2454         if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2455         {
2456                 return retval;
2457         }
2458
2459         for (i = 0; i < bank->num_sectors; i++)
2460         {
2461                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2462
2463                 if (block_status & 1)
2464                         bank->sectors[i].is_protected = 1;
2465                 else
2466                         bank->sectors[i].is_protected = 0;
2467         }
2468
2469         cfi_command(bank, 0xf0, command);
2470         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2471 }
2472
2473 static int cfi_protect_check(struct flash_bank_s *bank)
2474 {
2475         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2476
2477         if (bank->target->state != TARGET_HALTED)
2478         {
2479                 LOG_ERROR("Target not halted");
2480                 return ERROR_TARGET_NOT_HALTED;
2481         }
2482
2483         if (cfi_info->qry[0] != 'Q')
2484                 return ERROR_FLASH_BANK_NOT_PROBED;
2485
2486         switch(cfi_info->pri_id)
2487         {
2488                 case 1:
2489                 case 3:
2490                         return cfi_intel_protect_check(bank);
2491                         break;
2492                 case 2:
2493                         return cfi_spansion_protect_check(bank);
2494                         break;
2495                 default:
2496                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2497                         break;
2498         }
2499
2500         return ERROR_OK;
2501 }
2502
2503 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2504 {
2505         int printed;
2506         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2507
2508         if (cfi_info->qry[0] == (char)-1)
2509         {
2510                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2511                 return ERROR_OK;
2512         }
2513
2514         if (cfi_info->not_cfi == 0)
2515                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2516         else
2517                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2518         buf += printed;
2519         buf_size -= printed;
2520
2521         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2522                 cfi_info->manufacturer, cfi_info->device_id);
2523         buf += printed;
2524         buf_size -= printed;
2525
2526         if (cfi_info->not_cfi == 0)
2527         {
2528         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2529         buf += printed;
2530         buf_size -= printed;
2531
2532                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2533                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2534         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2535         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2536         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2537         buf += printed;
2538         buf_size -= printed;
2539
2540                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2541                                    1 << cfi_info->word_write_timeout_typ,
2542                                    1 << cfi_info->buf_write_timeout_typ,
2543                                    1 << cfi_info->block_erase_timeout_typ,
2544                                    1 << cfi_info->chip_erase_timeout_typ);
2545         buf += printed;
2546         buf_size -= printed;
2547
2548                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2549                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2550                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2551                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2552                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2553         buf += printed;
2554         buf_size -= printed;
2555
2556                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2557                                    cfi_info->dev_size,
2558                                    cfi_info->interface_desc,
2559                                    1 << cfi_info->max_buf_write_size);
2560         buf += printed;
2561         buf_size -= printed;
2562
2563         switch(cfi_info->pri_id)
2564         {
2565                 case 1:
2566                 case 3:
2567                         cfi_intel_info(bank, buf, buf_size);
2568                         break;
2569                 case 2:
2570                         cfi_spansion_info(bank, buf, buf_size);
2571                         break;
2572                 default:
2573                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2574                         break;
2575         }
2576         }
2577
2578         return ERROR_OK;
2579 }