1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
29 #include "binarybuffer.h"
32 static int cfi_register_commands(struct command_context_s *cmd_ctx);
33 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
34 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
35 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
36 static int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
37 static int cfi_probe(struct flash_bank_s *bank);
38 static int cfi_auto_probe(struct flash_bank_s *bank);
39 static int cfi_protect_check(struct flash_bank_s *bank);
40 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
42 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 #define CFI_MAX_BUS_WIDTH 4
45 #define CFI_MAX_CHIP_WIDTH 4
47 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
48 #define CFI_MAX_INTEL_CODESIZE 256
50 flash_driver_t cfi_flash =
53 .register_commands = cfi_register_commands,
54 .flash_bank_command = cfi_flash_bank_command,
56 .protect = cfi_protect,
59 .auto_probe = cfi_auto_probe,
60 .erase_check = default_flash_blank_check,
61 .protect_check = cfi_protect_check,
65 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
67 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
68 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
71 /* CFI fixups foward declarations */
72 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
73 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
74 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
76 /* fixup after reading cmdset 0002 primary query table */
77 static const cfi_fixup_t cfi_0002_fixups[] = {
78 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
79 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
80 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
81 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
82 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
83 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
84 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
85 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
86 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
87 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
88 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
92 /* fixup after reading cmdset 0001 primary query table */
93 static const cfi_fixup_t cfi_0001_fixups[] = {
97 static void cfi_fixup(flash_bank_t *bank, const cfi_fixup_t *fixups)
99 cfi_flash_bank_t *cfi_info = bank->driver_priv;
100 const cfi_fixup_t *f;
102 for (f = fixups; f->fixup; f++)
104 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
105 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
107 f->fixup(bank, f->param);
112 /* inline uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset) */
113 static __inline__ uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset)
115 cfi_flash_bank_t *cfi_info = bank->driver_priv;
117 if (cfi_info->x16_as_x8) offset *= 2;
119 /* while the sector list isn't built, only accesses to sector 0 work */
121 return bank->base + offset * bank->bus_width;
126 LOG_ERROR("BUG: sector list not yet built");
129 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
134 static void cfi_command(flash_bank_t *bank, uint8_t cmd, uint8_t *cmd_buf)
138 /* clear whole buffer, to ensure bits that exceed the bus_width
141 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
144 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
146 for (i = bank->bus_width; i > 0; i--)
148 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
153 for (i = 1; i <= bank->bus_width; i++)
155 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
160 /* read unsigned 8-bit value from the bank
161 * flash banks are expected to be made of similar chips
162 * the query result should be the same for all
164 static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, uint32_t offset)
166 target_t *target = bank->target;
167 uint8_t data[CFI_MAX_BUS_WIDTH];
169 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
171 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
174 return data[bank->bus_width - 1];
177 /* read unsigned 8-bit value from the bank
178 * in case of a bank made of multiple chips,
179 * the individual values are ORed
181 static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, uint32_t offset)
183 target_t *target = bank->target;
184 uint8_t data[CFI_MAX_BUS_WIDTH];
187 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
189 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
191 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
199 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
200 value |= data[bank->bus_width - 1 - i];
206 static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, uint32_t offset)
208 target_t *target = bank->target;
209 cfi_flash_bank_t *cfi_info = bank->driver_priv;
210 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
212 if (cfi_info->x16_as_x8)
215 for (i = 0;i < 2;i++)
216 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
217 &data[i*bank->bus_width]);
220 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
222 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
223 return data[0] | data[bank->bus_width] << 8;
225 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
228 static uint32_t cfi_query_u32(flash_bank_t *bank, int sector, uint32_t offset)
230 target_t *target = bank->target;
231 cfi_flash_bank_t *cfi_info = bank->driver_priv;
232 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
234 if (cfi_info->x16_as_x8)
237 for (i = 0;i < 4;i++)
238 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
239 &data[i*bank->bus_width]);
242 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
244 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
245 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
247 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
248 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
251 static void cfi_intel_clear_status_register(flash_bank_t *bank)
253 target_t *target = bank->target;
256 if (target->state != TARGET_HALTED)
258 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
262 cfi_command(bank, 0x50, command);
263 target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
266 uint8_t cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
270 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
272 LOG_DEBUG("status: 0x%x", status);
276 /* mask out bit 0 (reserved) */
277 status = status & 0xfe;
279 LOG_DEBUG("status: 0x%x", status);
281 if ((status & 0x80) != 0x80)
283 LOG_ERROR("timeout while waiting for WSM to become ready");
285 else if (status != 0x80)
287 LOG_ERROR("status register: 0x%x", status);
289 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
291 LOG_ERROR("Program suspended");
293 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
295 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
297 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
299 LOG_ERROR("Block Erase Suspended");
301 cfi_intel_clear_status_register(bank);
307 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
309 uint8_t status, oldstatus;
310 cfi_flash_bank_t *cfi_info = bank->driver_priv;
312 oldstatus = cfi_get_u8(bank, 0, 0x0);
315 status = cfi_get_u8(bank, 0, 0x0);
316 if ((status ^ oldstatus) & 0x40) {
317 if (status & cfi_info->status_poll_mask & 0x20) {
318 oldstatus = cfi_get_u8(bank, 0, 0x0);
319 status = cfi_get_u8(bank, 0, 0x0);
320 if ((status ^ oldstatus) & 0x40) {
321 LOG_ERROR("dq5 timeout, status: 0x%x", status);
322 return(ERROR_FLASH_OPERATION_FAILED);
324 LOG_DEBUG("status: 0x%x", status);
328 } else { /* no toggle: finished, OK */
329 LOG_DEBUG("status: 0x%x", status);
335 } while (timeout-- > 0);
337 LOG_ERROR("timeout, status: 0x%x", status);
339 return(ERROR_FLASH_BUSY);
342 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
345 cfi_flash_bank_t *cfi_info = bank->driver_priv;
346 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
347 target_t *target = bank->target;
350 cfi_info->pri_ext = pri_ext;
352 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
353 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
354 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
356 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
358 cfi_command(bank, 0xf0, command);
359 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
363 cfi_command(bank, 0xff, command);
364 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
368 LOG_ERROR("Could not read bank flash bank information");
369 return ERROR_FLASH_BANK_INVALID;
372 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
373 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
375 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
377 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
378 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
379 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
381 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
382 pri_ext->feature_support,
383 pri_ext->suspend_cmd_support,
384 pri_ext->blk_status_reg_mask);
386 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
387 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
389 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
390 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
391 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
393 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
394 if (pri_ext->num_protection_fields != 1)
396 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
399 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
400 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
401 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
403 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
408 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
411 cfi_flash_bank_t *cfi_info = bank->driver_priv;
412 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
413 target_t *target = bank->target;
416 cfi_info->pri_ext = pri_ext;
418 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
419 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
420 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
422 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
424 cfi_command(bank, 0xf0, command);
425 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
429 LOG_ERROR("Could not read spansion bank information");
430 return ERROR_FLASH_BANK_INVALID;
433 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
434 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
436 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
438 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
439 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
440 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
441 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
442 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
443 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
444 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
445 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
446 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
447 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
448 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
450 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
451 pri_ext->EraseSuspend, pri_ext->BlkProt);
453 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
454 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
456 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
459 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
460 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
461 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
463 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
465 /* default values for implementation specific workarounds */
466 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
467 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
468 pri_ext->_reversed_geometry = 0;
473 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
476 cfi_atmel_pri_ext_t atmel_pri_ext;
477 cfi_flash_bank_t *cfi_info = bank->driver_priv;
478 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
479 target_t *target = bank->target;
482 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
483 * but a different primary extended query table.
484 * We read the atmel table, and prepare a valid AMD/Spansion query table.
487 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
489 cfi_info->pri_ext = pri_ext;
491 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
492 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
493 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
495 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
497 cfi_command(bank, 0xf0, command);
498 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
502 LOG_ERROR("Could not read atmel bank information");
503 return ERROR_FLASH_BANK_INVALID;
506 pri_ext->pri[0] = atmel_pri_ext.pri[0];
507 pri_ext->pri[1] = atmel_pri_ext.pri[1];
508 pri_ext->pri[2] = atmel_pri_ext.pri[2];
510 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
511 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
513 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
515 pri_ext->major_version = atmel_pri_ext.major_version;
516 pri_ext->minor_version = atmel_pri_ext.minor_version;
518 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
519 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
520 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
521 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
523 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
524 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
526 if (atmel_pri_ext.features & 0x02)
527 pri_ext->EraseSuspend = 2;
529 if (atmel_pri_ext.bottom_boot)
530 pri_ext->TopBottom = 2;
532 pri_ext->TopBottom = 3;
534 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
535 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
540 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
542 cfi_flash_bank_t *cfi_info = bank->driver_priv;
544 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
546 return cfi_read_atmel_pri_ext(bank);
550 return cfi_read_spansion_pri_ext(bank);
554 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
557 cfi_flash_bank_t *cfi_info = bank->driver_priv;
558 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
560 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
564 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
565 pri_ext->pri[1], pri_ext->pri[2],
566 pri_ext->major_version, pri_ext->minor_version);
570 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
571 (pri_ext->SiliconRevision) >> 2,
572 (pri_ext->SiliconRevision) & 0x03);
576 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
577 pri_ext->EraseSuspend,
582 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
583 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
584 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
589 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
592 cfi_flash_bank_t *cfi_info = bank->driver_priv;
593 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
595 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
599 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
603 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
607 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
608 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
609 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
613 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
618 static int cfi_register_commands(struct command_context_s *cmd_ctx)
620 /*command_t *cfi_cmd = */
621 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
623 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
624 "print part id of cfi flash bank <num>");
629 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
631 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
633 cfi_flash_bank_t *cfi_info;
640 LOG_WARNING("incomplete flash_bank cfi configuration");
641 return ERROR_FLASH_BANK_INVALID;
644 uint16_t chip_width, bus_width;
645 COMMAND_PARSE_NUMBER(u16, args[3], bus_width);
646 COMMAND_PARSE_NUMBER(u16, args[4], chip_width);
648 if ((chip_width > CFI_MAX_CHIP_WIDTH)
649 || (bus_width > CFI_MAX_BUS_WIDTH))
651 LOG_ERROR("chip and bus width have to specified in bytes");
652 return ERROR_FLASH_BANK_INVALID;
655 cfi_info = malloc(sizeof(cfi_flash_bank_t));
656 cfi_info->probed = 0;
657 bank->driver_priv = cfi_info;
659 cfi_info->write_algorithm = NULL;
661 cfi_info->x16_as_x8 = 0;
662 cfi_info->jedec_probe = 0;
663 cfi_info->not_cfi = 0;
665 for (i = 6; i < argc; i++)
667 if (strcmp(args[i], "x16_as_x8") == 0)
669 cfi_info->x16_as_x8 = 1;
671 else if (strcmp(args[i], "jedec_probe") == 0)
673 cfi_info->jedec_probe = 1;
677 cfi_info->write_algorithm = NULL;
679 /* bank wasn't probed yet */
680 cfi_info->qry[0] = -1;
685 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
688 cfi_flash_bank_t *cfi_info = bank->driver_priv;
689 target_t *target = bank->target;
693 cfi_intel_clear_status_register(bank);
695 for (i = first; i <= last; i++)
697 cfi_command(bank, 0x20, command);
698 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
703 cfi_command(bank, 0xd0, command);
704 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
709 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
710 bank->sectors[i].is_erased = 1;
713 cfi_command(bank, 0xff, command);
714 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
719 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
720 return ERROR_FLASH_OPERATION_FAILED;
724 cfi_command(bank, 0xff, command);
725 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
729 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
732 cfi_flash_bank_t *cfi_info = bank->driver_priv;
733 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
734 target_t *target = bank->target;
738 for (i = first; i <= last; i++)
740 cfi_command(bank, 0xaa, command);
741 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
746 cfi_command(bank, 0x55, command);
747 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
752 cfi_command(bank, 0x80, command);
753 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
758 cfi_command(bank, 0xaa, command);
759 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
764 cfi_command(bank, 0x55, command);
765 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
770 cfi_command(bank, 0x30, command);
771 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
776 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
777 bank->sectors[i].is_erased = 1;
780 cfi_command(bank, 0xf0, command);
781 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
786 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
787 return ERROR_FLASH_OPERATION_FAILED;
791 cfi_command(bank, 0xf0, command);
792 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
795 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
797 cfi_flash_bank_t *cfi_info = bank->driver_priv;
799 if (bank->target->state != TARGET_HALTED)
801 LOG_ERROR("Target not halted");
802 return ERROR_TARGET_NOT_HALTED;
805 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
807 return ERROR_FLASH_SECTOR_INVALID;
810 if (cfi_info->qry[0] != 'Q')
811 return ERROR_FLASH_BANK_NOT_PROBED;
813 switch (cfi_info->pri_id)
817 return cfi_intel_erase(bank, first, last);
820 return cfi_spansion_erase(bank, first, last);
823 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
830 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
833 cfi_flash_bank_t *cfi_info = bank->driver_priv;
834 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
835 target_t *target = bank->target;
840 /* if the device supports neither legacy lock/unlock (bit 3) nor
841 * instant individual block locking (bit 5).
843 if (!(pri_ext->feature_support & 0x28))
844 return ERROR_FLASH_OPERATION_FAILED;
846 cfi_intel_clear_status_register(bank);
848 for (i = first; i <= last; i++)
850 cfi_command(bank, 0x60, command);
851 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
852 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
858 cfi_command(bank, 0x01, command);
859 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
860 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
864 bank->sectors[i].is_protected = 1;
868 cfi_command(bank, 0xd0, command);
869 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
870 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
874 bank->sectors[i].is_protected = 0;
877 /* instant individual block locking doesn't require reading of the status register */
878 if (!(pri_ext->feature_support & 0x20))
880 /* Clear lock bits operation may take up to 1.4s */
881 cfi_intel_wait_status_busy(bank, 1400);
885 uint8_t block_status;
886 /* read block lock bit, to verify status */
887 cfi_command(bank, 0x90, command);
888 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
892 block_status = cfi_get_u8(bank, i, 0x2);
894 if ((block_status & 0x1) != set)
896 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
897 cfi_command(bank, 0x70, command);
898 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
902 cfi_intel_wait_status_busy(bank, 10);
905 return ERROR_FLASH_OPERATION_FAILED;
915 /* if the device doesn't support individual block lock bits set/clear,
916 * all blocks have been unlocked in parallel, so we set those that should be protected
918 if ((!set) && (!(pri_ext->feature_support & 0x20)))
920 for (i = 0; i < bank->num_sectors; i++)
922 if (bank->sectors[i].is_protected == 1)
924 cfi_intel_clear_status_register(bank);
926 cfi_command(bank, 0x60, command);
927 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
932 cfi_command(bank, 0x01, command);
933 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
938 cfi_intel_wait_status_busy(bank, 100);
943 cfi_command(bank, 0xff, command);
944 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
947 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
949 cfi_flash_bank_t *cfi_info = bank->driver_priv;
951 if (bank->target->state != TARGET_HALTED)
953 LOG_ERROR("Target not halted");
954 return ERROR_TARGET_NOT_HALTED;
957 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
959 return ERROR_FLASH_SECTOR_INVALID;
962 if (cfi_info->qry[0] != 'Q')
963 return ERROR_FLASH_BANK_NOT_PROBED;
965 switch (cfi_info->pri_id)
969 cfi_intel_protect(bank, set, first, last);
972 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
979 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
980 static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
982 /* target_t *target = bank->target; */
987 * The data to flash must not be changed in endian! We write a bytestrem in
988 * target byte order already. Only the control and status byte lane of the flash
989 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
990 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
994 if (target->endianness == TARGET_LITTLE_ENDIAN)
998 for (i = 0; i < bank->bus_width - 1; i++)
999 word[i] = word[i + 1];
1000 word[bank->bus_width - 1] = byte;
1006 for (i = bank->bus_width - 1; i > 0; i--)
1007 word[i] = word[i - 1];
1013 /* Convert code image to target endian */
1014 /* FIXME create general block conversion fcts in target.c?) */
1015 static void cfi_fix_code_endian(target_t *target, uint8_t *dest, const uint32_t *src, uint32_t count)
1018 for (i = 0; i< count; i++)
1020 target_buffer_set_u32(target, dest, *src);
1026 static uint32_t cfi_command_val(flash_bank_t *bank, uint8_t cmd)
1028 target_t *target = bank->target;
1030 uint8_t buf[CFI_MAX_BUS_WIDTH];
1031 cfi_command(bank, cmd, buf);
1032 switch (bank->bus_width)
1038 return target_buffer_get_u16(target, buf);
1041 return target_buffer_get_u32(target, buf);
1044 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1049 static int cfi_intel_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1051 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1052 target_t *target = bank->target;
1053 reg_param_t reg_params[7];
1054 armv4_5_algorithm_t armv4_5_info;
1055 working_area_t *source;
1056 uint32_t buffer_size = 32768;
1057 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1059 /* algorithm register usage:
1060 * r0: source address (in RAM)
1061 * r1: target address (in Flash)
1063 * r3: flash write command
1064 * r4: status byte (returned to host)
1065 * r5: busy test pattern
1066 * r6: error test pattern
1069 static const uint32_t word_32_code[] = {
1070 0xe4904004, /* loop: ldr r4, [r0], #4 */
1071 0xe5813000, /* str r3, [r1] */
1072 0xe5814000, /* str r4, [r1] */
1073 0xe5914000, /* busy: ldr r4, [r1] */
1074 0xe0047005, /* and r7, r4, r5 */
1075 0xe1570005, /* cmp r7, r5 */
1076 0x1afffffb, /* bne busy */
1077 0xe1140006, /* tst r4, r6 */
1078 0x1a000003, /* bne done */
1079 0xe2522001, /* subs r2, r2, #1 */
1080 0x0a000001, /* beq done */
1081 0xe2811004, /* add r1, r1 #4 */
1082 0xeafffff2, /* b loop */
1083 0xeafffffe /* done: b -2 */
1086 static const uint32_t word_16_code[] = {
1087 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1088 0xe1c130b0, /* strh r3, [r1] */
1089 0xe1c140b0, /* strh r4, [r1] */
1090 0xe1d140b0, /* busy ldrh r4, [r1] */
1091 0xe0047005, /* and r7, r4, r5 */
1092 0xe1570005, /* cmp r7, r5 */
1093 0x1afffffb, /* bne busy */
1094 0xe1140006, /* tst r4, r6 */
1095 0x1a000003, /* bne done */
1096 0xe2522001, /* subs r2, r2, #1 */
1097 0x0a000001, /* beq done */
1098 0xe2811002, /* add r1, r1 #2 */
1099 0xeafffff2, /* b loop */
1100 0xeafffffe /* done: b -2 */
1103 static const uint32_t word_8_code[] = {
1104 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1105 0xe5c13000, /* strb r3, [r1] */
1106 0xe5c14000, /* strb r4, [r1] */
1107 0xe5d14000, /* busy ldrb r4, [r1] */
1108 0xe0047005, /* and r7, r4, r5 */
1109 0xe1570005, /* cmp r7, r5 */
1110 0x1afffffb, /* bne busy */
1111 0xe1140006, /* tst r4, r6 */
1112 0x1a000003, /* bne done */
1113 0xe2522001, /* subs r2, r2, #1 */
1114 0x0a000001, /* beq done */
1115 0xe2811001, /* add r1, r1 #1 */
1116 0xeafffff2, /* b loop */
1117 0xeafffffe /* done: b -2 */
1119 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1120 const uint32_t *target_code_src;
1121 uint32_t target_code_size;
1122 int retval = ERROR_OK;
1125 cfi_intel_clear_status_register(bank);
1127 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1128 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1129 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1131 /* If we are setting up the write_algorith, we need target_code_src */
1132 /* if not we only need target_code_size. */
1134 /* However, we don't want to create multiple code paths, so we */
1135 /* do the unecessary evaluation of target_code_src, which the */
1136 /* compiler will probably nicely optimize away if not needed */
1138 /* prepare algorithm code for target endian */
1139 switch (bank->bus_width)
1142 target_code_src = word_8_code;
1143 target_code_size = sizeof(word_8_code);
1146 target_code_src = word_16_code;
1147 target_code_size = sizeof(word_16_code);
1150 target_code_src = word_32_code;
1151 target_code_size = sizeof(word_32_code);
1154 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1155 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1158 /* flash write code */
1159 if (!cfi_info->write_algorithm)
1161 if (target_code_size > sizeof(target_code))
1163 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1164 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1166 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1168 /* Get memory for block write handler */
1169 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1170 if (retval != ERROR_OK)
1172 LOG_WARNING("No working area available, can't do block memory writes");
1173 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1176 /* write algorithm code to working area */
1177 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1178 if (retval != ERROR_OK)
1180 LOG_ERROR("Unable to write block write code to target");
1185 /* Get a workspace buffer for the data to flash starting with 32k size.
1186 Half size until buffer would be smaller 256 Bytem then fail back */
1187 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1188 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1191 if (buffer_size <= 256)
1193 LOG_WARNING("no large enough working area available, can't do block memory writes");
1194 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1199 /* setup algo registers */
1200 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1201 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1202 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1203 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1204 init_reg_param(®_params[4], "r4", 32, PARAM_IN);
1205 init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
1206 init_reg_param(®_params[6], "r6", 32, PARAM_OUT);
1208 /* prepare command and status register patterns */
1209 write_command_val = cfi_command_val(bank, 0x40);
1210 busy_pattern_val = cfi_command_val(bank, 0x80);
1211 error_pattern_val = cfi_command_val(bank, 0x7e);
1213 LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1215 /* Programming main loop */
1218 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1221 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1226 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1227 buf_set_u32(reg_params[1].value, 0, 32, address);
1228 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1230 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1231 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1232 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1234 LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1236 /* Execute algorithm, assume breakpoint for last instruction */
1237 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1238 cfi_info->write_algorithm->address,
1239 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1240 10000, /* 10s should be enough for max. 32k of data */
1243 /* On failure try a fall back to direct word writes */
1244 if (retval != ERROR_OK)
1246 cfi_intel_clear_status_register(bank);
1247 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1248 retval = ERROR_FLASH_OPERATION_FAILED;
1249 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1250 /* FIXME To allow fall back or recovery, we must save the actual status
1251 somewhere, so that a higher level code can start recovery. */
1255 /* Check return value from algo code */
1256 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1259 /* read status register (outputs debug inforation) */
1260 cfi_intel_wait_status_busy(bank, 100);
1261 cfi_intel_clear_status_register(bank);
1262 retval = ERROR_FLASH_OPERATION_FAILED;
1266 buffer += thisrun_count;
1267 address += thisrun_count;
1268 count -= thisrun_count;
1271 /* free up resources */
1274 target_free_working_area(target, source);
1276 if (cfi_info->write_algorithm)
1278 target_free_working_area(target, cfi_info->write_algorithm);
1279 cfi_info->write_algorithm = NULL;
1282 destroy_reg_param(®_params[0]);
1283 destroy_reg_param(®_params[1]);
1284 destroy_reg_param(®_params[2]);
1285 destroy_reg_param(®_params[3]);
1286 destroy_reg_param(®_params[4]);
1287 destroy_reg_param(®_params[5]);
1288 destroy_reg_param(®_params[6]);
1293 static int cfi_spansion_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1295 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1296 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1297 target_t *target = bank->target;
1298 reg_param_t reg_params[10];
1299 armv4_5_algorithm_t armv4_5_info;
1300 working_area_t *source;
1301 uint32_t buffer_size = 32768;
1303 int retval, retvaltemp;
1304 int exit_code = ERROR_OK;
1306 /* input parameters - */
1307 /* R0 = source address */
1308 /* R1 = destination address */
1309 /* R2 = number of writes */
1310 /* R3 = flash write command */
1311 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1312 /* output parameters - */
1313 /* R5 = 0x80 ok 0x00 bad */
1314 /* temp registers - */
1315 /* R6 = value read from flash to test status */
1316 /* R7 = holding register */
1317 /* unlock registers - */
1318 /* R8 = unlock1_addr */
1319 /* R9 = unlock1_cmd */
1320 /* R10 = unlock2_addr */
1321 /* R11 = unlock2_cmd */
1323 static const uint32_t word_32_code[] = {
1324 /* 00008100 <sp_32_code>: */
1325 0xe4905004, /* ldr r5, [r0], #4 */
1326 0xe5889000, /* str r9, [r8] */
1327 0xe58ab000, /* str r11, [r10] */
1328 0xe5883000, /* str r3, [r8] */
1329 0xe5815000, /* str r5, [r1] */
1330 0xe1a00000, /* nop */
1332 /* 00008110 <sp_32_busy>: */
1333 0xe5916000, /* ldr r6, [r1] */
1334 0xe0257006, /* eor r7, r5, r6 */
1335 0xe0147007, /* ands r7, r4, r7 */
1336 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1337 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1338 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1339 0xe5916000, /* ldr r6, [r1] */
1340 0xe0257006, /* eor r7, r5, r6 */
1341 0xe0147007, /* ands r7, r4, r7 */
1342 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1343 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1344 0x1a000004, /* bne 8154 <sp_32_done> */
1346 /* 00008140 <sp_32_cont>: */
1347 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1348 0x03a05080, /* moveq r5, #128 ; 0x80 */
1349 0x0a000001, /* beq 8154 <sp_32_done> */
1350 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1351 0xeaffffe8, /* b 8100 <sp_32_code> */
1353 /* 00008154 <sp_32_done>: */
1354 0xeafffffe /* b 8154 <sp_32_done> */
1357 static const uint32_t word_16_code[] = {
1358 /* 00008158 <sp_16_code>: */
1359 0xe0d050b2, /* ldrh r5, [r0], #2 */
1360 0xe1c890b0, /* strh r9, [r8] */
1361 0xe1cab0b0, /* strh r11, [r10] */
1362 0xe1c830b0, /* strh r3, [r8] */
1363 0xe1c150b0, /* strh r5, [r1] */
1364 0xe1a00000, /* nop (mov r0,r0) */
1366 /* 00008168 <sp_16_busy>: */
1367 0xe1d160b0, /* ldrh r6, [r1] */
1368 0xe0257006, /* eor r7, r5, r6 */
1369 0xe0147007, /* ands r7, r4, r7 */
1370 0x0a000007, /* beq 8198 <sp_16_cont> */
1371 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1372 0x0afffff9, /* beq 8168 <sp_16_busy> */
1373 0xe1d160b0, /* ldrh r6, [r1] */
1374 0xe0257006, /* eor r7, r5, r6 */
1375 0xe0147007, /* ands r7, r4, r7 */
1376 0x0a000001, /* beq 8198 <sp_16_cont> */
1377 0xe3a05000, /* mov r5, #0 ; 0x0 */
1378 0x1a000004, /* bne 81ac <sp_16_done> */
1380 /* 00008198 <sp_16_cont>: */
1381 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1382 0x03a05080, /* moveq r5, #128 ; 0x80 */
1383 0x0a000001, /* beq 81ac <sp_16_done> */
1384 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1385 0xeaffffe8, /* b 8158 <sp_16_code> */
1387 /* 000081ac <sp_16_done>: */
1388 0xeafffffe /* b 81ac <sp_16_done> */
1391 static const uint32_t word_16_code_dq7only[] = {
1393 0xe0d050b2, /* ldrh r5, [r0], #2 */
1394 0xe1c890b0, /* strh r9, [r8] */
1395 0xe1cab0b0, /* strh r11, [r10] */
1396 0xe1c830b0, /* strh r3, [r8] */
1397 0xe1c150b0, /* strh r5, [r1] */
1398 0xe1a00000, /* nop (mov r0,r0) */
1401 0xe1d160b0, /* ldrh r6, [r1] */
1402 0xe0257006, /* eor r7, r5, r6 */
1403 0xe2177080, /* ands r7, #0x80 */
1404 0x1afffffb, /* bne 8168 <sp_16_busy> */
1406 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1407 0x03a05080, /* moveq r5, #128 ; 0x80 */
1408 0x0a000001, /* beq 81ac <sp_16_done> */
1409 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1410 0xeafffff0, /* b 8158 <sp_16_code> */
1412 /* 000081ac <sp_16_done>: */
1413 0xeafffffe /* b 81ac <sp_16_done> */
1416 static const uint32_t word_8_code[] = {
1417 /* 000081b0 <sp_16_code_end>: */
1418 0xe4d05001, /* ldrb r5, [r0], #1 */
1419 0xe5c89000, /* strb r9, [r8] */
1420 0xe5cab000, /* strb r11, [r10] */
1421 0xe5c83000, /* strb r3, [r8] */
1422 0xe5c15000, /* strb r5, [r1] */
1423 0xe1a00000, /* nop (mov r0,r0) */
1425 /* 000081c0 <sp_8_busy>: */
1426 0xe5d16000, /* ldrb r6, [r1] */
1427 0xe0257006, /* eor r7, r5, r6 */
1428 0xe0147007, /* ands r7, r4, r7 */
1429 0x0a000007, /* beq 81f0 <sp_8_cont> */
1430 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1431 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1432 0xe5d16000, /* ldrb r6, [r1] */
1433 0xe0257006, /* eor r7, r5, r6 */
1434 0xe0147007, /* ands r7, r4, r7 */
1435 0x0a000001, /* beq 81f0 <sp_8_cont> */
1436 0xe3a05000, /* mov r5, #0 ; 0x0 */
1437 0x1a000004, /* bne 8204 <sp_8_done> */
1439 /* 000081f0 <sp_8_cont>: */
1440 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1441 0x03a05080, /* moveq r5, #128 ; 0x80 */
1442 0x0a000001, /* beq 8204 <sp_8_done> */
1443 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1444 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1446 /* 00008204 <sp_8_done>: */
1447 0xeafffffe /* b 8204 <sp_8_done> */
1450 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1451 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1452 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1454 int target_code_size;
1455 const uint32_t *target_code_src;
1457 switch (bank->bus_width)
1460 target_code_src = word_8_code;
1461 target_code_size = sizeof(word_8_code);
1464 /* Check for DQ5 support */
1465 if( cfi_info->status_poll_mask & (1 << 5) )
1467 target_code_src = word_16_code;
1468 target_code_size = sizeof(word_16_code);
1472 /* No DQ5 support. Use DQ7 DATA# polling only. */
1473 target_code_src = word_16_code_dq7only;
1474 target_code_size = sizeof(word_16_code_dq7only);
1478 target_code_src = word_32_code;
1479 target_code_size = sizeof(word_32_code);
1482 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1483 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1486 /* flash write code */
1487 if (!cfi_info->write_algorithm)
1489 uint8_t *target_code;
1491 /* convert bus-width dependent algorithm code to correct endiannes */
1492 target_code = malloc(target_code_size);
1493 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1495 /* allocate working area */
1496 retval = target_alloc_working_area(target, target_code_size,
1497 &cfi_info->write_algorithm);
1498 if (retval != ERROR_OK)
1504 /* write algorithm code to working area */
1505 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1506 target_code_size, target_code)) != ERROR_OK)
1514 /* the following code still assumes target code is fixed 24*4 bytes */
1516 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1519 if (buffer_size <= 256)
1521 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1522 if (cfi_info->write_algorithm)
1523 target_free_working_area(target, cfi_info->write_algorithm);
1525 LOG_WARNING("not enough working area available, can't do block memory writes");
1526 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1530 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1531 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1532 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1533 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1534 init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
1535 init_reg_param(®_params[5], "r5", 32, PARAM_IN);
1536 init_reg_param(®_params[6], "r8", 32, PARAM_OUT);
1537 init_reg_param(®_params[7], "r9", 32, PARAM_OUT);
1538 init_reg_param(®_params[8], "r10", 32, PARAM_OUT);
1539 init_reg_param(®_params[9], "r11", 32, PARAM_OUT);
1543 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1545 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1547 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1548 buf_set_u32(reg_params[1].value, 0, 32, address);
1549 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1550 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1551 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1552 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1553 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1554 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1555 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1557 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1558 cfi_info->write_algorithm->address,
1559 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1560 10000, &armv4_5_info);
1562 status = buf_get_u32(reg_params[5].value, 0, 32);
1564 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1566 LOG_DEBUG("status: 0x%" PRIx32 , status);
1567 exit_code = ERROR_FLASH_OPERATION_FAILED;
1571 buffer += thisrun_count;
1572 address += thisrun_count;
1573 count -= thisrun_count;
1576 target_free_all_working_areas(target);
1578 destroy_reg_param(®_params[0]);
1579 destroy_reg_param(®_params[1]);
1580 destroy_reg_param(®_params[2]);
1581 destroy_reg_param(®_params[3]);
1582 destroy_reg_param(®_params[4]);
1583 destroy_reg_param(®_params[5]);
1584 destroy_reg_param(®_params[6]);
1585 destroy_reg_param(®_params[7]);
1586 destroy_reg_param(®_params[8]);
1587 destroy_reg_param(®_params[9]);
1592 static int cfi_intel_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1595 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1596 target_t *target = bank->target;
1599 cfi_intel_clear_status_register(bank);
1600 cfi_command(bank, 0x40, command);
1601 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1606 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1611 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1613 cfi_command(bank, 0xff, command);
1614 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1619 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1620 return ERROR_FLASH_OPERATION_FAILED;
1626 static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1629 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1630 target_t *target = bank->target;
1633 /* Calculate buffer size and boundary mask */
1634 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1635 uint32_t buffermask = buffersize-1;
1636 uint32_t bufferwsize;
1638 /* Check for valid range */
1639 if (address & buffermask)
1641 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1642 bank->base, address, cfi_info->max_buf_write_size);
1643 return ERROR_FLASH_OPERATION_FAILED;
1645 switch (bank->chip_width)
1647 case 4 : bufferwsize = buffersize / 4; break;
1648 case 2 : bufferwsize = buffersize / 2; break;
1649 case 1 : bufferwsize = buffersize; break;
1651 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1652 return ERROR_FLASH_OPERATION_FAILED;
1655 bufferwsize/=(bank->bus_width / bank->chip_width);
1658 /* Check for valid size */
1659 if (wordcount > bufferwsize)
1661 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1662 return ERROR_FLASH_OPERATION_FAILED;
1665 /* Write to flash buffer */
1666 cfi_intel_clear_status_register(bank);
1668 /* Initiate buffer operation _*/
1669 cfi_command(bank, 0xE8, command);
1670 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1674 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1676 cfi_command(bank, 0xff, command);
1677 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1682 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1683 return ERROR_FLASH_OPERATION_FAILED;
1686 /* Write buffer wordcount-1 and data words */
1687 cfi_command(bank, bufferwsize-1, command);
1688 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1693 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1698 /* Commit write operation */
1699 cfi_command(bank, 0xd0, command);
1700 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1704 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1706 cfi_command(bank, 0xff, command);
1707 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1712 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1713 return ERROR_FLASH_OPERATION_FAILED;
1719 static int cfi_spansion_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1722 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1723 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1724 target_t *target = bank->target;
1727 cfi_command(bank, 0xaa, command);
1728 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1733 cfi_command(bank, 0x55, command);
1734 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1739 cfi_command(bank, 0xa0, command);
1740 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1745 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1750 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1752 cfi_command(bank, 0xf0, command);
1753 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1758 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1759 return ERROR_FLASH_OPERATION_FAILED;
1765 static int cfi_spansion_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1768 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1769 target_t *target = bank->target;
1771 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1773 /* Calculate buffer size and boundary mask */
1774 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1775 uint32_t buffermask = buffersize-1;
1776 uint32_t bufferwsize;
1778 /* Check for valid range */
1779 if (address & buffermask)
1781 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1782 return ERROR_FLASH_OPERATION_FAILED;
1784 switch (bank->chip_width)
1786 case 4 : bufferwsize = buffersize / 4; break;
1787 case 2 : bufferwsize = buffersize / 2; break;
1788 case 1 : bufferwsize = buffersize; break;
1790 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1791 return ERROR_FLASH_OPERATION_FAILED;
1794 bufferwsize/=(bank->bus_width / bank->chip_width);
1796 /* Check for valid size */
1797 if (wordcount > bufferwsize)
1799 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1800 return ERROR_FLASH_OPERATION_FAILED;
1804 cfi_command(bank, 0xaa, command);
1805 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1810 cfi_command(bank, 0x55, command);
1811 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1816 // Buffer load command
1817 cfi_command(bank, 0x25, command);
1818 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1823 /* Write buffer wordcount-1 and data words */
1824 cfi_command(bank, bufferwsize-1, command);
1825 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1830 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1835 /* Commit write operation */
1836 cfi_command(bank, 0x29, command);
1837 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1842 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1844 cfi_command(bank, 0xf0, command);
1845 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1850 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1851 return ERROR_FLASH_OPERATION_FAILED;
1857 static int cfi_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1859 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1861 switch (cfi_info->pri_id)
1865 return cfi_intel_write_word(bank, word, address);
1868 return cfi_spansion_write_word(bank, word, address);
1871 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1875 return ERROR_FLASH_OPERATION_FAILED;
1878 static int cfi_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1880 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1882 switch (cfi_info->pri_id)
1886 return cfi_intel_write_words(bank, word, wordcount, address);
1889 return cfi_spansion_write_words(bank, word, wordcount, address);
1892 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1896 return ERROR_FLASH_OPERATION_FAILED;
1899 int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1901 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1902 target_t *target = bank->target;
1903 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1904 uint32_t write_p, copy_p;
1905 int align; /* number of unaligned bytes */
1906 int blk_count; /* number of bus_width bytes for block copy */
1907 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1911 if (bank->target->state != TARGET_HALTED)
1913 LOG_ERROR("Target not halted");
1914 return ERROR_TARGET_NOT_HALTED;
1917 if (offset + count > bank->size)
1918 return ERROR_FLASH_DST_OUT_OF_BANK;
1920 if (cfi_info->qry[0] != 'Q')
1921 return ERROR_FLASH_BANK_NOT_PROBED;
1923 /* start at the first byte of the first word (bus_width size) */
1924 write_p = address & ~(bank->bus_width - 1);
1925 if ((align = address - write_p) != 0)
1927 LOG_INFO("Fixup %d unaligned head bytes", align);
1929 for (i = 0; i < bank->bus_width; i++)
1930 current_word[i] = 0;
1933 /* copy bytes before the first write address */
1934 for (i = 0; i < align; ++i, ++copy_p)
1937 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1941 cfi_add_byte(bank, current_word, byte);
1944 /* add bytes from the buffer */
1945 for (; (i < bank->bus_width) && (count > 0); i++)
1947 cfi_add_byte(bank, current_word, *buffer++);
1952 /* if the buffer is already finished, copy bytes after the last write address */
1953 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1956 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1960 cfi_add_byte(bank, current_word, byte);
1963 retval = cfi_write_word(bank, current_word, write_p);
1964 if (retval != ERROR_OK)
1969 /* handle blocks of bus_size aligned bytes */
1970 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1971 switch (cfi_info->pri_id)
1973 /* try block writes (fails without working area) */
1976 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1979 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1982 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1983 retval = ERROR_FLASH_OPERATION_FAILED;
1986 if (retval == ERROR_OK)
1988 /* Increment pointers and decrease count on succesful block write */
1989 buffer += blk_count;
1990 write_p += blk_count;
1995 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1997 //adjust buffersize for chip width
1998 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1999 uint32_t buffermask = buffersize-1;
2000 uint32_t bufferwsize;
2002 switch (bank->chip_width)
2004 case 4 : bufferwsize = buffersize / 4; break;
2005 case 2 : bufferwsize = buffersize / 2; break;
2006 case 1 : bufferwsize = buffersize; break;
2008 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
2009 return ERROR_FLASH_OPERATION_FAILED;
2012 bufferwsize/=(bank->bus_width / bank->chip_width);
2014 /* fall back to memory writes */
2015 while (count >= (uint32_t)bank->bus_width)
2018 if ((write_p & 0xff) == 0)
2020 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
2023 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2025 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2026 if (retval == ERROR_OK)
2028 buffer += buffersize;
2029 write_p += buffersize;
2030 count -= buffersize;
2034 /* try the slow way? */
2037 for (i = 0; i < bank->bus_width; i++)
2038 current_word[i] = 0;
2040 for (i = 0; i < bank->bus_width; i++)
2042 cfi_add_byte(bank, current_word, *buffer++);
2045 retval = cfi_write_word(bank, current_word, write_p);
2046 if (retval != ERROR_OK)
2049 write_p += bank->bus_width;
2050 count -= bank->bus_width;
2058 /* return to read array mode, so we can read from flash again for padding */
2059 cfi_command(bank, 0xf0, current_word);
2060 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2064 cfi_command(bank, 0xff, current_word);
2065 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2070 /* handle unaligned tail bytes */
2073 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2076 for (i = 0; i < bank->bus_width; i++)
2077 current_word[i] = 0;
2079 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2081 cfi_add_byte(bank, current_word, *buffer++);
2084 for (; i < bank->bus_width; ++i, ++copy_p)
2087 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2091 cfi_add_byte(bank, current_word, byte);
2093 retval = cfi_write_word(bank, current_word, write_p);
2094 if (retval != ERROR_OK)
2098 /* return to read array mode */
2099 cfi_command(bank, 0xf0, current_word);
2100 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2104 cfi_command(bank, 0xff, current_word);
2105 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2108 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2111 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2112 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2114 pri_ext->_reversed_geometry = 1;
2117 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2120 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2121 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2124 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2126 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2128 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2130 int j = (cfi_info->num_erase_regions - 1) - i;
2133 swap = cfi_info->erase_region_info[i];
2134 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2135 cfi_info->erase_region_info[j] = swap;
2140 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2142 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2143 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2144 cfi_unlock_addresses_t *unlock_addresses = param;
2146 pri_ext->_unlock1 = unlock_addresses->unlock1;
2147 pri_ext->_unlock2 = unlock_addresses->unlock2;
2151 static int cfi_query_string(struct flash_bank_s *bank, int address)
2153 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2154 target_t *target = bank->target;
2158 cfi_command(bank, 0x98, command);
2159 if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
2164 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2165 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2166 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2168 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2170 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2172 cfi_command(bank, 0xf0, command);
2173 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2177 cfi_command(bank, 0xff, command);
2178 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2182 LOG_ERROR("Could not probe bank: no QRY");
2183 return ERROR_FLASH_BANK_INVALID;
2189 static int cfi_probe(struct flash_bank_s *bank)
2191 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2192 target_t *target = bank->target;
2194 int num_sectors = 0;
2197 uint32_t unlock1 = 0x555;
2198 uint32_t unlock2 = 0x2aa;
2201 if (bank->target->state != TARGET_HALTED)
2203 LOG_ERROR("Target not halted");
2204 return ERROR_TARGET_NOT_HALTED;
2207 cfi_info->probed = 0;
2209 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2210 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2212 if (cfi_info->jedec_probe)
2218 /* switch to read identifier codes mode ("AUTOSELECT") */
2219 cfi_command(bank, 0xaa, command);
2220 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2224 cfi_command(bank, 0x55, command);
2225 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2229 cfi_command(bank, 0x90, command);
2230 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2235 if (bank->chip_width == 1)
2237 uint8_t manufacturer, device_id;
2238 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2242 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2246 cfi_info->manufacturer = manufacturer;
2247 cfi_info->device_id = device_id;
2249 else if (bank->chip_width == 2)
2251 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2255 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2261 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2262 /* switch back to read array mode */
2263 cfi_command(bank, 0xf0, command);
2264 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2268 cfi_command(bank, 0xff, command);
2269 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2274 /* check device/manufacturer ID for known non-CFI flashes. */
2275 cfi_fixup_non_cfi(bank);
2277 /* query only if this is a CFI compatible flash,
2278 * otherwise the relevant info has already been filled in
2280 if (cfi_info->not_cfi == 0)
2284 /* enter CFI query mode
2285 * according to JEDEC Standard No. 68.01,
2286 * a single bus sequence with address = 0x55, data = 0x98 should put
2287 * the device into CFI query mode.
2289 * SST flashes clearly violate this, and we will consider them incompatbile for now
2292 retval = cfi_query_string(bank, 0x55);
2293 if (retval != ERROR_OK)
2296 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2297 * be harmless enough:
2299 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2301 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2302 retval = cfi_query_string(bank, 0x555);
2304 if (retval != ERROR_OK)
2307 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2308 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2309 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2310 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2312 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2314 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2315 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2316 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2317 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2318 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2319 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2320 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2321 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2322 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2323 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2324 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2325 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2327 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2328 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2329 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2330 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2331 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2332 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2333 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2334 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2335 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2336 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2337 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2339 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2340 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2341 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2342 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2344 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2346 if (cfi_info->num_erase_regions)
2348 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2349 for (i = 0; i < cfi_info->num_erase_regions; i++)
2351 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2352 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2354 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2355 (cfi_info->erase_region_info[i] >> 16) * 256);
2360 cfi_info->erase_region_info = NULL;
2363 /* We need to read the primary algorithm extended query table before calculating
2364 * the sector layout to be able to apply fixups
2366 switch (cfi_info->pri_id)
2368 /* Intel command set (standard and extended) */
2371 cfi_read_intel_pri_ext(bank);
2373 /* AMD/Spansion, Atmel, ... command set */
2375 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2376 cfi_read_0002_pri_ext(bank);
2379 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2383 /* return to read array mode
2384 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2386 cfi_command(bank, 0xf0, command);
2387 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2391 cfi_command(bank, 0xff, command);
2392 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2396 } /* end CFI case */
2398 /* apply fixups depending on the primary command set */
2399 switch (cfi_info->pri_id)
2401 /* Intel command set (standard and extended) */
2404 cfi_fixup(bank, cfi_0001_fixups);
2406 /* AMD/Spansion, Atmel, ... command set */
2408 cfi_fixup(bank, cfi_0002_fixups);
2411 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2415 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2417 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2420 if (cfi_info->num_erase_regions == 0)
2422 /* a device might have only one erase block, spanning the whole device */
2423 bank->num_sectors = 1;
2424 bank->sectors = malloc(sizeof(flash_sector_t));
2426 bank->sectors[sector].offset = 0x0;
2427 bank->sectors[sector].size = bank->size;
2428 bank->sectors[sector].is_erased = -1;
2429 bank->sectors[sector].is_protected = -1;
2433 uint32_t offset = 0;
2435 for (i = 0; i < cfi_info->num_erase_regions; i++)
2437 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2440 bank->num_sectors = num_sectors;
2441 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2443 for (i = 0; i < cfi_info->num_erase_regions; i++)
2446 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2448 bank->sectors[sector].offset = offset;
2449 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2450 offset += bank->sectors[sector].size;
2451 bank->sectors[sector].is_erased = -1;
2452 bank->sectors[sector].is_protected = -1;
2456 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2458 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2459 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2463 cfi_info->probed = 1;
2468 static int cfi_auto_probe(struct flash_bank_s *bank)
2470 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2471 if (cfi_info->probed)
2473 return cfi_probe(bank);
2477 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2480 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2481 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2482 target_t *target = bank->target;
2483 uint8_t command[CFI_MAX_BUS_WIDTH];
2486 /* check if block lock bits are supported on this device */
2487 if (!(pri_ext->blk_status_reg_mask & 0x1))
2488 return ERROR_FLASH_OPERATION_FAILED;
2490 cfi_command(bank, 0x90, command);
2491 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2496 for (i = 0; i < bank->num_sectors; i++)
2498 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2500 if (block_status & 1)
2501 bank->sectors[i].is_protected = 1;
2503 bank->sectors[i].is_protected = 0;
2506 cfi_command(bank, 0xff, command);
2507 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2510 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2513 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2514 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2515 target_t *target = bank->target;
2519 cfi_command(bank, 0xaa, command);
2520 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2525 cfi_command(bank, 0x55, command);
2526 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2531 cfi_command(bank, 0x90, command);
2532 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2537 for (i = 0; i < bank->num_sectors; i++)
2539 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2541 if (block_status & 1)
2542 bank->sectors[i].is_protected = 1;
2544 bank->sectors[i].is_protected = 0;
2547 cfi_command(bank, 0xf0, command);
2548 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2551 static int cfi_protect_check(struct flash_bank_s *bank)
2553 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2555 if (bank->target->state != TARGET_HALTED)
2557 LOG_ERROR("Target not halted");
2558 return ERROR_TARGET_NOT_HALTED;
2561 if (cfi_info->qry[0] != 'Q')
2562 return ERROR_FLASH_BANK_NOT_PROBED;
2564 switch (cfi_info->pri_id)
2568 return cfi_intel_protect_check(bank);
2571 return cfi_spansion_protect_check(bank);
2574 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2581 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2584 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2586 if (cfi_info->qry[0] == (char)-1)
2588 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2592 if (cfi_info->not_cfi == 0)
2593 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2595 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2597 buf_size -= printed;
2599 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2600 cfi_info->manufacturer, cfi_info->device_id);
2602 buf_size -= printed;
2604 if (cfi_info->not_cfi == 0)
2606 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2608 buf_size -= printed;
2610 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2611 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2612 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2613 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2614 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2616 buf_size -= printed;
2618 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2619 1 << cfi_info->word_write_timeout_typ,
2620 1 << cfi_info->buf_write_timeout_typ,
2621 1 << cfi_info->block_erase_timeout_typ,
2622 1 << cfi_info->chip_erase_timeout_typ);
2624 buf_size -= printed;
2626 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2627 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2628 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2629 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2630 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2632 buf_size -= printed;
2634 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2636 cfi_info->interface_desc,
2637 1 << cfi_info->max_buf_write_size);
2639 buf_size -= printed;
2641 switch (cfi_info->pri_id)
2645 cfi_intel_info(bank, buf, buf_size);
2648 cfi_spansion_info(bank, buf, buf_size);
2651 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);