1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "replacements.h"
35 #include "algorithm.h"
36 #include "binarybuffer.h"
43 static int cfi_register_commands(struct command_context_s *cmd_ctx);
44 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
45 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
46 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
47 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
48 static int cfi_probe(struct flash_bank_s *bank);
49 static int cfi_auto_probe(struct flash_bank_s *bank);
50 static int cfi_protect_check(struct flash_bank_s *bank);
51 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
53 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 #define CFI_MAX_BUS_WIDTH 4
56 #define CFI_MAX_CHIP_WIDTH 4
58 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
59 #define CFI_MAX_INTEL_CODESIZE 256
61 flash_driver_t cfi_flash =
64 .register_commands = cfi_register_commands,
65 .flash_bank_command = cfi_flash_bank_command,
67 .protect = cfi_protect,
70 .auto_probe = cfi_auto_probe,
71 .erase_check = default_flash_blank_check,
72 .protect_check = cfi_protect_check,
76 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
78 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
79 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
82 /* CFI fixups foward declarations */
83 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
84 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
85 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
87 /* fixup after reading cmdset 0002 primary query table */
88 static cfi_fixup_t cfi_0002_fixups[] = {
89 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
90 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
91 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
92 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
93 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
94 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
95 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
96 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
97 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
98 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
99 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
103 /* fixup after reading cmdset 0001 primary query table */
104 static cfi_fixup_t cfi_0001_fixups[] = {
108 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
110 cfi_flash_bank_t *cfi_info = bank->driver_priv;
113 for (f = fixups; f->fixup; f++)
115 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
116 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
118 f->fixup(bank, f->param);
123 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
124 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
126 /* while the sector list isn't built, only accesses to sector 0 work */
128 return bank->base + offset * bank->bus_width;
133 LOG_ERROR("BUG: sector list not yet built");
136 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
141 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
145 /* clear whole buffer, to ensure bits that exceed the bus_width
148 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
151 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
153 for (i = bank->bus_width; i > 0; i--)
155 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
160 for (i = 1; i <= bank->bus_width; i++)
162 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
167 /* read unsigned 8-bit value from the bank
168 * flash banks are expected to be made of similar chips
169 * the query result should be the same for all
171 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
173 target_t *target = bank->target;
174 u8 data[CFI_MAX_BUS_WIDTH];
176 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
178 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
181 return data[bank->bus_width - 1];
184 /* read unsigned 8-bit value from the bank
185 * in case of a bank made of multiple chips,
186 * the individual values are ORed
188 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
190 target_t *target = bank->target;
191 u8 data[CFI_MAX_BUS_WIDTH];
194 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
196 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
198 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
206 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
207 value |= data[bank->bus_width - 1 - i];
213 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
215 target_t *target = bank->target;
216 u8 data[CFI_MAX_BUS_WIDTH * 2];
218 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
220 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
221 return data[0] | data[bank->bus_width] << 8;
223 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
226 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
228 target_t *target = bank->target;
229 u8 data[CFI_MAX_BUS_WIDTH * 4];
231 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
233 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
234 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
236 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
237 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
240 static void cfi_intel_clear_status_register(flash_bank_t *bank)
242 target_t *target = bank->target;
245 if (target->state != TARGET_HALTED)
247 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
251 cfi_command(bank, 0x50, command);
252 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
255 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
259 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
261 LOG_DEBUG("status: 0x%x", status);
265 /* mask out bit 0 (reserved) */
266 status = status & 0xfe;
268 LOG_DEBUG("status: 0x%x", status);
270 if ((status & 0x80) != 0x80)
272 LOG_ERROR("timeout while waiting for WSM to become ready");
274 else if (status != 0x80)
276 LOG_ERROR("status register: 0x%x", status);
278 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
280 LOG_ERROR("Program suspended");
282 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
284 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
286 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
288 LOG_ERROR("Block Erase Suspended");
290 cfi_intel_clear_status_register(bank);
296 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
298 u8 status, oldstatus;
299 cfi_flash_bank_t *cfi_info = bank->driver_priv;
301 oldstatus = cfi_get_u8(bank, 0, 0x0);
304 status = cfi_get_u8(bank, 0, 0x0);
305 if ((status ^ oldstatus) & 0x40) {
306 if (status & cfi_info->status_poll_mask & 0x20) {
307 oldstatus = cfi_get_u8(bank, 0, 0x0);
308 status = cfi_get_u8(bank, 0, 0x0);
309 if ((status ^ oldstatus) & 0x40) {
310 LOG_ERROR("dq5 timeout, status: 0x%x", status);
311 return(ERROR_FLASH_OPERATION_FAILED);
313 LOG_DEBUG("status: 0x%x", status);
317 } else { /* no toggle: finished, OK */
318 LOG_DEBUG("status: 0x%x", status);
324 } while (timeout-- > 0);
326 LOG_ERROR("timeout, status: 0x%x", status);
328 return(ERROR_FLASH_BUSY);
331 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
334 cfi_flash_bank_t *cfi_info = bank->driver_priv;
335 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
336 target_t *target = bank->target;
339 cfi_info->pri_ext = pri_ext;
341 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
342 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
343 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
345 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
347 cfi_command(bank, 0xf0, command);
348 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
352 cfi_command(bank, 0xff, command);
353 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
357 LOG_ERROR("Could not read bank flash bank information");
358 return ERROR_FLASH_BANK_INVALID;
361 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
362 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
364 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
366 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
367 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
368 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
370 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
372 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
373 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
375 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
376 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
377 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
379 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
380 if (pri_ext->num_protection_fields != 1)
382 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
385 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
386 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
387 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
389 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
394 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
397 cfi_flash_bank_t *cfi_info = bank->driver_priv;
398 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
399 target_t *target = bank->target;
402 cfi_info->pri_ext = pri_ext;
404 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
405 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
406 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
408 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
410 cfi_command(bank, 0xf0, command);
411 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
415 LOG_ERROR("Could not read spansion bank information");
416 return ERROR_FLASH_BANK_INVALID;
419 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
420 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
422 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
424 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
425 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
426 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
427 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
428 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
429 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
430 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
431 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
432 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
433 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
434 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
436 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
437 pri_ext->EraseSuspend, pri_ext->BlkProt);
439 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
440 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
442 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
445 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
446 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
447 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
449 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
451 /* default values for implementation specific workarounds */
452 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
453 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
454 pri_ext->_reversed_geometry = 0;
459 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
462 cfi_atmel_pri_ext_t atmel_pri_ext;
463 cfi_flash_bank_t *cfi_info = bank->driver_priv;
464 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
465 target_t *target = bank->target;
468 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
469 * but a different primary extended query table.
470 * We read the atmel table, and prepare a valid AMD/Spansion query table.
473 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
475 cfi_info->pri_ext = pri_ext;
477 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
478 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
479 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
481 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
483 cfi_command(bank, 0xf0, command);
484 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
488 LOG_ERROR("Could not read atmel bank information");
489 return ERROR_FLASH_BANK_INVALID;
492 pri_ext->pri[0] = atmel_pri_ext.pri[0];
493 pri_ext->pri[1] = atmel_pri_ext.pri[1];
494 pri_ext->pri[2] = atmel_pri_ext.pri[2];
496 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
497 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
499 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
501 pri_ext->major_version = atmel_pri_ext.major_version;
502 pri_ext->minor_version = atmel_pri_ext.minor_version;
504 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
505 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
506 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
507 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
509 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
510 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
512 if (atmel_pri_ext.features & 0x02)
513 pri_ext->EraseSuspend = 2;
515 if (atmel_pri_ext.bottom_boot)
516 pri_ext->TopBottom = 2;
518 pri_ext->TopBottom = 3;
520 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
521 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
526 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
528 cfi_flash_bank_t *cfi_info = bank->driver_priv;
530 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
532 return cfi_read_atmel_pri_ext(bank);
536 return cfi_read_spansion_pri_ext(bank);
540 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
543 cfi_flash_bank_t *cfi_info = bank->driver_priv;
544 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
546 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
550 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
551 pri_ext->pri[1], pri_ext->pri[2],
552 pri_ext->major_version, pri_ext->minor_version);
556 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
557 (pri_ext->SiliconRevision) >> 2,
558 (pri_ext->SiliconRevision) & 0x03);
562 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
563 pri_ext->EraseSuspend,
568 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
569 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
570 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
575 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
578 cfi_flash_bank_t *cfi_info = bank->driver_priv;
579 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
581 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
585 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
589 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
593 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
594 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
595 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
599 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
604 static int cfi_register_commands(struct command_context_s *cmd_ctx)
606 /*command_t *cfi_cmd = */
607 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
609 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
610 "print part id of cfi flash bank <num>");
615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
617 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
619 cfi_flash_bank_t *cfi_info;
626 LOG_WARNING("incomplete flash_bank cfi configuration");
627 return ERROR_FLASH_BANK_INVALID;
630 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
631 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
633 LOG_ERROR("chip and bus width have to specified in bytes");
634 return ERROR_FLASH_BANK_INVALID;
637 cfi_info = malloc(sizeof(cfi_flash_bank_t));
638 cfi_info->probed = 0;
639 bank->driver_priv = cfi_info;
641 cfi_info->write_algorithm = NULL;
643 cfi_info->x16_as_x8 = 0;
644 cfi_info->jedec_probe = 0;
645 cfi_info->not_cfi = 0;
647 for (i = 6; i < argc; i++)
649 if (strcmp(args[i], "x16_as_x8") == 0)
651 cfi_info->x16_as_x8 = 1;
653 else if (strcmp(args[i], "jedec_probe") == 0)
655 cfi_info->jedec_probe = 1;
659 cfi_info->write_algorithm = NULL;
661 /* bank wasn't probed yet */
662 cfi_info->qry[0] = -1;
667 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
670 cfi_flash_bank_t *cfi_info = bank->driver_priv;
671 target_t *target = bank->target;
675 cfi_intel_clear_status_register(bank);
677 for (i = first; i <= last; i++)
679 cfi_command(bank, 0x20, command);
680 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
685 cfi_command(bank, 0xd0, command);
686 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
691 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
692 bank->sectors[i].is_erased = 1;
695 cfi_command(bank, 0xff, command);
696 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
701 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
702 return ERROR_FLASH_OPERATION_FAILED;
706 cfi_command(bank, 0xff, command);
707 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
711 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
714 cfi_flash_bank_t *cfi_info = bank->driver_priv;
715 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
716 target_t *target = bank->target;
720 for (i = first; i <= last; i++)
722 cfi_command(bank, 0xaa, command);
723 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
728 cfi_command(bank, 0x55, command);
729 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
734 cfi_command(bank, 0x80, command);
735 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
740 cfi_command(bank, 0xaa, command);
741 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
746 cfi_command(bank, 0x55, command);
747 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
752 cfi_command(bank, 0x30, command);
753 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
758 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
759 bank->sectors[i].is_erased = 1;
762 cfi_command(bank, 0xf0, command);
763 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
768 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
769 return ERROR_FLASH_OPERATION_FAILED;
773 cfi_command(bank, 0xf0, command);
774 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
777 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
779 cfi_flash_bank_t *cfi_info = bank->driver_priv;
781 if (bank->target->state != TARGET_HALTED)
783 LOG_ERROR("Target not halted");
784 return ERROR_TARGET_NOT_HALTED;
787 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
789 return ERROR_FLASH_SECTOR_INVALID;
792 if (cfi_info->qry[0] != 'Q')
793 return ERROR_FLASH_BANK_NOT_PROBED;
795 switch(cfi_info->pri_id)
799 return cfi_intel_erase(bank, first, last);
802 return cfi_spansion_erase(bank, first, last);
805 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
812 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
815 cfi_flash_bank_t *cfi_info = bank->driver_priv;
816 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
817 target_t *target = bank->target;
822 /* if the device supports neither legacy lock/unlock (bit 3) nor
823 * instant individual block locking (bit 5).
825 if (!(pri_ext->feature_support & 0x28))
826 return ERROR_FLASH_OPERATION_FAILED;
828 cfi_intel_clear_status_register(bank);
830 for (i = first; i <= last; i++)
832 cfi_command(bank, 0x60, command);
833 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
834 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
840 cfi_command(bank, 0x01, command);
841 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
842 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
846 bank->sectors[i].is_protected = 1;
850 cfi_command(bank, 0xd0, command);
851 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
852 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
856 bank->sectors[i].is_protected = 0;
859 /* instant individual block locking doesn't require reading of the status register */
860 if (!(pri_ext->feature_support & 0x20))
862 /* Clear lock bits operation may take up to 1.4s */
863 cfi_intel_wait_status_busy(bank, 1400);
868 /* read block lock bit, to verify status */
869 cfi_command(bank, 0x90, command);
870 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
874 block_status = cfi_get_u8(bank, i, 0x2);
876 if ((block_status & 0x1) != set)
878 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
879 cfi_command(bank, 0x70, command);
880 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
884 cfi_intel_wait_status_busy(bank, 10);
887 return ERROR_FLASH_OPERATION_FAILED;
897 /* if the device doesn't support individual block lock bits set/clear,
898 * all blocks have been unlocked in parallel, so we set those that should be protected
900 if ((!set) && (!(pri_ext->feature_support & 0x20)))
902 for (i = 0; i < bank->num_sectors; i++)
904 if (bank->sectors[i].is_protected == 1)
906 cfi_intel_clear_status_register(bank);
908 cfi_command(bank, 0x60, command);
909 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
914 cfi_command(bank, 0x01, command);
915 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
920 cfi_intel_wait_status_busy(bank, 100);
925 cfi_command(bank, 0xff, command);
926 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
929 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
931 cfi_flash_bank_t *cfi_info = bank->driver_priv;
933 if (bank->target->state != TARGET_HALTED)
935 LOG_ERROR("Target not halted");
936 return ERROR_TARGET_NOT_HALTED;
939 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
941 return ERROR_FLASH_SECTOR_INVALID;
944 if (cfi_info->qry[0] != 'Q')
945 return ERROR_FLASH_BANK_NOT_PROBED;
947 switch(cfi_info->pri_id)
951 cfi_intel_protect(bank, set, first, last);
954 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
961 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
962 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
964 /* target_t *target = bank->target; */
969 * The data to flash must not be changed in endian! We write a bytestrem in
970 * target byte order already. Only the control and status byte lane of the flash
971 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
972 * word (data seems to be in the upper or lower byte lane for u16 accesses).
976 if (target->endianness == TARGET_LITTLE_ENDIAN)
980 for (i = 0; i < bank->bus_width - 1; i++)
981 word[i] = word[i + 1];
982 word[bank->bus_width - 1] = byte;
988 for (i = bank->bus_width - 1; i > 0; i--)
989 word[i] = word[i - 1];
995 /* Convert code image to target endian */
996 /* FIXME create general block conversion fcts in target.c?) */
997 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
1000 for (i=0; i< count; i++)
1002 target_buffer_set_u32(target, dest, *src);
1008 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1010 target_t *target = bank->target;
1012 u8 buf[CFI_MAX_BUS_WIDTH];
1013 cfi_command(bank, cmd, buf);
1014 switch (bank->bus_width)
1020 return target_buffer_get_u16(target, buf);
1023 return target_buffer_get_u32(target, buf);
1026 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1031 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1033 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1034 target_t *target = bank->target;
1035 reg_param_t reg_params[7];
1036 armv4_5_algorithm_t armv4_5_info;
1037 working_area_t *source;
1038 u32 buffer_size = 32768;
1039 u32 write_command_val, busy_pattern_val, error_pattern_val;
1041 /* algorithm register usage:
1042 * r0: source address (in RAM)
1043 * r1: target address (in Flash)
1045 * r3: flash write command
1046 * r4: status byte (returned to host)
1047 * r5: busy test pattern
1048 * r6: error test pattern
1051 static const u32 word_32_code[] = {
1052 0xe4904004, /* loop: ldr r4, [r0], #4 */
1053 0xe5813000, /* str r3, [r1] */
1054 0xe5814000, /* str r4, [r1] */
1055 0xe5914000, /* busy: ldr r4, [r1] */
1056 0xe0047005, /* and r7, r4, r5 */
1057 0xe1570005, /* cmp r7, r5 */
1058 0x1afffffb, /* bne busy */
1059 0xe1140006, /* tst r4, r6 */
1060 0x1a000003, /* bne done */
1061 0xe2522001, /* subs r2, r2, #1 */
1062 0x0a000001, /* beq done */
1063 0xe2811004, /* add r1, r1 #4 */
1064 0xeafffff2, /* b loop */
1065 0xeafffffe /* done: b -2 */
1068 static const u32 word_16_code[] = {
1069 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1070 0xe1c130b0, /* strh r3, [r1] */
1071 0xe1c140b0, /* strh r4, [r1] */
1072 0xe1d140b0, /* busy ldrh r4, [r1] */
1073 0xe0047005, /* and r7, r4, r5 */
1074 0xe1570005, /* cmp r7, r5 */
1075 0x1afffffb, /* bne busy */
1076 0xe1140006, /* tst r4, r6 */
1077 0x1a000003, /* bne done */
1078 0xe2522001, /* subs r2, r2, #1 */
1079 0x0a000001, /* beq done */
1080 0xe2811002, /* add r1, r1 #2 */
1081 0xeafffff2, /* b loop */
1082 0xeafffffe /* done: b -2 */
1085 static const u32 word_8_code[] = {
1086 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1087 0xe5c13000, /* strb r3, [r1] */
1088 0xe5c14000, /* strb r4, [r1] */
1089 0xe5d14000, /* busy ldrb r4, [r1] */
1090 0xe0047005, /* and r7, r4, r5 */
1091 0xe1570005, /* cmp r7, r5 */
1092 0x1afffffb, /* bne busy */
1093 0xe1140006, /* tst r4, r6 */
1094 0x1a000003, /* bne done */
1095 0xe2522001, /* subs r2, r2, #1 */
1096 0x0a000001, /* beq done */
1097 0xe2811001, /* add r1, r1 #1 */
1098 0xeafffff2, /* b loop */
1099 0xeafffffe /* done: b -2 */
1101 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1102 const u32 *target_code_src;
1103 u32 target_code_size;
1104 int retval = ERROR_OK;
1107 cfi_intel_clear_status_register(bank);
1109 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1110 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1111 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1113 /* If we are setting up the write_algorith, we need target_code_src */
1114 /* if not we only need target_code_size. */
1116 /* However, we don't want to create multiple code paths, so we */
1117 /* do the unecessary evaluation of target_code_src, which the */
1118 /* compiler will probably nicely optimize away if not needed */
1120 /* prepare algorithm code for target endian */
1121 switch (bank->bus_width)
1124 target_code_src = word_8_code;
1125 target_code_size = sizeof(word_8_code);
1128 target_code_src = word_16_code;
1129 target_code_size = sizeof(word_16_code);
1132 target_code_src = word_32_code;
1133 target_code_size = sizeof(word_32_code);
1136 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1137 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1140 /* flash write code */
1141 if (!cfi_info->write_algorithm)
1143 if ( target_code_size > sizeof(target_code) )
1145 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1146 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1148 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1150 /* Get memory for block write handler */
1151 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1152 if (retval != ERROR_OK)
1154 LOG_WARNING("No working area available, can't do block memory writes");
1155 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1158 /* write algorithm code to working area */
1159 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1160 if (retval != ERROR_OK)
1162 LOG_ERROR("Unable to write block write code to target");
1167 /* Get a workspace buffer for the data to flash starting with 32k size.
1168 Half size until buffer would be smaller 256 Bytem then fail back */
1169 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1170 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1173 if (buffer_size <= 256)
1175 LOG_WARNING("no large enough working area available, can't do block memory writes");
1176 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1181 /* setup algo registers */
1182 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1183 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1184 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1185 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1186 init_reg_param(®_params[4], "r4", 32, PARAM_IN);
1187 init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
1188 init_reg_param(®_params[6], "r6", 32, PARAM_OUT);
1190 /* prepare command and status register patterns */
1191 write_command_val = cfi_command_val(bank, 0x40);
1192 busy_pattern_val = cfi_command_val(bank, 0x80);
1193 error_pattern_val = cfi_command_val(bank, 0x7e);
1195 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1197 /* Programming main loop */
1200 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1203 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1208 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1209 buf_set_u32(reg_params[1].value, 0, 32, address);
1210 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1212 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1213 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1214 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1216 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1218 /* Execute algorithm, assume breakpoint for last instruction */
1219 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1220 cfi_info->write_algorithm->address,
1221 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1222 10000, /* 10s should be enough for max. 32k of data */
1225 /* On failure try a fall back to direct word writes */
1226 if (retval != ERROR_OK)
1228 cfi_intel_clear_status_register(bank);
1229 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1230 retval = ERROR_FLASH_OPERATION_FAILED;
1231 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1232 /* FIXME To allow fall back or recovery, we must save the actual status
1233 somewhere, so that a higher level code can start recovery. */
1237 /* Check return value from algo code */
1238 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1241 /* read status register (outputs debug inforation) */
1242 cfi_intel_wait_status_busy(bank, 100);
1243 cfi_intel_clear_status_register(bank);
1244 retval = ERROR_FLASH_OPERATION_FAILED;
1248 buffer += thisrun_count;
1249 address += thisrun_count;
1250 count -= thisrun_count;
1253 /* free up resources */
1256 target_free_working_area(target, source);
1258 if (cfi_info->write_algorithm)
1260 target_free_working_area(target, cfi_info->write_algorithm);
1261 cfi_info->write_algorithm = NULL;
1264 destroy_reg_param(®_params[0]);
1265 destroy_reg_param(®_params[1]);
1266 destroy_reg_param(®_params[2]);
1267 destroy_reg_param(®_params[3]);
1268 destroy_reg_param(®_params[4]);
1269 destroy_reg_param(®_params[5]);
1270 destroy_reg_param(®_params[6]);
1275 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1277 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1278 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1279 target_t *target = bank->target;
1280 reg_param_t reg_params[10];
1281 armv4_5_algorithm_t armv4_5_info;
1282 working_area_t *source;
1283 u32 buffer_size = 32768;
1285 int retval, retvaltemp;
1286 int exit_code = ERROR_OK;
1288 /* input parameters - */
1289 /* R0 = source address */
1290 /* R1 = destination address */
1291 /* R2 = number of writes */
1292 /* R3 = flash write command */
1293 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1294 /* output parameters - */
1295 /* R5 = 0x80 ok 0x00 bad */
1296 /* temp registers - */
1297 /* R6 = value read from flash to test status */
1298 /* R7 = holding register */
1299 /* unlock registers - */
1300 /* R8 = unlock1_addr */
1301 /* R9 = unlock1_cmd */
1302 /* R10 = unlock2_addr */
1303 /* R11 = unlock2_cmd */
1305 static const u32 word_32_code[] = {
1306 /* 00008100 <sp_32_code>: */
1307 0xe4905004, /* ldr r5, [r0], #4 */
1308 0xe5889000, /* str r9, [r8] */
1309 0xe58ab000, /* str r11, [r10] */
1310 0xe5883000, /* str r3, [r8] */
1311 0xe5815000, /* str r5, [r1] */
1312 0xe1a00000, /* nop */
1314 /* 00008110 <sp_32_busy>: */
1315 0xe5916000, /* ldr r6, [r1] */
1316 0xe0257006, /* eor r7, r5, r6 */
1317 0xe0147007, /* ands r7, r4, r7 */
1318 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1319 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1320 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1321 0xe5916000, /* ldr r6, [r1] */
1322 0xe0257006, /* eor r7, r5, r6 */
1323 0xe0147007, /* ands r7, r4, r7 */
1324 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1325 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1326 0x1a000004, /* bne 8154 <sp_32_done> */
1328 /* 00008140 <sp_32_cont>: */
1329 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1330 0x03a05080, /* moveq r5, #128 ; 0x80 */
1331 0x0a000001, /* beq 8154 <sp_32_done> */
1332 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1333 0xeaffffe8, /* b 8100 <sp_32_code> */
1335 /* 00008154 <sp_32_done>: */
1336 0xeafffffe /* b 8154 <sp_32_done> */
1339 static const u32 word_16_code[] = {
1340 /* 00008158 <sp_16_code>: */
1341 0xe0d050b2, /* ldrh r5, [r0], #2 */
1342 0xe1c890b0, /* strh r9, [r8] */
1343 0xe1cab0b0, /* strh r11, [r10] */
1344 0xe1c830b0, /* strh r3, [r8] */
1345 0xe1c150b0, /* strh r5, [r1] */
1346 0xe1a00000, /* nop (mov r0,r0) */
1348 /* 00008168 <sp_16_busy>: */
1349 0xe1d160b0, /* ldrh r6, [r1] */
1350 0xe0257006, /* eor r7, r5, r6 */
1351 0xe0147007, /* ands r7, r4, r7 */
1352 0x0a000007, /* beq 8198 <sp_16_cont> */
1353 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1354 0x0afffff9, /* beq 8168 <sp_16_busy> */
1355 0xe1d160b0, /* ldrh r6, [r1] */
1356 0xe0257006, /* eor r7, r5, r6 */
1357 0xe0147007, /* ands r7, r4, r7 */
1358 0x0a000001, /* beq 8198 <sp_16_cont> */
1359 0xe3a05000, /* mov r5, #0 ; 0x0 */
1360 0x1a000004, /* bne 81ac <sp_16_done> */
1362 /* 00008198 <sp_16_cont>: */
1363 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1364 0x03a05080, /* moveq r5, #128 ; 0x80 */
1365 0x0a000001, /* beq 81ac <sp_16_done> */
1366 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1367 0xeaffffe8, /* b 8158 <sp_16_code> */
1369 /* 000081ac <sp_16_done>: */
1370 0xeafffffe /* b 81ac <sp_16_done> */
1373 static const u32 word_8_code[] = {
1374 /* 000081b0 <sp_16_code_end>: */
1375 0xe4d05001, /* ldrb r5, [r0], #1 */
1376 0xe5c89000, /* strb r9, [r8] */
1377 0xe5cab000, /* strb r11, [r10] */
1378 0xe5c83000, /* strb r3, [r8] */
1379 0xe5c15000, /* strb r5, [r1] */
1380 0xe1a00000, /* nop (mov r0,r0) */
1382 /* 000081c0 <sp_8_busy>: */
1383 0xe5d16000, /* ldrb r6, [r1] */
1384 0xe0257006, /* eor r7, r5, r6 */
1385 0xe0147007, /* ands r7, r4, r7 */
1386 0x0a000007, /* beq 81f0 <sp_8_cont> */
1387 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1388 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1389 0xe5d16000, /* ldrb r6, [r1] */
1390 0xe0257006, /* eor r7, r5, r6 */
1391 0xe0147007, /* ands r7, r4, r7 */
1392 0x0a000001, /* beq 81f0 <sp_8_cont> */
1393 0xe3a05000, /* mov r5, #0 ; 0x0 */
1394 0x1a000004, /* bne 8204 <sp_8_done> */
1396 /* 000081f0 <sp_8_cont>: */
1397 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1398 0x03a05080, /* moveq r5, #128 ; 0x80 */
1399 0x0a000001, /* beq 8204 <sp_8_done> */
1400 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1401 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1403 /* 00008204 <sp_8_done>: */
1404 0xeafffffe /* b 8204 <sp_8_done> */
1407 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1408 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1409 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1411 /* flash write code */
1412 if (!cfi_info->write_algorithm)
1415 int target_code_size;
1418 /* convert bus-width dependent algorithm code to correct endiannes */
1419 switch (bank->bus_width)
1423 target_code_size = sizeof(word_8_code);
1427 target_code_size = sizeof(word_16_code);
1431 target_code_size = sizeof(word_32_code);
1434 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1435 return ERROR_FLASH_OPERATION_FAILED;
1437 target_code = malloc(target_code_size);
1438 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1440 /* allocate working area */
1441 retval=target_alloc_working_area(target, target_code_size,
1442 &cfi_info->write_algorithm);
1443 if (retval != ERROR_OK)
1449 /* write algorithm code to working area */
1450 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1451 target_code_size, target_code)) != ERROR_OK)
1459 /* the following code still assumes target code is fixed 24*4 bytes */
1461 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1464 if (buffer_size <= 256)
1466 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1467 if (cfi_info->write_algorithm)
1468 target_free_working_area(target, cfi_info->write_algorithm);
1470 LOG_WARNING("not enough working area available, can't do block memory writes");
1471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1475 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1476 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1477 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1478 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1479 init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
1480 init_reg_param(®_params[5], "r5", 32, PARAM_IN);
1481 init_reg_param(®_params[6], "r8", 32, PARAM_OUT);
1482 init_reg_param(®_params[7], "r9", 32, PARAM_OUT);
1483 init_reg_param(®_params[8], "r10", 32, PARAM_OUT);
1484 init_reg_param(®_params[9], "r11", 32, PARAM_OUT);
1488 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1490 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1492 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1493 buf_set_u32(reg_params[1].value, 0, 32, address);
1494 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1495 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1496 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1497 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1498 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1499 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1500 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1502 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1503 cfi_info->write_algorithm->address,
1504 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1505 10000, &armv4_5_info);
1507 status = buf_get_u32(reg_params[5].value, 0, 32);
1509 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1511 LOG_DEBUG("status: 0x%x", status);
1512 exit_code = ERROR_FLASH_OPERATION_FAILED;
1516 buffer += thisrun_count;
1517 address += thisrun_count;
1518 count -= thisrun_count;
1521 target_free_working_area(target, source);
1523 destroy_reg_param(®_params[0]);
1524 destroy_reg_param(®_params[1]);
1525 destroy_reg_param(®_params[2]);
1526 destroy_reg_param(®_params[3]);
1527 destroy_reg_param(®_params[4]);
1528 destroy_reg_param(®_params[5]);
1529 destroy_reg_param(®_params[6]);
1530 destroy_reg_param(®_params[7]);
1531 destroy_reg_param(®_params[8]);
1532 destroy_reg_param(®_params[9]);
1537 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1540 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1541 target_t *target = bank->target;
1544 cfi_intel_clear_status_register(bank);
1545 cfi_command(bank, 0x40, command);
1546 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1551 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1556 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1558 cfi_command(bank, 0xff, command);
1559 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1564 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1565 return ERROR_FLASH_OPERATION_FAILED;
1571 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1574 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1575 target_t *target = bank->target;
1578 /* Calculate buffer size and boundary mask */
1579 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1580 u32 buffermask = buffersize-1;
1583 /* Check for valid range */
1584 if (address & buffermask)
1586 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1587 return ERROR_FLASH_OPERATION_FAILED;
1589 switch(bank->chip_width)
1591 case 4 : bufferwsize = buffersize / 4; break;
1592 case 2 : bufferwsize = buffersize / 2; break;
1593 case 1 : bufferwsize = buffersize; break;
1595 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1596 return ERROR_FLASH_OPERATION_FAILED;
1599 bufferwsize/=(bank->bus_width / bank->chip_width);
1602 /* Check for valid size */
1603 if (wordcount > bufferwsize)
1605 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1606 return ERROR_FLASH_OPERATION_FAILED;
1609 /* Write to flash buffer */
1610 cfi_intel_clear_status_register(bank);
1612 /* Initiate buffer operation _*/
1613 cfi_command(bank, 0xE8, command);
1614 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1618 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1620 cfi_command(bank, 0xff, command);
1621 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1626 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1627 return ERROR_FLASH_OPERATION_FAILED;
1630 /* Write buffer wordcount-1 and data words */
1631 cfi_command(bank, bufferwsize-1, command);
1632 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1637 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1642 /* Commit write operation */
1643 cfi_command(bank, 0xd0, command);
1644 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1648 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1650 cfi_command(bank, 0xff, command);
1651 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1656 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1657 return ERROR_FLASH_OPERATION_FAILED;
1663 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1666 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1667 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1668 target_t *target = bank->target;
1671 cfi_command(bank, 0xaa, command);
1672 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1677 cfi_command(bank, 0x55, command);
1678 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1683 cfi_command(bank, 0xa0, command);
1684 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1689 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1694 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1696 cfi_command(bank, 0xf0, command);
1697 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1702 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1703 return ERROR_FLASH_OPERATION_FAILED;
1709 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1712 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1713 target_t *target = bank->target;
1715 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1717 /* Calculate buffer size and boundary mask */
1718 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1719 u32 buffermask = buffersize-1;
1722 /* Check for valid range */
1723 if (address & buffermask)
1725 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1726 return ERROR_FLASH_OPERATION_FAILED;
1728 switch(bank->chip_width)
1730 case 4 : bufferwsize = buffersize / 4; break;
1731 case 2 : bufferwsize = buffersize / 2; break;
1732 case 1 : bufferwsize = buffersize; break;
1734 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1735 return ERROR_FLASH_OPERATION_FAILED;
1738 bufferwsize/=(bank->bus_width / bank->chip_width);
1740 /* Check for valid size */
1741 if (wordcount > bufferwsize)
1743 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1744 return ERROR_FLASH_OPERATION_FAILED;
1748 cfi_command(bank, 0xaa, command);
1749 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1754 cfi_command(bank, 0x55, command);
1755 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1760 // Buffer load command
1761 cfi_command(bank, 0x25, command);
1762 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1767 /* Write buffer wordcount-1 and data words */
1768 cfi_command(bank, bufferwsize-1, command);
1769 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1774 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1779 /* Commit write operation */
1780 cfi_command(bank, 0x29, command);
1781 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1786 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1788 cfi_command(bank, 0xf0, command);
1789 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1794 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1795 return ERROR_FLASH_OPERATION_FAILED;
1801 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1803 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1805 switch(cfi_info->pri_id)
1809 return cfi_intel_write_word(bank, word, address);
1812 return cfi_spansion_write_word(bank, word, address);
1815 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1819 return ERROR_FLASH_OPERATION_FAILED;
1822 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1824 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1826 switch(cfi_info->pri_id)
1830 return cfi_intel_write_words(bank, word, wordcount, address);
1833 return cfi_spansion_write_words(bank, word, wordcount, address);
1836 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1840 return ERROR_FLASH_OPERATION_FAILED;
1843 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1845 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1846 target_t *target = bank->target;
1847 u32 address = bank->base + offset; /* address of first byte to be programmed */
1848 u32 write_p, copy_p;
1849 int align; /* number of unaligned bytes */
1850 int blk_count; /* number of bus_width bytes for block copy */
1851 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1855 if (bank->target->state != TARGET_HALTED)
1857 LOG_ERROR("Target not halted");
1858 return ERROR_TARGET_NOT_HALTED;
1861 if (offset + count > bank->size)
1862 return ERROR_FLASH_DST_OUT_OF_BANK;
1864 if (cfi_info->qry[0] != 'Q')
1865 return ERROR_FLASH_BANK_NOT_PROBED;
1867 /* start at the first byte of the first word (bus_width size) */
1868 write_p = address & ~(bank->bus_width - 1);
1869 if ((align = address - write_p) != 0)
1871 LOG_INFO("Fixup %d unaligned head bytes", align );
1873 for (i = 0; i < bank->bus_width; i++)
1874 current_word[i] = 0;
1877 /* copy bytes before the first write address */
1878 for (i = 0; i < align; ++i, ++copy_p)
1881 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1885 cfi_add_byte(bank, current_word, byte);
1888 /* add bytes from the buffer */
1889 for (; (i < bank->bus_width) && (count > 0); i++)
1891 cfi_add_byte(bank, current_word, *buffer++);
1896 /* if the buffer is already finished, copy bytes after the last write address */
1897 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1900 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1904 cfi_add_byte(bank, current_word, byte);
1907 retval = cfi_write_word(bank, current_word, write_p);
1908 if (retval != ERROR_OK)
1913 /* handle blocks of bus_size aligned bytes */
1914 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1915 switch(cfi_info->pri_id)
1917 /* try block writes (fails without working area) */
1920 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1923 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1926 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1927 retval = ERROR_FLASH_OPERATION_FAILED;
1930 if (retval == ERROR_OK)
1932 /* Increment pointers and decrease count on succesful block write */
1933 buffer += blk_count;
1934 write_p += blk_count;
1939 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1941 //adjust buffersize for chip width
1942 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1943 u32 buffermask = buffersize-1;
1946 switch(bank->chip_width)
1948 case 4 : bufferwsize = buffersize / 4; break;
1949 case 2 : bufferwsize = buffersize / 2; break;
1950 case 1 : bufferwsize = buffersize; break;
1952 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1953 return ERROR_FLASH_OPERATION_FAILED;
1956 bufferwsize/=(bank->bus_width / bank->chip_width);
1958 /* fall back to memory writes */
1959 while (count >= (u32)bank->bus_width)
1962 if ((write_p & 0xff) == 0)
1964 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1967 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1969 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1970 if (retval == ERROR_OK)
1972 buffer += buffersize;
1973 write_p += buffersize;
1974 count -= buffersize;
1978 /* try the slow way? */
1981 for (i = 0; i < bank->bus_width; i++)
1982 current_word[i] = 0;
1984 for (i = 0; i < bank->bus_width; i++)
1986 cfi_add_byte(bank, current_word, *buffer++);
1989 retval = cfi_write_word(bank, current_word, write_p);
1990 if (retval != ERROR_OK)
1993 write_p += bank->bus_width;
1994 count -= bank->bus_width;
2002 /* return to read array mode, so we can read from flash again for padding */
2003 cfi_command(bank, 0xf0, current_word);
2004 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2008 cfi_command(bank, 0xff, current_word);
2009 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2014 /* handle unaligned tail bytes */
2017 LOG_INFO("Fixup %d unaligned tail bytes", count );
2020 for (i = 0; i < bank->bus_width; i++)
2021 current_word[i] = 0;
2023 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2025 cfi_add_byte(bank, current_word, *buffer++);
2028 for (; i < bank->bus_width; ++i, ++copy_p)
2031 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2035 cfi_add_byte(bank, current_word, byte);
2037 retval = cfi_write_word(bank, current_word, write_p);
2038 if (retval != ERROR_OK)
2042 /* return to read array mode */
2043 cfi_command(bank, 0xf0, current_word);
2044 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2048 cfi_command(bank, 0xff, current_word);
2049 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2052 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2055 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2056 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2058 pri_ext->_reversed_geometry = 1;
2061 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2064 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2065 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2068 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2070 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2072 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2074 int j = (cfi_info->num_erase_regions - 1) - i;
2077 swap = cfi_info->erase_region_info[i];
2078 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2079 cfi_info->erase_region_info[j] = swap;
2084 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2086 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2087 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2088 cfi_unlock_addresses_t *unlock_addresses = param;
2090 pri_ext->_unlock1 = unlock_addresses->unlock1;
2091 pri_ext->_unlock2 = unlock_addresses->unlock2;
2094 static int cfi_probe(struct flash_bank_s *bank)
2096 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2097 target_t *target = bank->target;
2099 int num_sectors = 0;
2102 u32 unlock1 = 0x555;
2103 u32 unlock2 = 0x2aa;
2106 if (bank->target->state != TARGET_HALTED)
2108 LOG_ERROR("Target not halted");
2109 return ERROR_TARGET_NOT_HALTED;
2112 cfi_info->probed = 0;
2114 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2115 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2117 if (cfi_info->jedec_probe)
2123 /* switch to read identifier codes mode ("AUTOSELECT") */
2124 cfi_command(bank, 0xaa, command);
2125 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2129 cfi_command(bank, 0x55, command);
2130 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2134 cfi_command(bank, 0x90, command);
2135 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2140 if (bank->chip_width == 1)
2142 u8 manufacturer, device_id;
2143 if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
2147 if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
2151 cfi_info->manufacturer = manufacturer;
2152 cfi_info->device_id = device_id;
2154 else if (bank->chip_width == 2)
2156 if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
2160 if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
2166 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2167 /* switch back to read array mode */
2168 cfi_command(bank, 0xf0, command);
2169 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2173 cfi_command(bank, 0xff, command);
2174 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2179 /* check device/manufacturer ID for known non-CFI flashes. */
2180 cfi_fixup_non_cfi(bank);
2182 /* query only if this is a CFI compatible flash,
2183 * otherwise the relevant info has already been filled in
2185 if (cfi_info->not_cfi == 0)
2187 /* enter CFI query mode
2188 * according to JEDEC Standard No. 68.01,
2189 * a single bus sequence with address = 0x55, data = 0x98 should put
2190 * the device into CFI query mode.
2192 * SST flashes clearly violate this, and we will consider them incompatbile for now
2194 cfi_command(bank, 0x98, command);
2195 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2200 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2201 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2202 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2204 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2206 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2208 cfi_command(bank, 0xf0, command);
2209 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2213 cfi_command(bank, 0xff, command);
2214 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2218 LOG_ERROR("Could not probe bank: no QRY");
2219 return ERROR_FLASH_BANK_INVALID;
2222 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2223 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2224 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2225 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2227 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2229 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2230 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2231 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2232 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2233 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2234 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2235 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2236 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2237 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2238 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2239 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2240 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2242 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2243 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2244 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2245 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2246 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2247 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2248 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2249 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2250 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2251 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2252 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2254 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2255 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2256 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2257 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2259 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2261 if (cfi_info->num_erase_regions)
2263 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2264 for (i = 0; i < cfi_info->num_erase_regions; i++)
2266 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2267 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2272 cfi_info->erase_region_info = NULL;
2275 /* We need to read the primary algorithm extended query table before calculating
2276 * the sector layout to be able to apply fixups
2278 switch(cfi_info->pri_id)
2280 /* Intel command set (standard and extended) */
2283 cfi_read_intel_pri_ext(bank);
2285 /* AMD/Spansion, Atmel, ... command set */
2287 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2288 cfi_read_0002_pri_ext(bank);
2291 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2295 /* return to read array mode
2296 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2298 cfi_command(bank, 0xf0, command);
2299 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2303 cfi_command(bank, 0xff, command);
2304 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2308 } /* end CFI case */
2310 /* apply fixups depending on the primary command set */
2311 switch(cfi_info->pri_id)
2313 /* Intel command set (standard and extended) */
2316 cfi_fixup(bank, cfi_0001_fixups);
2318 /* AMD/Spansion, Atmel, ... command set */
2320 cfi_fixup(bank, cfi_0002_fixups);
2323 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2327 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2329 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2332 if (cfi_info->num_erase_regions == 0)
2334 /* a device might have only one erase block, spanning the whole device */
2335 bank->num_sectors = 1;
2336 bank->sectors = malloc(sizeof(flash_sector_t));
2338 bank->sectors[sector].offset = 0x0;
2339 bank->sectors[sector].size = bank->size;
2340 bank->sectors[sector].is_erased = -1;
2341 bank->sectors[sector].is_protected = -1;
2347 for (i = 0; i < cfi_info->num_erase_regions; i++)
2349 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2352 bank->num_sectors = num_sectors;
2353 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2355 for (i = 0; i < cfi_info->num_erase_regions; i++)
2358 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2360 bank->sectors[sector].offset = offset;
2361 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2362 offset += bank->sectors[sector].size;
2363 bank->sectors[sector].is_erased = -1;
2364 bank->sectors[sector].is_protected = -1;
2368 if (offset != cfi_info->dev_size)
2370 LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2374 cfi_info->probed = 1;
2379 static int cfi_auto_probe(struct flash_bank_s *bank)
2381 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2382 if (cfi_info->probed)
2384 return cfi_probe(bank);
2388 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2391 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2392 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2393 target_t *target = bank->target;
2394 u8 command[CFI_MAX_BUS_WIDTH];
2397 /* check if block lock bits are supported on this device */
2398 if (!(pri_ext->blk_status_reg_mask & 0x1))
2399 return ERROR_FLASH_OPERATION_FAILED;
2401 cfi_command(bank, 0x90, command);
2402 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2407 for (i = 0; i < bank->num_sectors; i++)
2409 u8 block_status = cfi_get_u8(bank, i, 0x2);
2411 if (block_status & 1)
2412 bank->sectors[i].is_protected = 1;
2414 bank->sectors[i].is_protected = 0;
2417 cfi_command(bank, 0xff, command);
2418 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2421 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2424 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2425 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2426 target_t *target = bank->target;
2430 cfi_command(bank, 0xaa, command);
2431 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2436 cfi_command(bank, 0x55, command);
2437 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2442 cfi_command(bank, 0x90, command);
2443 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2448 for (i = 0; i < bank->num_sectors; i++)
2450 u8 block_status = cfi_get_u8(bank, i, 0x2);
2452 if (block_status & 1)
2453 bank->sectors[i].is_protected = 1;
2455 bank->sectors[i].is_protected = 0;
2458 cfi_command(bank, 0xf0, command);
2459 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2462 static int cfi_protect_check(struct flash_bank_s *bank)
2464 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2466 if (bank->target->state != TARGET_HALTED)
2468 LOG_ERROR("Target not halted");
2469 return ERROR_TARGET_NOT_HALTED;
2472 if (cfi_info->qry[0] != 'Q')
2473 return ERROR_FLASH_BANK_NOT_PROBED;
2475 switch(cfi_info->pri_id)
2479 return cfi_intel_protect_check(bank);
2482 return cfi_spansion_protect_check(bank);
2485 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2492 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2495 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2497 if (cfi_info->qry[0] == (char)-1)
2499 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2503 if (cfi_info->not_cfi == 0)
2504 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2506 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2508 buf_size -= printed;
2510 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2511 cfi_info->manufacturer, cfi_info->device_id);
2513 buf_size -= printed;
2515 if (cfi_info->not_cfi == 0)
2517 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2519 buf_size -= printed;
2521 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2522 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2523 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2524 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2525 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2527 buf_size -= printed;
2529 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2530 1 << cfi_info->word_write_timeout_typ,
2531 1 << cfi_info->buf_write_timeout_typ,
2532 1 << cfi_info->block_erase_timeout_typ,
2533 1 << cfi_info->chip_erase_timeout_typ);
2535 buf_size -= printed;
2537 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2538 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2539 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2540 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2541 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2543 buf_size -= printed;
2545 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2547 cfi_info->interface_desc,
2548 1 << cfi_info->max_buf_write_size);
2550 buf_size -= printed;
2552 switch(cfi_info->pri_id)
2556 cfi_intel_info(bank, buf, buf_size);
2559 cfi_spansion_info(bank, buf, buf_size);
2562 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);