git.sur5r.net Git - openocd/blob - src/flash/davinci_nand.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by David Brownell                                  *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /*
  21  * DaVinci family NAND controller support for OpenOCD.
  22  *
  23  * This driver uses hardware ECC (1-bit or 4-bit) unless
  24  * the chip is accessed in "raw" mode.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "nand.h"
  32
  33
  34 enum ecc {
  35         HWECC1,         /* all controllers support 1-bit ECC */
  36         HWECC4,         /* newer chips also have 4-bit ECC hardware */
  37         HWECC4_INFIX,   /* avoid this layout, except maybe for boot code */
  38 };
  39
  40 struct davinci_nand {
  41         target_t        *target;
  42
  43         u8              chipsel;        /* chipselect 0..3 == CS2..CS5 */
  44         u8              eccmode;
  45
  46         /* Async EMIF controller base */
  47         u32             aemif;
  48
  49         /* NAND chip addresses */
  50         u32             data;           /* without CLE or ALE */
  51         u32             cmd;            /* with CLE */
  52         u32             addr;           /* with ALE */
  53
  54         /* page i/o for the relevant flavor of hardware ECC */
  55         int (*read_page)(struct nand_device_s *nand, u32 page,
  56                         u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  57         int (*write_page)(struct nand_device_s *nand, u32 page,
  58                         u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  59 };
  60
  61 #define NANDFCR         0x60            /* flash control register */
  62 #define NANDFSR         0x64            /* flash status register */
  63 #define NANDFECC        0x70            /* 1-bit ECC data, CS0, 1st of 4 */
  64 #define NAND4BITECCLOAD 0xbc            /* 4-bit ECC, load saved values */
  65 #define NAND4BITECC     0xc0            /* 4-bit ECC data, 1st of 4 */
  66 #define NANDERRADDR     0xd0            /* 4-bit ECC err addr, 1st of 2 */
  67 #define NANDERRVAL      0xd8            /* 4-bit ECC err value, 1st of 2 */
  68
  69 static int halted(target_t *target, const char *label)
  70 {
  71         if (target->state == TARGET_HALTED)
  72                 return true;
  73
  74         LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
  75         return false;
  76 }
  77
  78 static int davinci_register_commands(struct command_context_s *cmd_ctx)
  79 {
  80         return ERROR_OK;
  81 }
  82
  83 static int davinci_init(struct nand_device_s *nand)
  84 {
  85         struct davinci_nand *info = nand->controller_priv;
  86         target_t *target = info->target;
  87         u32 nandfcr;
  88
  89         if (!halted(target, "init"))
  90                 return ERROR_NAND_OPERATION_FAILED;
  91
  92         /* We require something else to have configured AEMIF to talk
  93          * to NAND chip in this range (including timings and width).
  94          */
  95         target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
  96         if (!(nandfcr & (1 << info->chipsel))) {
  97                 LOG_ERROR("chip address %08x not NAND-enabled?", info->data);
  98                 return ERROR_NAND_OPERATION_FAILED;
  99         }
 100
 101         /* REVISIT verify:  AxCR must be in 8-bit mode, since that's all we
 102          * tested.  16 bit support should work too; but not with 4-bit ECC.
 103          */
 104
 105         return ERROR_OK;
 106 }
 107
 108 static int davinci_reset(struct nand_device_s *nand)
 109 {
 110         return ERROR_OK;
 111 }
 112
 113 static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
 114 {
 115         struct davinci_nand *info = nand->controller_priv;
 116         target_t *target = info->target;
 117         u32 nandfsr;
 118
 119         /* NOTE: return code is zero/error, else success; not ERROR_* */
 120
 121         if (!halted(target, "ready"))
 122                 return 0;
 123
 124         do {
 125                 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
 126
 127                 if (nandfsr & 0x01)
 128                         return 1;
 129
 130                 alive_sleep(1);
 131         } while (timeout-- > 0);
 132
 133         return 0;
 134 }
 135
 136 static int davinci_command(struct nand_device_s *nand, u8 command)
 137 {
 138         struct davinci_nand *info = nand->controller_priv;
 139         target_t *target = info->target;
 140
 141         if (!halted(target, "command"))
 142                 return ERROR_NAND_OPERATION_FAILED;
 143
 144         target_write_u8(target, info->cmd, command);
 145         return ERROR_OK;
 146 }
 147
 148 static int davinci_address(struct nand_device_s *nand, u8 address)
 149 {
 150         struct davinci_nand *info = nand->controller_priv;
 151         target_t *target = info->target;
 152
 153         if (!halted(target, "address"))
 154                 return ERROR_NAND_OPERATION_FAILED;
 155
 156         target_write_u8(target, info->addr, address);
 157         return ERROR_OK;
 158 }
 159
 160 static int davinci_write_data(struct nand_device_s *nand, u16 data)
 161 {
 162         struct davinci_nand *info = nand->controller_priv;
 163         target_t *target = info->target;
 164
 165         if (!halted(target, "write_data"))
 166                 return ERROR_NAND_OPERATION_FAILED;
 167
 168         target_write_u8(target, info->data, data);
 169         return ERROR_OK;
 170 }
 171
 172 static int davinci_read_data(struct nand_device_s *nand, void *data)
 173 {
 174         struct davinci_nand *info = nand->controller_priv;
 175         target_t *target = info->target;
 176
 177         if (!halted(target, "read_data"))
 178                 return ERROR_NAND_OPERATION_FAILED;
 179
 180         target_read_u8(target, info->data, data);
 181         return ERROR_OK;
 182 }
 183
 184 /* REVISIT a bit of native code should let block I/O be MUCH faster */
 185
 186 static int davinci_read_block_data(struct nand_device_s *nand,
 187                 u8 *data, int data_size)
 188 {
 189         struct davinci_nand *info = nand->controller_priv;
 190         target_t *target = info->target;
 191         u32 nfdata = info->data;
 192         u32 tmp;
 193
 194         if (!halted(target, "read_block"))
 195                 return ERROR_NAND_OPERATION_FAILED;
 196
 197         while (data_size >= 4) {
 198                 target_read_u32(target, nfdata, &tmp);
 199
 200                 data[0] = tmp;
 201                 data[1] = tmp >> 8;
 202                 data[2] = tmp >> 16;
 203                 data[3] = tmp >> 24;
 204
 205                 data_size -= 4;
 206                 data += 4;
 207         }
 208
 209         while (data_size > 0) {
 210                 target_read_u8(target, nfdata, data);
 211
 212                 data_size -= 1;
 213                 data += 1;
 214         }
 215
 216         return ERROR_OK;
 217 }
 218
 219 static int davinci_write_block_data(struct nand_device_s *nand,
 220                 u8 *data, int data_size)
 221 {
 222         struct davinci_nand *info = nand->controller_priv;
 223         target_t *target = info->target;
 224         u32 nfdata = info->data;
 225         u32 tmp;
 226
 227         if (!halted(target, "write_block"))
 228                 return ERROR_NAND_OPERATION_FAILED;
 229
 230         while (data_size >= 4) {
 231                 tmp = le_to_h_u32(data);
 232                 target_write_u32(target, nfdata, tmp);
 233
 234                 data_size -= 4;
 235                 data += 4;
 236         }
 237
 238         while (data_size > 0) {
 239                 target_write_u8(target, nfdata, *data);
 240
 241                 data_size -= 1;
 242                 data += 1;
 243         }
 244
 245         return ERROR_OK;
 246 }
 247
 248 static int davinci_write_page(struct nand_device_s *nand, u32 page,
 249                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 250 {
 251         struct davinci_nand *info = nand->controller_priv;
 252         u8 *ooballoc = NULL;
 253         int status;
 254
 255         if (!nand->device)
 256                 return ERROR_NAND_DEVICE_NOT_PROBED;
 257         if (!halted(info->target, "write_page"))
 258                 return ERROR_NAND_OPERATION_FAILED;
 259
 260         /* Always write both data and OOB ... we are not "raw" I/O! */
 261         if (!data) {
 262                 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n");
 263                 return ERROR_NAND_OPERATION_FAILED;
 264         }
 265
 266         /* If we're not given OOB, write 0xff where we don't write ECC codes. */
 267         switch (nand->page_size) {
 268         case 512:
 269                 oob_size = 16;
 270                 break;
 271         case 2048:
 272                 oob_size = 64;
 273                 break;
 274         case 4096:
 275                 oob_size = 128;
 276                 break;
 277         default:
 278                 return ERROR_NAND_OPERATION_FAILED;
 279         }
 280         if (!oob) {
 281                 ooballoc = malloc(oob_size);
 282                 if (!ooballoc)
 283                         return ERROR_NAND_OPERATION_FAILED;
 284                 oob = ooballoc;
 285                 memset(oob, 0x0ff, oob_size);
 286         }
 287
 288         status = info->write_page(nand, page, data, data_size, oob, oob_size);
 289         free(ooballoc);
 290         return status;
 291 }
 292
 293 static int davinci_read_page(struct nand_device_s *nand, u32 page,
 294                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 295 {
 296         struct davinci_nand *info = nand->controller_priv;
 297
 298         if (!nand->device)
 299                 return ERROR_NAND_DEVICE_NOT_PROBED;
 300         if (!halted(info->target, "read_page"))
 301                 return ERROR_NAND_OPERATION_FAILED;
 302
 303         return info->read_page(nand, page, data, data_size, oob, oob_size);
 304 }
 305
 306 static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page)
 307 {
 308         struct davinci_nand *info = nand->controller_priv;
 309         target_t *target = info->target;
 310         int page3 = nand->address_cycles - (nand->page_size == 512);
 311
 312         /* write command ({page,otp}x{read,program} */
 313         target_write_u8(target, info->cmd, cmd);
 314
 315         /* column address (beginning-of-page) */
 316         target_write_u8(target, info->addr, 0);
 317         if (nand->page_size > 512)
 318                 target_write_u8(target, info->addr, 0);
 319
 320         /* page address */
 321         target_write_u8(target, info->addr, page);
 322         target_write_u8(target, info->addr, page >> 8);
 323         if (page3)
 324                 target_write_u8(target, info->addr, page >> 16);
 325         if (page3 == 2)
 326                 target_write_u8(target, info->addr, page >> 24);
 327 }
 328
 329 static int davinci_writepage_tail(struct nand_device_s *nand,
 330                 u8 *oob, u32 oob_size)
 331 {
 332         struct davinci_nand *info = nand->controller_priv;
 333         target_t *target = info->target;
 334         u8 status;
 335
 336         if (oob_size)
 337                 davinci_write_block_data(nand, oob, oob_size);
 338
 339         /* non-cachemode page program */
 340         target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
 341
 342         if (!davinci_nand_ready(nand, 100))
 343                 return ERROR_NAND_OPERATION_TIMEOUT;
 344
 345         if (nand_read_status(nand, &status) != ERROR_OK) {
 346                 LOG_ERROR("couldn't read status");
 347                 return ERROR_NAND_OPERATION_FAILED;
 348         }
 349
 350         if (status & NAND_STATUS_FAIL) {
 351                 LOG_ERROR("write operation failed, status: 0x%02x", status);
 352                 return ERROR_NAND_OPERATION_FAILED;
 353         }
 354
 355         return ERROR_OK;
 356 }
 357
 358 /*
 359  * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
 360  */
 361 static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page,
 362                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 363 {
 364         unsigned oob_offset;
 365         struct davinci_nand *info = nand->controller_priv;
 366         target_t *target = info->target;
 367         const u32 fcr_addr = info->aemif + NANDFCR;
 368         const u32 ecc1_addr = info->aemif + NANDFECC + info->chipsel;
 369         u32 fcr, ecc1;
 370
 371         /* Write contiguous ECC bytes starting at specified offset.
 372          * NOTE: Linux reserves twice as many bytes as we need; and
 373          * for 16-bit OOB, those extra bytes are discontiguous.
 374          */
 375         switch (nand->page_size) {
 376         case 512:
 377                 oob_offset = 0;
 378                 break;
 379         case 2048:
 380                 oob_offset = 40;
 381                 break;
 382         default:
 383                 oob_offset = 80;
 384                 break;
 385         }
 386
 387         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 388
 389         /* scrub any old ECC state */
 390         target_read_u32(target, ecc1_addr, &ecc1);
 391
 392         target_read_u32(target, fcr_addr, &fcr);
 393         fcr |= 1 << (8 + info->chipsel);
 394
 395         do {
 396                 /* set "start csX 1bit ecc" bit */
 397                 target_write_u32(target, fcr_addr, fcr);
 398
 399                 /* write 512 bytes */
 400                 davinci_write_block_data(nand, data, 512);
 401                 data += 512;
 402                 data_size -= 512;
 403
 404                 /* read the ecc, pack to 3 bytes, and invert so the ecc
 405                  * in an erased block is correct
 406                  */
 407                 target_read_u32(target, ecc1_addr, &ecc1);
 408                 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
 409                 ecc1 = ~ecc1;
 410
 411                 /* save correct ECC code into oob data */
 412                 oob[oob_offset++] = (u8)(ecc1);
 413                 oob[oob_offset++] = (u8)(ecc1 >> 8);
 414                 oob[oob_offset++] = (u8)(ecc1 >> 16);
 415
 416         } while (data_size);
 417
 418         /* write OOB into spare area */
 419         return davinci_writepage_tail(nand, oob, oob_size);
 420 }
 421
 422 /*
 423  * Preferred "new style" ECC layout for use with 4-bit ECC.  This somewhat
 424  * slows down large page reads done with error correction (since the OOB
 425  * is read first, so its ECC data can be used incrementally), but the
 426  * manufacturer bad block markers are safe.  Contrast:  old "infix" style.
 427  */
 428 static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page,
 429                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 430 {
 431         static const u8 ecc512[] = {
 432                 0, 1, 2, 3, 4, /* 5== mfr badblock */
 433                 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
 434         };
 435         static const u8 ecc2048[] = {
 436                 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 437                 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 438                 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
 439                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 440         };
 441         static const u8 ecc4096[] = {
 442                  48,  49,  50,  51,  52,  53,  54,  55,  56,  57,
 443                  58,  59,  60,  61,  62,  63,  64,  65,  66,  67,
 444                  68,  69,  70,  71,  72,  73,  74,  75,  76,  77,
 445                  78,  79,  80,  81,  82,  83,  84,  85,  86,  87,
 446                  88,  89,  90,  91,  92,  93,  94,  95,  96,  97,
 447                  98,  99, 100, 101, 102, 103, 104, 105, 106, 107,
 448                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
 449                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
 450         };
 451
 452         struct davinci_nand *info = nand->controller_priv;
 453         const u8 *l;
 454         target_t *target = info->target;
 455         const u32 fcr_addr = info->aemif + NANDFCR;
 456         const u32 ecc4_addr = info->aemif + NAND4BITECC;
 457         u32 fcr, ecc4;
 458
 459         /* Use the same ECC layout Linux uses.  For small page chips
 460          * it's a bit cramped.
 461          *
 462          * NOTE:  at this writing, 4KB pages have issues in Linux
 463          * because they need more than 64 bytes of ECC data, which
 464          * the standard ECC logic can't handle.
 465          */
 466         switch (nand->page_size) {
 467         case 512:
 468                 l = ecc512;
 469                 break;
 470         case 2048:
 471                 l = ecc2048;
 472                 break;
 473         default:
 474                 l = ecc4096;
 475                 break;
 476         }
 477
 478         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 479
 480         /* scrub any old ECC state */
 481         target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
 482
 483         target_read_u32(target, fcr_addr, &fcr);
 484         fcr &= ~(0x03 << 4);
 485         fcr |= (1 << 12) | (info->chipsel << 4);
 486
 487         do {
 488                 u32 raw_ecc[4], *p;
 489                 int i;
 490
 491                 /* start 4bit ecc on csX */
 492                 target_write_u32(target, fcr_addr, fcr);
 493
 494                 /* write 512 bytes */
 495                 davinci_write_block_data(nand, data, 512);
 496                 data += 512;
 497                 data_size -= 512;
 498
 499                 /* read the ecc, then save it into 10 bytes in the oob */
 500                 for (i = 0; i < 4; i++) {
 501                         target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
 502                         raw_ecc[i] &= 0x03ff03ff;
 503                 }
 504                 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
 505                         oob[*l++] =   p[0]        & 0xff;
 506                         oob[*l++] = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 507                         oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 508                         oob[*l++] = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 509                         oob[*l++] =  (p[1] >> 18) & 0xff;
 510                 }
 511
 512         } while (data_size);
 513
 514         /* write OOB into spare area */
 515         return davinci_writepage_tail(nand, oob, oob_size);
 516 }
 517
 518 /*
 519  * "Infix" OOB ... like Linux ECC_HW_SYNDROME.  Avoided because it trashes
 520  * manufacturer bad block markers, except on small page chips.  Once you
 521  * write to a page using this scheme, you need specialized code to update
 522  * it (code which ignores now-invalid bad block markers).
 523  *
 524  * This is needed *only* to support older firmware.  Older ROM Boot Loaders
 525  * need it to read their second stage loader (UBL) into SRAM, but from then
 526  * on the whole system can use the cleaner non-infix layouts.  Systems with
 527  * older second stage loaders (ABL/U-Boot, etc) or other system software
 528  * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
 529  */
 530 static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page,
 531                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 532 {
 533         struct davinci_nand *info = nand->controller_priv;
 534         target_t *target = info->target;
 535         const u32 fcr_addr = info->aemif + NANDFCR;
 536         const u32 ecc4_addr = info->aemif + NAND4BITECC;
 537         u32 fcr, ecc4;
 538
 539         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 540
 541         /* scrub any old ECC state */
 542         target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
 543
 544         target_read_u32(target, fcr_addr, &fcr);
 545         fcr &= ~(0x03 << 4);
 546         fcr |= (1 << 12) | (info->chipsel << 4);
 547
 548         do {
 549                 u32 raw_ecc[4], *p;
 550                 u8 *l;
 551                 int i;
 552
 553                 /* start 4bit ecc on csX */
 554                 target_write_u32(target, fcr_addr, fcr);
 555
 556                 /* write 512 bytes */
 557                 davinci_write_block_data(nand, data, 512);
 558                 data += 512;
 559                 data_size -= 512;
 560
 561                 /* read the ecc */
 562                 for (i = 0; i < 4; i++) {
 563                         target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
 564                         raw_ecc[i] &= 0x03ff03ff;
 565                 }
 566
 567                 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
 568                 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
 569                         *l++ =   p[0]        & 0xff;
 570                         *l++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 571                         *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 572                         *l++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 573                         *l++ =  (p[1] >> 18) & 0xff;
 574                 }
 575
 576                 /* write this "out-of-band" data -- infix */
 577                 davinci_write_block_data(nand, oob, 16);
 578                 oob += 16;
 579                 oob_size -= 16;
 580
 581         } while (data_size);
 582
 583         /* the last data and OOB writes included the spare area */
 584         return davinci_writepage_tail(nand, NULL, 0);
 585 }
 586
 587 static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page,
 588                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 589 {
 590         davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
 591
 592         /* large page devices need a start command */
 593         if (nand->page_size > 512)
 594                 davinci_command(nand, NAND_CMD_READSTART);
 595
 596         if (!davinci_nand_ready(nand, 100))
 597                 return ERROR_NAND_OPERATION_TIMEOUT;
 598
 599         /* NOTE:  not bothering to compute and use ECC data for now */
 600
 601         do {
 602                 /* write 512 bytes */
 603                 davinci_read_block_data(nand, data, 512);
 604                 data += 512;
 605                 data_size -= 512;
 606
 607                 /* read this "out-of-band" data -- infix */
 608                 davinci_read_block_data(nand, oob, 16);
 609                 oob += 16;
 610                 oob_size -= 16;
 611         } while (data_size);
 612
 613         return ERROR_OK;
 614 }
 615
 616 static int davinci_nand_device_command(struct command_context_s *cmd_ctx,
 617                 char *cmd, char **argv, int argc,
 618                 struct nand_device_s *nand)
 619 {
 620         struct davinci_nand *info;
 621         target_t *target;
 622         unsigned long chip, aemif;
 623         enum ecc eccmode;
 624         int chipsel;
 625         char *ep;
 626
 627         /* arguments:
 628          *  - "davinci"
 629          *  - target
 630          *  - nand chip address
 631          *  - ecc mode
 632          *  - aemif address
 633          * Plus someday, optionally, ALE and CLE masks.
 634          */
 635         if (argc < 5) {
 636                 LOG_ERROR("parameters: %s target "
 637                                 "chip_addr hwecc_mode aemif_addr",
 638                                 argv[0]);
 639                 goto fail;
 640         }
 641
 642         target = get_target(argv[1]);
 643         if (!target) {
 644                 LOG_ERROR("invalid target %s", argv[1]);
 645                 goto fail;
 646         }
 647
 648         chip = strtoul(argv[2], &ep, 0);
 649         if (*ep || chip == 0 || chip == ULONG_MAX) {
 650                 LOG_ERROR("Invalid NAND chip address %s", argv[2]);
 651                 goto fail;
 652         }
 653
 654         if (strcmp(argv[3], "hwecc1") == 0)
 655                 eccmode = HWECC1;
 656         else if (strcmp(argv[3], "hwecc4") == 0)
 657                 eccmode = HWECC4;
 658         else if (strcmp(argv[3], "hwecc4_infix") == 0)
 659                 eccmode = HWECC4_INFIX;
 660         else {
 661                 LOG_ERROR("Invalid ecc mode %s", argv[3]);
 662                 goto fail;
 663         }
 664
 665         aemif = strtoul(argv[4], &ep, 0);
 666         if (*ep || chip == 0 || chip == ULONG_MAX) {
 667                 LOG_ERROR("Invalid AEMIF controller address %s", argv[4]);
 668                 goto fail;
 669         }
 670
 671         /* REVISIT what we'd *like* to do is look up valid ranges using
 672          * target-specific declarations, and not even need to pass the
 673          * AEMIF controller address.
 674          */
 675         if (aemif == 0x01e00000                 /* dm6446, dm357 */
 676                         || aemif == 0x01e10000  /* dm335, dm355 */
 677                         || aemif == 0x01d10000  /* dm365 */
 678                         ) {
 679                 if (chip < 0x0200000 || chip >= 0x0a000000) {
 680                         LOG_ERROR("NAND address %08lx out of range?", chip);
 681                         goto fail;
 682                 }
 683                 chipsel = (chip - 0x02000000) >> 21;
 684         } else {
 685                 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
 686                 goto fail;
 687         }
 688
 689         info = calloc(1, sizeof *info);
 690         if (info == NULL)
 691                 goto fail;
 692
 693         info->target = target;
 694         info->eccmode = eccmode;
 695         info->chipsel = chipsel;
 696         info->aemif = aemif;
 697         info->data = chip;
 698         info->cmd = chip | 0x10;
 699         info->addr = chip | 0x08;
 700
 701         nand->controller_priv = info;
 702
 703         /* NOTE:  for now we don't do any error correction on read.
 704          * Nothing else in OpenOCD currently corrects read errors,
 705          * and in any case it's *writing* that we care most about.
 706          */
 707         info->read_page = nand_read_page_raw;
 708
 709         switch (eccmode) {
 710         case HWECC1:
 711                 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
 712                 info->write_page = davinci_write_page_ecc1;
 713                 break;
 714         case HWECC4:
 715                 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
 716                 info->write_page = davinci_write_page_ecc4;
 717                 break;
 718         case HWECC4_INFIX:
 719                 /* Same 4-bit ECC HW, with problematic page/ecc layout */
 720                 info->read_page = davinci_read_page_ecc4infix;
 721                 info->write_page = davinci_write_page_ecc4infix;
 722                 break;
 723         }
 724
 725         return ERROR_OK;
 726
 727 fail:
 728         return ERROR_NAND_OPERATION_FAILED;
 729 }
 730
 731 nand_flash_controller_t davinci_nand_controller = {
 732         .name                   = "davinci",
 733         .nand_device_command    = davinci_nand_device_command,
 734         .register_commands      = davinci_register_commands,
 735         .init                   = davinci_init,
 736         .reset                  = davinci_reset,
 737         .command                = davinci_command,
 738         .address                = davinci_address,
 739         .write_data             = davinci_write_data,
 740         .read_data              = davinci_read_data,
 741         .write_page             = davinci_write_page,
 742         .read_page              = davinci_read_page,
 743         .write_block_data       = davinci_write_block_data,
 744         .read_block_data        = davinci_read_block_data,
 745         .nand_ready             = davinci_nand_ready,
 746 };