1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
21 * DaVinci family NAND controller support for OpenOCD.
23 * This driver uses hardware ECC (1-bit or 4-bit) unless
24 * the chip is accessed in "raw" mode.
35 HWECC1, /* all controllers support 1-bit ECC */
36 HWECC4, /* newer chips also have 4-bit ECC hardware */
37 HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
43 u8 chipsel; /* chipselect 0..3 == CS2..CS5 */
46 /* Async EMIF controller base */
49 /* NAND chip addresses */
50 u32 data; /* without CLE or ALE */
51 u32 cmd; /* with CLE */
52 u32 addr; /* with ALE */
54 /* page i/o for the relevant flavor of hardware ECC */
55 int (*read_page)(struct nand_device_s *nand, u32 page,
56 u8 *data, u32 data_size, u8 *oob, u32 oob_size);
57 int (*write_page)(struct nand_device_s *nand, u32 page,
58 u8 *data, u32 data_size, u8 *oob, u32 oob_size);
61 #define NANDFCR 0x60 /* flash control register */
62 #define NANDFSR 0x64 /* flash status register */
63 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
64 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
65 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
66 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
67 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
69 static int halted(target_t *target, const char *label)
71 if (target->state == TARGET_HALTED)
74 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
78 static int davinci_register_commands(struct command_context_s *cmd_ctx)
83 static int davinci_init(struct nand_device_s *nand)
85 struct davinci_nand *info = nand->controller_priv;
86 target_t *target = info->target;
89 if (!halted(target, "init"))
90 return ERROR_NAND_OPERATION_FAILED;
92 /* We require something else to have configured AEMIF to talk
93 * to NAND chip in this range (including timings and width).
95 target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
96 if (!(nandfcr & (1 << info->chipsel))) {
97 LOG_ERROR("chip address %08x not NAND-enabled?", info->data);
98 return ERROR_NAND_OPERATION_FAILED;
101 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
102 * tested. 16 bit support should work too; but not with 4-bit ECC.
108 static int davinci_reset(struct nand_device_s *nand)
113 static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
115 struct davinci_nand *info = nand->controller_priv;
116 target_t *target = info->target;
119 /* NOTE: return code is zero/error, else success; not ERROR_* */
121 if (!halted(target, "ready"))
125 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
131 } while (timeout-- > 0);
136 static int davinci_command(struct nand_device_s *nand, u8 command)
138 struct davinci_nand *info = nand->controller_priv;
139 target_t *target = info->target;
141 if (!halted(target, "command"))
142 return ERROR_NAND_OPERATION_FAILED;
144 target_write_u8(target, info->cmd, command);
148 static int davinci_address(struct nand_device_s *nand, u8 address)
150 struct davinci_nand *info = nand->controller_priv;
151 target_t *target = info->target;
153 if (!halted(target, "address"))
154 return ERROR_NAND_OPERATION_FAILED;
156 target_write_u8(target, info->addr, address);
160 static int davinci_write_data(struct nand_device_s *nand, u16 data)
162 struct davinci_nand *info = nand->controller_priv;
163 target_t *target = info->target;
165 if (!halted(target, "write_data"))
166 return ERROR_NAND_OPERATION_FAILED;
168 target_write_u8(target, info->data, data);
172 static int davinci_read_data(struct nand_device_s *nand, void *data)
174 struct davinci_nand *info = nand->controller_priv;
175 target_t *target = info->target;
177 if (!halted(target, "read_data"))
178 return ERROR_NAND_OPERATION_FAILED;
180 target_read_u8(target, info->data, data);
184 /* REVISIT a bit of native code should let block I/O be MUCH faster */
186 static int davinci_read_block_data(struct nand_device_s *nand,
187 u8 *data, int data_size)
189 struct davinci_nand *info = nand->controller_priv;
190 target_t *target = info->target;
191 u32 nfdata = info->data;
194 if (!halted(target, "read_block"))
195 return ERROR_NAND_OPERATION_FAILED;
197 while (data_size >= 4) {
198 target_read_u32(target, nfdata, &tmp);
209 while (data_size > 0) {
210 target_read_u8(target, nfdata, data);
219 static int davinci_write_block_data(struct nand_device_s *nand,
220 u8 *data, int data_size)
222 struct davinci_nand *info = nand->controller_priv;
223 target_t *target = info->target;
224 u32 nfdata = info->data;
227 if (!halted(target, "write_block"))
228 return ERROR_NAND_OPERATION_FAILED;
230 while (data_size >= 4) {
231 tmp = le_to_h_u32(data);
232 target_write_u32(target, nfdata, tmp);
238 while (data_size > 0) {
239 target_write_u8(target, nfdata, *data);
248 static int davinci_write_page(struct nand_device_s *nand, u32 page,
249 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
251 struct davinci_nand *info = nand->controller_priv;
256 return ERROR_NAND_DEVICE_NOT_PROBED;
257 if (!halted(info->target, "write_page"))
258 return ERROR_NAND_OPERATION_FAILED;
260 /* Always write both data and OOB ... we are not "raw" I/O! */
262 return ERROR_NAND_OPERATION_FAILED;
264 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
265 switch (nand->page_size) {
276 return ERROR_NAND_OPERATION_FAILED;
279 ooballoc = malloc(oob_size);
281 return ERROR_NAND_OPERATION_FAILED;
283 memset(oob, 0x0ff, oob_size);
286 status = info->write_page(nand, page, data, data_size, oob, oob_size);
291 static int davinci_read_page(struct nand_device_s *nand, u32 page,
292 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
294 struct davinci_nand *info = nand->controller_priv;
297 return ERROR_NAND_DEVICE_NOT_PROBED;
298 if (!halted(info->target, "read_page"))
299 return ERROR_NAND_OPERATION_FAILED;
301 return info->read_page(nand, page, data, data_size, oob, oob_size);
304 static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page)
306 struct davinci_nand *info = nand->controller_priv;
307 target_t *target = info->target;
308 int page3 = nand->address_cycles - (nand->page_size == 512);
310 /* write command ({page,otp}x{read,program} */
311 target_write_u8(target, info->cmd, cmd);
313 /* column address (beginning-of-page) */
314 target_write_u8(target, info->addr, 0);
315 if (nand->page_size > 512)
316 target_write_u8(target, info->addr, 0);
319 target_write_u8(target, info->addr, page);
320 target_write_u8(target, info->addr, page >> 8);
322 target_write_u8(target, info->addr, page >> 16);
324 target_write_u8(target, info->addr, page >> 24);
327 static int davinci_writepage_tail(struct nand_device_s *nand,
328 u8 *oob, u32 oob_size)
330 struct davinci_nand *info = nand->controller_priv;
331 target_t *target = info->target;
335 davinci_write_block_data(nand, oob, oob_size);
337 /* non-cachemode page program */
338 target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
340 if (!davinci_nand_ready(nand, 100))
341 return ERROR_NAND_OPERATION_TIMEOUT;
343 if (nand_read_status(nand, &status) != ERROR_OK) {
344 LOG_ERROR("couldn't read status");
345 return ERROR_NAND_OPERATION_FAILED;
348 if (status & NAND_STATUS_FAIL) {
349 LOG_ERROR("write operation failed, status: 0x%02x", status);
350 return ERROR_NAND_OPERATION_FAILED;
357 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
359 static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page,
360 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
363 struct davinci_nand *info = nand->controller_priv;
364 target_t *target = info->target;
365 const u32 fcr_addr = info->aemif + NANDFCR;
366 const u32 ecc1_addr = info->aemif + NANDFECC + info->chipsel;
369 /* Write contiguous ECC bytes starting at specified offset.
370 * NOTE: Linux reserves twice as many bytes as we need; and
371 * for 16-bit OOB, those extra bytes are discontiguous.
373 switch (nand->page_size) {
385 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
387 /* scrub any old ECC state */
388 target_read_u32(target, ecc1_addr, &ecc1);
390 target_read_u32(target, fcr_addr, &fcr);
391 fcr |= 1 << (8 + info->chipsel);
394 /* set "start csX 1bit ecc" bit */
395 target_write_u32(target, fcr_addr, fcr);
397 /* write 512 bytes */
398 davinci_write_block_data(nand, data, 512);
402 /* read the ecc, pack to 3 bytes, and invert so the ecc
403 * in an erased block is correct
405 target_read_u32(target, ecc1_addr, &ecc1);
406 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
409 /* save correct ECC code into oob data */
410 oob[oob_offset++] = (u8)(ecc1);
411 oob[oob_offset++] = (u8)(ecc1 >> 8);
412 oob[oob_offset++] = (u8)(ecc1 >> 16);
416 /* write OOB into spare area */
417 return davinci_writepage_tail(nand, oob, oob_size);
421 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
422 * slows down large page reads done with error correction (since the OOB
423 * is read first, so its ECC data can be used incrementally), but the
424 * manufacturer bad block markers are safe. Contrast: old "infix" style.
426 static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page,
427 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
429 static const u8 ecc512[] = {
430 0, 1, 2, 3, 4, /* 5== mfr badblock */
431 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
433 static const u8 ecc2048[] = {
434 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
435 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
436 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
437 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
439 static const u8 ecc4096[] = {
440 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
441 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
442 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
443 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
444 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
445 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
446 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
447 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
450 struct davinci_nand *info = nand->controller_priv;
452 target_t *target = info->target;
453 const u32 fcr_addr = info->aemif + NANDFCR;
454 const u32 ecc4_addr = info->aemif + NAND4BITECC;
457 /* Use the same ECC layout Linux uses. For small page chips
458 * it's a bit cramped.
460 * NOTE: at this writing, 4KB pages have issues in Linux
461 * because they need more than 64 bytes of ECC data, which
462 * the standard ECC logic can't handle.
464 switch (nand->page_size) {
476 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
478 /* scrub any old ECC state */
479 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
481 target_read_u32(target, fcr_addr, &fcr);
483 fcr |= (1 << 12) | (info->chipsel << 4);
489 /* start 4bit ecc on csX */
490 target_write_u32(target, fcr_addr, fcr);
492 /* write 512 bytes */
493 davinci_write_block_data(nand, data, 512);
497 /* read the ecc, then save it into 10 bytes in the oob */
498 for (i = 0; i < 4; i++) {
499 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
500 raw_ecc[i] &= 0x03ff03ff;
502 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
503 oob[*l++] = p[0] & 0xff;
504 oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
505 oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
506 oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
507 oob[*l++] = (p[1] >> 18) & 0xff;
512 /* write OOB into spare area */
513 return davinci_writepage_tail(nand, oob, oob_size);
517 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
518 * manufacturer bad block markers, except on small page chips. Once you
519 * write to a page using this scheme, you need specialized code to update
520 * it (code which ignores now-invalid bad block markers).
522 * This is needed *only* to support older firmware. Older ROM Boot Loaders
523 * need it to read their second stage loader (UBL) into SRAM, but from then
524 * on the whole system can use the cleaner non-infix layouts. Systems with
525 * older second stage loaders (ABL/U-Boot, etc) or other system software
526 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
528 static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page,
529 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
531 struct davinci_nand *info = nand->controller_priv;
532 target_t *target = info->target;
533 const u32 fcr_addr = info->aemif + NANDFCR;
534 const u32 ecc4_addr = info->aemif + NAND4BITECC;
537 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
539 /* scrub any old ECC state */
540 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
542 target_read_u32(target, fcr_addr, &fcr);
544 fcr |= (1 << 12) | (info->chipsel << 4);
551 /* start 4bit ecc on csX */
552 target_write_u32(target, fcr_addr, fcr);
554 /* write 512 bytes */
555 davinci_write_block_data(nand, data, 512);
560 for (i = 0; i < 4; i++) {
561 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
562 raw_ecc[i] &= 0x03ff03ff;
565 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
566 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
568 *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
569 *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
570 *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
571 *l++ = (p[1] >> 18) & 0xff;
574 /* write this "out-of-band" data -- infix */
575 davinci_write_block_data(nand, oob, 16);
581 /* the last data and OOB writes included the spare area */
582 return davinci_writepage_tail(nand, NULL, 0);
585 static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page,
586 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
588 davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
590 /* large page devices need a start command */
591 if (nand->page_size > 512)
592 davinci_command(nand, NAND_CMD_READSTART);
594 if (!davinci_nand_ready(nand, 100))
595 return ERROR_NAND_OPERATION_TIMEOUT;
597 /* NOTE: not bothering to compute and use ECC data for now */
600 /* write 512 bytes */
601 davinci_read_block_data(nand, data, 512);
605 /* read this "out-of-band" data -- infix */
606 davinci_read_block_data(nand, oob, 16);
614 static int davinci_nand_device_command(struct command_context_s *cmd_ctx,
615 char *cmd, char **argv, int argc,
616 struct nand_device_s *nand)
618 struct davinci_nand *info;
620 unsigned long chip, aemif;
628 * - nand chip address
631 * Plus someday, optionally, ALE and CLE masks.
634 LOG_ERROR("parameters: %s target "
635 "chip_addr hwecc_mode aemif_addr",
640 target = get_target(argv[1]);
642 LOG_ERROR("invalid target %s", argv[1]);
646 chip = strtoul(argv[2], &ep, 0);
647 if (*ep || chip == 0 || chip == ULONG_MAX) {
648 LOG_ERROR("Invalid NAND chip address %s", argv[2]);
652 if (strcmp(argv[3], "hwecc1") == 0)
654 else if (strcmp(argv[3], "hwecc4") == 0)
656 else if (strcmp(argv[3], "hwecc4_infix") == 0)
657 eccmode = HWECC4_INFIX;
659 LOG_ERROR("Invalid ecc mode %s", argv[3]);
663 aemif = strtoul(argv[4], &ep, 0);
664 if (*ep || chip == 0 || chip == ULONG_MAX) {
665 LOG_ERROR("Invalid AEMIF controller address %s", argv[4]);
669 /* REVISIT what we'd *like* to do is look up valid ranges using
670 * target-specific declarations, and not even need to pass the
671 * AEMIF controller address.
673 if (aemif == 0x01e00000 /* dm6446, dm357 */
674 || aemif == 0x01e10000 /* dm335, dm355 */
675 || aemif == 0x01d10000 /* dm365 */
677 if (chip < 0x0200000 || chip >= 0x0a000000) {
678 LOG_ERROR("NAND address %08lx out of range?", chip);
681 chipsel = (chip - 0x02000000) >> 21;
683 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
687 info = calloc(1, sizeof *info);
691 info->target = target;
692 info->eccmode = eccmode;
693 info->chipsel = chipsel;
696 info->cmd = chip | 0x10;
697 info->addr = chip | 0x08;
699 nand->controller_priv = info;
701 /* NOTE: for now we don't do any error correction on read.
702 * Nothing else in OpenOCD currently corrects read errors,
703 * and in any case it's *writing* that we care most about.
705 info->read_page = nand_read_page_raw;
709 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
710 info->write_page = davinci_write_page_ecc1;
713 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
714 info->write_page = davinci_write_page_ecc4;
717 /* Same 4-bit ECC HW, with problematic page/ecc layout */
718 info->read_page = davinci_read_page_ecc4infix;
719 info->write_page = davinci_write_page_ecc4infix;
726 return ERROR_NAND_OPERATION_FAILED;
729 nand_flash_controller_t davinci_nand_controller = {
731 .nand_device_command = davinci_nand_device_command,
732 .register_commands = davinci_register_commands,
733 .init = davinci_init,
734 .reset = davinci_reset,
735 .command = davinci_command,
736 .address = davinci_address,
737 .write_data = davinci_write_data,
738 .read_data = davinci_read_data,
739 .write_page = davinci_write_page,
740 .read_page = davinci_read_page,
741 .write_block_data = davinci_write_block_data,
742 .read_block_data = davinci_read_block_data,
743 .nand_ready = davinci_nand_ready,