git.sur5r.net Git - openocd/blob - src/flash/lpc3180_nand_controller.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "lpc3180_nand_controller.h"
  25 #include "nand.h"
  26
  27 static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
  28 static int lpc3180_register_commands(struct command_context_s *cmd_ctx);
  29 static int lpc3180_init(struct nand_device_s *device);
  30 static int lpc3180_reset(struct nand_device_s *device);
  31 static int lpc3180_command(struct nand_device_s *device, u8 command);
  32 static int lpc3180_address(struct nand_device_s *device, u8 address);
  33 static int lpc3180_write_data(struct nand_device_s *device, u16 data);
  34 static int lpc3180_read_data(struct nand_device_s *device, void *data);
  35 static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  36 static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  37 static int lpc3180_controller_ready(struct nand_device_s *device, int timeout);
  38 static int lpc3180_nand_ready(struct nand_device_s *device, int timeout);
  39
  40 static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41
  42 nand_flash_controller_t lpc3180_nand_controller =
  43 {
  44         .name = "lpc3180",
  45         .nand_device_command = lpc3180_nand_device_command,
  46         .register_commands = lpc3180_register_commands,
  47         .init = lpc3180_init,
  48         .reset = lpc3180_reset,
  49         .command = lpc3180_command,
  50         .address = lpc3180_address,
  51         .write_data = lpc3180_write_data,
  52         .read_data = lpc3180_read_data,
  53         .write_page = lpc3180_write_page,
  54         .read_page = lpc3180_read_page,
  55         .controller_ready = lpc3180_controller_ready,
  56         .nand_ready = lpc3180_nand_ready,
  57 };
  58
  59 /* nand device lpc3180 <target#> <oscillator_frequency>
  60  */
  61 static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
  62 {
  63         lpc3180_nand_controller_t *lpc3180_info;
  64
  65         if (argc < 3)
  66         {
  67                 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
  68                 return ERROR_FLASH_BANK_INVALID;
  69         }
  70
  71         lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
  72         device->controller_priv = lpc3180_info;
  73
  74         lpc3180_info->target = get_target(args[1]);
  75         if (!lpc3180_info->target)
  76         {
  77                 LOG_ERROR("target '%s' not defined", args[1]);
  78                 return ERROR_NAND_DEVICE_INVALID;
  79         }
  80
  81         lpc3180_info->osc_freq = strtoul(args[2], NULL, 0);
  82         if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  83         {
  84                 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
  85         }
  86         lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  87         lpc3180_info->sw_write_protection = 0;
  88         lpc3180_info->sw_wp_lower_bound = 0x0;
  89         lpc3180_info->sw_wp_upper_bound = 0x0;
  90
  91         return ERROR_OK;
  92 }
  93
  94 static int lpc3180_register_commands(struct command_context_s *cmd_ctx)
  95 {
  96         command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
  97
  98         register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)");
  99
 100         return ERROR_OK;
 101 }
 102
 103 static int lpc3180_pll(int fclkin, u32 pll_ctrl)
 104 {
 105         int bypass = (pll_ctrl & 0x8000) >> 15;
 106         int direct = (pll_ctrl & 0x4000) >> 14;
 107         int feedback = (pll_ctrl & 0x2000) >> 13;
 108         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
 109         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
 110         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
 111         int lock = (pll_ctrl & 0x1);
 112
 113         if (!lock)
 114                 LOG_WARNING("PLL is not locked");
 115
 116         if (!bypass && direct)  /* direct mode */
 117                 return (m * fclkin) / n;
 118
 119         if (bypass && !direct)  /* bypass mode */
 120                 return fclkin / (2 * p);
 121
 122         if (bypass & direct)    /* direct bypass mode */
 123                 return fclkin;
 124
 125         if (feedback)                   /* integer mode */
 126                 return m * (fclkin / n);
 127         else                                    /* non-integer mode */
 128                 return (m / (2 * p)) * (fclkin / n);
 129 }
 130
 131 static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
 132 {
 133         target_t *target = lpc3180_info->target;
 134         u32 sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 135         int sysclk;
 136         int hclk;
 137         int hclk_pll;
 138         float cycle;
 139
 140         /* calculate timings */
 141
 142         /* determine current SYSCLK (13'MHz or main oscillator) */
 143         target_read_u32(target, 0x40004050, &sysclk_ctrl);
 144
 145         if ((sysclk_ctrl & 1) == 0)
 146                 sysclk = lpc3180_info->osc_freq;
 147         else
 148                 sysclk = 13000;
 149
 150         /* determine selected HCLK source */
 151         target_read_u32(target, 0x40004044, &pwr_ctrl);
 152
 153         if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
 154         {
 155                 hclk = sysclk;
 156         }
 157         else
 158         {
 159                 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 160                 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
 161
 162                 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 163
 164                 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
 165                 {
 166                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 167                 }
 168                 else /* HCLK uses HCLK_PLL */
 169                 {
 170                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 171                 }
 172         }
 173
 174         LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
 175
 176         cycle = (1.0 / hclk) * 1000000.0;
 177
 178         return cycle;
 179 }
 180
 181 static int lpc3180_init(struct nand_device_s *device)
 182 {
 183         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 184         target_t *target = lpc3180_info->target;
 185         int bus_width = (device->bus_width) ? (device->bus_width) : 8;
 186         int address_cycles = (device->address_cycles) ? (device->address_cycles) : 3;
 187         int page_size = (device->page_size) ? (device->page_size) : 512;
 188
 189         if (target->state != TARGET_HALTED)
 190         {
 191                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 192                 return ERROR_NAND_OPERATION_FAILED;
 193         }
 194
 195         /* sanitize arguments */
 196         if ((bus_width != 8) && (bus_width != 16))
 197         {
 198                 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
 199                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 200         }
 201
 202         /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
 203          * would support 16 bit, too, so we just warn about this for now
 204          */
 205         if (bus_width == 16)
 206         {
 207                 LOG_WARNING("LPC3180 only supports 8 bit bus width");
 208         }
 209
 210         /* inform calling code about selected bus width */
 211         device->bus_width = bus_width;
 212
 213         if ((address_cycles != 3) && (address_cycles != 4))
 214         {
 215                 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
 216                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 217         }
 218
 219         if ((page_size != 512) && (page_size != 2048))
 220         {
 221                 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
 222                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 223         }
 224
 225         /* select MLC controller if none is currently selected */
 226         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 227         {
 228                 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
 229                 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 230         }
 231
 232         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 233         {
 234                 u32 mlc_icr_value = 0x0;
 235                 float cycle;
 236                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 237
 238                 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
 239                 target_write_u32(target, 0x400040c8, 0x22);
 240
 241                 /* MLC_CEH = 0x0 (Force nCE assert) */
 242                 target_write_u32(target, 0x200b804c, 0x0);
 243
 244                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 245                 target_write_u32(target, 0x200b8044, 0xa25e);
 246
 247                 /* MLC_ICR = configuration */
 248                 if (lpc3180_info->sw_write_protection)
 249                         mlc_icr_value |= 0x8;
 250                 if (page_size == 2048)
 251                         mlc_icr_value |= 0x4;
 252                 if (address_cycles == 4)
 253                         mlc_icr_value |= 0x2;
 254                 if (bus_width == 16)
 255                         mlc_icr_value |= 0x1;
 256                 target_write_u32(target, 0x200b8030, mlc_icr_value);
 257
 258                 /* calculate NAND controller timings */
 259                 cycle = lpc3180_cycle_time(lpc3180_info);
 260
 261                 twp = ((40 / cycle) + 1);
 262                 twh = ((20 / cycle) + 1);
 263                 trp = ((30 / cycle) + 1);
 264                 treh = ((15 / cycle) + 1);
 265                 trhz = ((30 / cycle) + 1);
 266                 trbwb = ((100 / cycle) + 1);
 267                 tcea = ((45 / cycle) + 1);
 268
 269                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 270                 target_write_u32(target, 0x200b8044, 0xa25e);
 271
 272                 /* MLC_TIME_REG */
 273                 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
 274                         ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
 275                         ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
 276
 277                 lpc3180_reset(device);
 278         }
 279         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 280         {
 281                 float cycle;
 282                 int r_setup, r_hold, r_width, r_rdy;
 283                 int w_setup, w_hold, w_width, w_rdy;
 284
 285                 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 286                 target_write_u32(target, 0x400040c8, 0x05);
 287
 288                 /* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
 289                 target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
 290
 291                 /* calculate NAND controller timings */
 292                 cycle = lpc3180_cycle_time(lpc3180_info);
 293
 294                 r_setup = w_setup = 0;
 295                 r_hold = w_hold = 10 / cycle;
 296                 r_width = 30 / cycle;
 297                 w_width = 40 / cycle;
 298                 r_rdy = w_rdy = 100 / cycle;
 299
 300                 /* SLC_TAC: SLC timing arcs register */
 301                 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
 302                         ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) |  ((w_setup & 0xf) << 16) |
 303                         ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
 304
 305                 lpc3180_reset(device);
 306         }
 307
 308         return ERROR_OK;
 309 }
 310
 311 static int lpc3180_reset(struct nand_device_s *device)
 312 {
 313         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 314         target_t *target = lpc3180_info->target;
 315
 316         if (target->state != TARGET_HALTED)
 317         {
 318                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 319                 return ERROR_NAND_OPERATION_FAILED;
 320         }
 321
 322         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 323         {
 324                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 325                 return ERROR_NAND_OPERATION_FAILED;
 326         }
 327         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 328         {
 329                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 330                 target_write_u32(target, 0x200b8000, 0xff);
 331
 332                 if (!lpc3180_controller_ready(device, 100))
 333                 {
 334                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 335                         return ERROR_NAND_OPERATION_TIMEOUT;
 336                 }
 337         }
 338         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 339         {
 340                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 341                 target_write_u32(target, 0x20020010, 0x6);
 342
 343                 if (!lpc3180_controller_ready(device, 100))
 344                 {
 345                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 346                         return ERROR_NAND_OPERATION_TIMEOUT;
 347                 }
 348         }
 349
 350         return ERROR_OK;
 351 }
 352
 353 static int lpc3180_command(struct nand_device_s *device, u8 command)
 354 {
 355         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 356         target_t *target = lpc3180_info->target;
 357
 358         if (target->state != TARGET_HALTED)
 359         {
 360                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 361                 return ERROR_NAND_OPERATION_FAILED;
 362         }
 363
 364         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 365         {
 366                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 367                 return ERROR_NAND_OPERATION_FAILED;
 368         }
 369         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 370         {
 371                 /* MLC_CMD = command */
 372                 target_write_u32(target, 0x200b8000, command);
 373         }
 374         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 375         {
 376                 /* SLC_CMD = command */
 377                 target_write_u32(target, 0x20020008, command);
 378         }
 379
 380         return ERROR_OK;
 381 }
 382
 383 static int lpc3180_address(struct nand_device_s *device, u8 address)
 384 {
 385         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 386         target_t *target = lpc3180_info->target;
 387
 388         if (target->state != TARGET_HALTED)
 389         {
 390                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 391                 return ERROR_NAND_OPERATION_FAILED;
 392         }
 393
 394         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 395         {
 396                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 397                 return ERROR_NAND_OPERATION_FAILED;
 398         }
 399         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 400         {
 401                 /* MLC_ADDR = address */
 402                 target_write_u32(target, 0x200b8004, address);
 403         }
 404         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 405         {
 406                 /* SLC_ADDR = address */
 407                 target_write_u32(target, 0x20020004, address);
 408         }
 409
 410         return ERROR_OK;
 411 }
 412
 413 static int lpc3180_write_data(struct nand_device_s *device, u16 data)
 414 {
 415         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 416         target_t *target = lpc3180_info->target;
 417
 418         if (target->state != TARGET_HALTED)
 419         {
 420                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 421                 return ERROR_NAND_OPERATION_FAILED;
 422         }
 423
 424         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 425         {
 426                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 427                 return ERROR_NAND_OPERATION_FAILED;
 428         }
 429         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 430         {
 431                 /* MLC_DATA = data */
 432                 target_write_u32(target, 0x200b0000, data);
 433         }
 434         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 435         {
 436                 /* SLC_DATA = data */
 437                 target_write_u32(target, 0x20020000, data);
 438         }
 439
 440         return ERROR_OK;
 441 }
 442
 443 static int lpc3180_read_data(struct nand_device_s *device, void *data)
 444 {
 445         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 446         target_t *target = lpc3180_info->target;
 447
 448         if (target->state != TARGET_HALTED)
 449         {
 450                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 451                 return ERROR_NAND_OPERATION_FAILED;
 452         }
 453
 454         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 455         {
 456                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 457                 return ERROR_NAND_OPERATION_FAILED;
 458         }
 459         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 460         {
 461                 /* data = MLC_DATA, use sized access */
 462                 if (device->bus_width == 8)
 463                 {
 464                         u8 *data8 = data;
 465                         target_read_u8(target, 0x200b0000, data8);
 466                 }
 467                 else if (device->bus_width == 16)
 468                 {
 469                         u16 *data16 = data;
 470                         target_read_u16(target, 0x200b0000, data16);
 471                 }
 472                 else
 473                 {
 474                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 475                         return ERROR_NAND_OPERATION_FAILED;
 476                 }
 477         }
 478         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 479         {
 480                 u32 data32;
 481
 482                 /* data = SLC_DATA, must use 32-bit access */
 483                 target_read_u32(target, 0x20020000, &data32);
 484
 485                 if (device->bus_width == 8)
 486                 {
 487                         u8 *data8 = data;
 488                         *data8 = data32 & 0xff;
 489                 }
 490                 else if (device->bus_width == 16)
 491                 {
 492                         u16 *data16 = data;
 493                         *data16 = data32 & 0xffff;
 494                 }
 495                 else
 496                 {
 497                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 498                         return ERROR_NAND_OPERATION_FAILED;
 499                 }
 500         }
 501
 502         return ERROR_OK;
 503 }
 504
 505 static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 506 {
 507         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 508         target_t *target = lpc3180_info->target;
 509         int retval;
 510         u8 status;
 511
 512         if (target->state != TARGET_HALTED)
 513         {
 514                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 515                 return ERROR_NAND_OPERATION_FAILED;
 516         }
 517
 518         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 519         {
 520                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 521                 return ERROR_NAND_OPERATION_FAILED;
 522         }
 523         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 524         {
 525                 u8 *page_buffer;
 526                 u8 *oob_buffer;
 527                 int quarter, num_quarters;
 528
 529                 if (!data && oob)
 530                 {
 531                         LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
 532                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 533                 }
 534
 535                 if (oob && (oob_size > 6))
 536                 {
 537                         LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
 538                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 539                 }
 540
 541                 if (data_size > (u32)device->page_size)
 542                 {
 543                         LOG_ERROR("data size exceeds page size");
 544                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 545                 }
 546
 547                 /* MLC_CMD = sequential input */
 548                 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 549
 550                 page_buffer = malloc(512);
 551                 oob_buffer = malloc(6);
 552
 553                 if (device->page_size == 512)
 554                 {
 555                         /* MLC_ADDR = 0x0 (one column cycle) */
 556                         target_write_u32(target, 0x200b8004, 0x0);
 557
 558                         /* MLC_ADDR = row */
 559                         target_write_u32(target, 0x200b8004, page & 0xff);
 560                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 561
 562                         if (device->address_cycles == 4)
 563                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 564                 }
 565                 else
 566                 {
 567                         /* MLC_ADDR = 0x0 (two column cycles) */
 568                         target_write_u32(target, 0x200b8004, 0x0);
 569                         target_write_u32(target, 0x200b8004, 0x0);
 570
 571                         /* MLC_ADDR = row */
 572                         target_write_u32(target, 0x200b8004, page & 0xff);
 573                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 574                 }
 575
 576                 /* when using the MLC controller, we have to treat a large page device
 577                  * as being made out of four quarters, each the size of a small page device
 578                  */
 579                 num_quarters = (device->page_size == 2048) ? 4 : 1;
 580
 581                 for (quarter = 0; quarter < num_quarters; quarter++)
 582                 {
 583                         int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 584                         int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 585
 586                         memset(page_buffer, 0xff, 512);
 587                         if (data)
 588                         {
 589                                 memcpy(page_buffer, data, thisrun_data_size);
 590                                 data_size -= thisrun_data_size;
 591                                 data += thisrun_data_size;
 592                         }
 593
 594                         memset(oob_buffer, 0xff, (device->page_size == 512) ? 6 : 24);
 595                         if (oob)
 596                         {
 597                                 memcpy(page_buffer, oob, thisrun_oob_size);
 598                                 oob_size -= thisrun_oob_size;
 599                                 oob += thisrun_oob_size;
 600                         }
 601
 602                         /* write MLC_ECC_ENC_REG to start encode cycle */
 603                         target_write_u32(target, 0x200b8008, 0x0);
 604
 605                         target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
 606                         target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
 607
 608                         /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 609                         target_write_u32(target, 0x200b8010, 0x0);
 610
 611                         if (!lpc3180_controller_ready(device, 1000))
 612                         {
 613                                 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
 614                                 return ERROR_NAND_OPERATION_FAILED;
 615                         }
 616                 }
 617
 618                 /* MLC_CMD = auto program command */
 619                 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 620
 621                 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
 622                 {
 623                         LOG_ERROR("couldn't read status");
 624                         return ERROR_NAND_OPERATION_FAILED;
 625                 }
 626
 627                 if (status & NAND_STATUS_FAIL)
 628                 {
 629                         LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
 630                         return ERROR_NAND_OPERATION_FAILED;
 631                 }
 632
 633                 free(page_buffer);
 634                 free(oob_buffer);
 635         }
 636         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 637         {
 638                 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
 639         }
 640
 641         return ERROR_OK;
 642 }
 643
 644 static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 645 {
 646         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 647         target_t *target = lpc3180_info->target;
 648
 649         if (target->state != TARGET_HALTED)
 650         {
 651                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 652                 return ERROR_NAND_OPERATION_FAILED;
 653         }
 654
 655         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 656         {
 657                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 658                 return ERROR_NAND_OPERATION_FAILED;
 659         }
 660         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 661         {
 662                 u8 *page_buffer;
 663                 u8 *oob_buffer;
 664                 u32 page_bytes_done = 0;
 665                 u32 oob_bytes_done = 0;
 666                 u32 mlc_isr;
 667
 668 #if 0
 669                 if (oob && (oob_size > 6))
 670                 {
 671                         LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
 672                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 673                 }
 674 #endif
 675
 676                 if (data_size > (u32)device->page_size)
 677                 {
 678                         LOG_ERROR("data size exceeds page size");
 679                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 680                 }
 681
 682                 if (device->page_size == 2048)
 683                 {
 684                         page_buffer = malloc(2048);
 685                         oob_buffer = malloc(64);
 686                 }
 687                 else
 688                 {
 689                         page_buffer = malloc(512);
 690                         oob_buffer = malloc(16);
 691                 }
 692
 693                 if (!data && oob)
 694                 {
 695                         /* MLC_CMD = Read OOB
 696                          * we can use the READOOB command on both small and large page devices,
 697                          * as the controller translates the 0x50 command to a 0x0 with appropriate
 698                          * positioning of the serial buffer read pointer
 699                          */
 700                         target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
 701                 }
 702                 else
 703                 {
 704                         /* MLC_CMD = Read0 */
 705                         target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
 706                 }
 707
 708                 if (device->page_size == 512)
 709                 {
 710                         /* small page device */
 711                         /* MLC_ADDR = 0x0 (one column cycle) */
 712                         target_write_u32(target, 0x200b8004, 0x0);
 713
 714                         /* MLC_ADDR = row */
 715                         target_write_u32(target, 0x200b8004, page & 0xff);
 716                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 717
 718                         if (device->address_cycles == 4)
 719                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 720                 }
 721                 else
 722                 {
 723                         /* large page device */
 724                         /* MLC_ADDR = 0x0 (two column cycles) */
 725                         target_write_u32(target, 0x200b8004, 0x0);
 726                         target_write_u32(target, 0x200b8004, 0x0);
 727
 728                         /* MLC_ADDR = row */
 729                         target_write_u32(target, 0x200b8004, page & 0xff);
 730                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 731
 732                         /* MLC_CMD = Read Start */
 733                         target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
 734                 }
 735
 736                 while (page_bytes_done < (u32)device->page_size)
 737                 {
 738                         /* MLC_ECC_AUTO_DEC_REG = dummy */
 739                         target_write_u32(target, 0x200b8014, 0xaa55aa55);
 740
 741                         if (!lpc3180_controller_ready(device, 1000))
 742                         {
 743                                 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
 744                                 return ERROR_NAND_OPERATION_FAILED;
 745                         }
 746
 747                         target_read_u32(target, 0x200b8048, &mlc_isr);
 748
 749                         if (mlc_isr & 0x8)
 750                         {
 751                                 if (mlc_isr & 0x40)
 752                                 {
 753                                         LOG_ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr);
 754                                         return ERROR_NAND_OPERATION_FAILED;
 755                                 }
 756
 757                                 LOG_WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1);
 758                         }
 759
 760                         if (data)
 761                         {
 762                                 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
 763                         }
 764
 765                         if (oob)
 766                         {
 767                                 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
 768                         }
 769
 770                         page_bytes_done += 512;
 771                         oob_bytes_done += 16;
 772                 }
 773
 774                 if (data)
 775                         memcpy(data, page_buffer, data_size);
 776
 777                 if (oob)
 778                         memcpy(oob, oob_buffer, oob_size);
 779
 780                 free(page_buffer);
 781                 free(oob_buffer);
 782         }
 783         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 784         {
 785                 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
 786         }
 787
 788         return ERROR_OK;
 789 }
 790
 791 static int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
 792 {
 793         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 794         target_t *target = lpc3180_info->target;
 795         u8 status = 0x0;
 796
 797         if (target->state != TARGET_HALTED)
 798         {
 799                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 800                 return ERROR_NAND_OPERATION_FAILED;
 801         }
 802
 803         do
 804         {
 805                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 806                 {
 807                         /* Read MLC_ISR, wait for controller to become ready */
 808                         target_read_u8(target, 0x200b8048, &status);
 809
 810                         if (status & 2)
 811                                 return 1;
 812                 }
 813                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 814                 {
 815                         /* we pretend that the SLC controller is always ready */
 816                         return 1;
 817                 }
 818
 819                 alive_sleep(1);
 820         } while (timeout-- > 0);
 821
 822         return 0;
 823 }
 824
 825 static int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
 826 {
 827         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 828         target_t *target = lpc3180_info->target;
 829
 830         if (target->state != TARGET_HALTED)
 831         {
 832                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 833                 return ERROR_NAND_OPERATION_FAILED;
 834         }
 835
 836         do
 837         {
 838                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 839                 {
 840                         u8 status = 0x0;
 841
 842                         /* Read MLC_ISR, wait for NAND flash device to become ready */
 843                         target_read_u8(target, 0x200b8048, &status);
 844
 845                         if (status & 1)
 846                                 return 1;
 847                 }
 848                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 849                 {
 850                         u32 status = 0x0;
 851
 852                         /* Read SLC_STAT and check READY bit */
 853                         target_read_u32(target, 0x20020018, &status);
 854
 855                         if (status & 1)
 856                                 return 1;
 857                 }
 858
 859                 alive_sleep(1);
 860         } while (timeout-- > 0);
 861
 862         return 0;
 863 }
 864
 865 static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 866 {
 867         nand_device_t *device = NULL;
 868         lpc3180_nand_controller_t *lpc3180_info = NULL;
 869         char *selected[] =
 870         {
 871                 "no", "mlc", "slc"
 872         };
 873
 874         if ((argc < 1) || (argc > 2))
 875         {
 876                 return ERROR_COMMAND_SYNTAX_ERROR;
 877         }
 878
 879         device = get_nand_device_by_num(strtoul(args[0], NULL, 0));
 880         if (!device)
 881         {
 882                 command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]);
 883                 return ERROR_OK;
 884         }
 885
 886         lpc3180_info = device->controller_priv;
 887
 888         if (argc == 2)
 889         {
 890                 if (strcmp(args[1], "mlc") == 0)
 891                 {
 892                         lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 893                 }
 894                 else if (strcmp(args[1], "slc") == 0)
 895                 {
 896                         lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
 897                 }
 898                 else
 899                 {
 900                         return ERROR_COMMAND_SYNTAX_ERROR;
 901                 }
 902         }
 903
 904         command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]);
 905
 906         return ERROR_OK;
 907 }