1 /***************************************************************************
2 * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
23 typedef unsigned long mg_io_uint32;
24 typedef unsigned short mg_io_uint16;
25 typedef unsigned char mg_io_uint8;
27 typedef struct mflash_gpio_num_s
33 typedef struct mflash_gpio_drv_s
36 int (*set_gpio_to_output) (mflash_gpio_num_t gpio);
37 int (*set_gpio_output_val) (mflash_gpio_num_t gpio, u8 val);
40 typedef struct _mg_io_type_drv_info {
42 mg_io_uint16 general_configuration; // 00
43 mg_io_uint16 number_of_cylinders; // 01
44 mg_io_uint16 reserved1; // 02
45 mg_io_uint16 number_of_heads; // 03
46 mg_io_uint16 unformatted_bytes_per_track; // 04
47 mg_io_uint16 unformatted_bytes_per_sector; // 05
48 mg_io_uint16 sectors_per_track; // 06
49 mg_io_uint8 vendor_unique1[6]; // 07/08/09
51 mg_io_uint8 serial_number[20]; // 10~19
53 mg_io_uint16 buffer_type; // 20
54 mg_io_uint16 buffer_sector_size; // 21
55 mg_io_uint16 number_of_ecc_bytes; // 22
57 mg_io_uint8 firmware_revision[8]; // 23~26
58 mg_io_uint8 model_number[40]; // 27
60 mg_io_uint8 maximum_block_transfer; // 47 low byte
61 mg_io_uint8 vendor_unique2; // 47 high byte
62 mg_io_uint16 dword_io; // 48
64 mg_io_uint16 capabilities; // 49
65 mg_io_uint16 reserved2; // 50
67 mg_io_uint8 vendor_unique3; // 51 low byte
68 mg_io_uint8 pio_cycle_timing_mode; // 51 high byte
69 mg_io_uint8 vendor_unique4; // 52 low byte
70 mg_io_uint8 dma_cycle_timing_mode; // 52 high byte
71 mg_io_uint16 translation_fields_valid; // 53 (low bit)
72 mg_io_uint16 number_of_current_cylinders; // 54
73 mg_io_uint16 number_of_current_heads; // 55
74 mg_io_uint16 current_sectors_per_track; // 56
75 mg_io_uint16 current_sector_capacity_lo; // 57 & 58
76 mg_io_uint16 current_sector_capacity_hi; // 57 & 58
77 mg_io_uint8 multi_sector_count; // 59 low
78 mg_io_uint8 multi_sector_setting_valid; // 59 high (low bit)
80 mg_io_uint16 total_user_addressable_sectors_lo; // 60 & 61
81 mg_io_uint16 total_user_addressable_sectors_hi; // 60 & 61
83 mg_io_uint8 single_dma_modes_supported; // 62 low byte
84 mg_io_uint8 single_dma_transfer_active; // 62 high byte
85 mg_io_uint8 multi_dma_modes_supported; // 63 low byte
86 mg_io_uint8 multi_dma_transfer_active; // 63 high byte
87 mg_io_uint16 adv_pio_mode;
88 mg_io_uint16 min_dma_cyc;
89 mg_io_uint16 recommend_dma_cyc;
90 mg_io_uint16 min_pio_cyc_no_iordy;
91 mg_io_uint16 min_pio_cyc_with_iordy;
92 mg_io_uint8 reserved3[22];
93 mg_io_uint16 major_ver_num;
94 mg_io_uint16 minor_ver_num;
95 mg_io_uint16 feature_cmd_set_suprt0;
96 mg_io_uint16 feature_cmd_set_suprt1;
97 mg_io_uint16 feature_cmd_set_suprt2;
98 mg_io_uint16 feature_cmd_set_en0;
99 mg_io_uint16 feature_cmd_set_en1;
100 mg_io_uint16 feature_cmd_set_en2;
101 mg_io_uint16 reserved4;
102 mg_io_uint16 req_time_for_security_er_done;
103 mg_io_uint16 req_time_for_enhan_security_er_done;
104 mg_io_uint16 adv_pwr_mgm_lvl_val;
105 mg_io_uint16 reserved5;
106 mg_io_uint16 re_of_hw_rst;
107 mg_io_uint8 reserved6[68];
108 mg_io_uint16 security_stas;
109 mg_io_uint8 vendor_uniq_bytes[62];
110 mg_io_uint16 cfa_pwr_mode;
111 mg_io_uint8 reserved7[186];
113 mg_io_uint16 scts_per_secure_data_unit;
114 mg_io_uint16 integrity_word;
116 } mg_io_type_drv_info;
118 typedef struct mg_drv_info_s {
119 mg_io_type_drv_info drv_id;
123 typedef struct mflash_bank_s
129 mflash_gpio_num_t rst_pin;
130 mflash_gpio_num_t wp_pin;
131 mflash_gpio_num_t dpd_pin;
133 mflash_gpio_drv_t *gpio_drv;
135 mg_drv_info_t *drv_info;
140 extern int mflash_register_commands(struct command_context_s *cmd_ctx);
141 extern int mflash_init_drivers(struct command_context_s *cmd_ctx);
143 #define MG_MFLASH_SECTOR_SIZE (0x200) //512Bytes = 2^9
144 #define MG_MFLASH_SECTOR_SIZE_MASK (0x200-1)
145 #define MG_MFLASH_SECTOR_SIZE_SHIFT (9)
147 #define MG_BUFFER_OFFSET 0x8000
148 #define MG_REG_OFFSET 0xC000
149 #define MG_REG_FEATURE 0x2 // write case
150 #define MG_REG_ERROR 0x2 // read case
151 #define MG_REG_SECT_CNT 0x4
152 #define MG_REG_SECT_NUM 0x6
153 #define MG_REG_CYL_LOW 0x8
154 #define MG_REG_CYL_HIGH 0xA
155 #define MG_REG_DRV_HEAD 0xC
156 #define MG_REG_COMMAND 0xE // write case
157 #define MG_REG_STATUS 0xE // read case
158 #define MG_REG_DRV_CTRL 0x10
159 #define MG_REG_BURST_CTRL 0x12
161 #define MG_OEM_DISK_WAIT_TIME_LONG 15000 // msec
162 #define MG_OEM_DISK_WAIT_TIME_NORMAL 3000 // msec
163 #define MG_OEM_DISK_WAIT_TIME_SHORT 1000 // msec
165 typedef enum _mg_io_type_wait{
168 mg_io_wait_not_bsy = 2,
170 mg_io_wait_drq = 4, // wait for data request
171 mg_io_wait_drq_noerr = 5, // wait for DRQ but ignore the error status bit
172 mg_io_wait_rdy_noerr = 6 // wait for ready, but ignore error status bit
176 //= "Status Register" bit masks.
177 typedef enum _mg_io_type_rbit_status{
179 mg_io_rbit_status_error = 0x01, // error bit in status register
180 mg_io_rbit_status_corrected_error = 0x04, // corrected error in status register
181 mg_io_rbit_status_data_req = 0x08, // data request bit in status register
182 mg_io_rbit_status_seek_done = 0x10, // DSC - Drive Seek Complete
183 mg_io_rbit_status_write_fault = 0x20, // DWF - Drive Write Fault
184 mg_io_rbit_status_ready = 0x40,
185 mg_io_rbit_status_busy = 0x80
187 } mg_io_type_rbit_status;
189 //= "Error Register" bit masks.
190 typedef enum _mg_io_type_rbit_error{
192 mg_io_rbit_err_general = 0x01,
193 mg_io_rbit_err_aborted = 0x04,
194 mg_io_rbit_err_bad_sect_num = 0x10,
195 mg_io_rbit_err_uncorrectable = 0x40,
196 mg_io_rbit_err_bad_block = 0x80
198 } mg_io_type_rbit_error;
200 //= "Device Control Register" bit.
201 typedef enum _mg_io_type_rbit_devc{
203 mg_io_rbit_devc_intr = 0x02,// interrupt enable bit (1:disable, 0:enable)
204 mg_io_rbit_devc_srst = 0x04 // softwrae reset bit (1:assert, 0:de-assert)
206 } mg_io_type_rbit_devc;
208 // "Drive Select/Head Register" values.
209 typedef enum _mg_io_type_rval_dev{
211 mg_io_rval_dev_must_be_on = 0x80, // These 1 bits are always on
212 mg_io_rval_dev_drv_master = (0x00 | mg_io_rval_dev_must_be_on),// Master
213 mg_io_rval_dev_drv_slave0 = (0x10 | mg_io_rval_dev_must_be_on),// Slave0
214 mg_io_rval_dev_drv_slave1 = (0x20 | mg_io_rval_dev_must_be_on),// Slave1
215 mg_io_rval_dev_drv_slave2 = (0x30 | mg_io_rval_dev_must_be_on),// Slave2
216 mg_io_rval_dev_lba_mode = (0x40 | mg_io_rval_dev_must_be_on)
218 } mg_io_type_rval_dev;
220 typedef enum _mg_io_type_cmd
222 mg_io_cmd_read =0x20,
223 mg_io_cmd_write =0x30,
225 mg_io_cmd_setmul =0xC6,
226 mg_io_cmd_readmul =0xC4,
227 mg_io_cmd_writemul =0xC5,
229 mg_io_cmd_idle =0x97,//0xE3
230 mg_io_cmd_idle_immediate =0x95,//0xE1
232 mg_io_cmd_setsleep =0x99,//0xE6
233 mg_io_cmd_stdby =0x96,//0xE2
234 mg_io_cmd_stdby_immediate =0x94,//0xE0
236 mg_io_cmd_identify =0xEC,
237 mg_io_cmd_set_feature =0xEF,
239 mg_io_cmd_confirm_write =0x3C,
240 mg_io_cmd_confirm_read =0x40,
241 mg_io_cmd_wakeup =0xC3