2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %" PRId32 " is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
46 static const char get_status_register_err_msg[] = "can't get NAND status";
47 static uint32_t in_sram_address;
48 unsigned char sign_of_sequental_byte_read;
50 static int test_iomux_settings (target_t * target, uint32_t value,
51 uint32_t mask, const char *text);
52 static int initialize_nf_controller (struct nand_device_s *nand);
53 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
54 static int get_next_halfword_from_sram_buffer (target_t * target,
56 static int poll_for_complete_op (target_t * target, const char *text);
57 static int validate_target_state (struct nand_device_s *nand);
58 static int do_data_output (struct nand_device_s *nand);
60 static int imx31_command (struct nand_device_s *nand, uint8_t command);
61 static int imx31_address (struct nand_device_s *nand, uint8_t address);
62 static int imx31_controller_ready (struct nand_device_s *nand, int tout);
64 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
65 char *cmd, char **args, int argc,
66 struct nand_device_s *nand)
68 mx3_nf_controller_t *mx3_nf_info;
69 mx3_nf_info = malloc (sizeof (mx3_nf_controller_t));
70 if (mx3_nf_info == NULL)
72 LOG_ERROR ("no memory for nand controller");
76 nand->controller_priv = mx3_nf_info;
78 mx3_nf_info->target = get_target (args[1]);
79 if (mx3_nf_info->target == NULL)
81 LOG_ERROR ("target '%s' not defined", args[1]);
86 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
90 * check hwecc requirements
94 hwecc_needed = strcmp (args[2], "hwecc");
95 if (hwecc_needed == 0)
97 mx3_nf_info->flags.hw_ecc_enabled = 1;
101 mx3_nf_info->flags.hw_ecc_enabled = 0;
105 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
106 mx3_nf_info->fin = MX3_NF_FIN_NONE;
107 mx3_nf_info->flags.target_little_endian =
108 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
110 * testing host endianess
114 if (*(char *) &x == 1)
116 mx3_nf_info->flags.host_little_endian = 1;
120 mx3_nf_info->flags.host_little_endian = 0;
126 static int imx31_init (struct nand_device_s *nand)
128 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
129 target_t *target = mx3_nf_info->target;
133 * validate target state
135 int validate_target_result;
136 validate_target_result = validate_target_state(nand);
137 if (validate_target_result != ERROR_OK)
139 return validate_target_result;
144 uint16_t buffsize_register_content;
145 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
146 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
150 uint32_t pcsr_register_content;
151 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
152 if (!nand->bus_width)
155 (pcsr_register_content & 0x80000000) ? 16 : 8;
159 pcsr_register_content |=
160 ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
161 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
164 if (!nand->page_size)
167 (pcsr_register_content & 0x40000000) ? 2048 : 512;
171 pcsr_register_content |=
172 ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
173 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
175 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
178 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
183 uint32_t cgr_register_content;
184 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
185 if (!(cgr_register_content & 0x00000300))
187 LOG_ERROR ("clock gating to EMI disabled");
193 uint32_t gpr_register_content;
194 target_read_u32 (target, MX3_GPR, &gpr_register_content);
195 if (gpr_register_content & 0x00000060)
197 LOG_ERROR ("pins mode overrided by GPR");
204 * testing IOMUX settings; must be in "functional-mode output and
205 * functional-mode input" mode
208 test_iomux = ERROR_OK;
210 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
212 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
214 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
215 if (nand->bus_width == 16)
218 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
221 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
224 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
227 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
230 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
231 "nfwe,nfre,nfale,nfcle");
232 if (test_iomux != ERROR_OK)
238 initialize_nf_controller (nand);
242 uint16_t nand_status_content;
244 retval |= imx31_command (nand, NAND_CMD_STATUS);
245 retval |= imx31_address (nand, 0x00);
246 retval |= do_data_output (nand);
247 if (retval != ERROR_OK)
249 LOG_ERROR (get_status_register_err_msg);
252 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
253 if (!(nand_status_content & 0x0080))
256 * is host-big-endian correctly ??
258 LOG_INFO ("NAND read-only");
259 mx3_nf_info->flags.nand_readonly = 1;
263 mx3_nf_info->flags.nand_readonly = 0;
269 static int imx31_read_data (struct nand_device_s *nand, void *data)
271 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
272 target_t *target = mx3_nf_info->target;
275 * validate target state
277 int validate_target_result;
278 validate_target_result = validate_target_state (nand);
279 if (validate_target_result != ERROR_OK)
281 return validate_target_result;
287 * get data from nand chip
289 int try_data_output_from_nand_chip;
290 try_data_output_from_nand_chip = do_data_output (nand);
291 if (try_data_output_from_nand_chip != ERROR_OK)
293 return try_data_output_from_nand_chip;
297 if (nand->bus_width == 16)
299 get_next_halfword_from_sram_buffer (target, data);
303 get_next_byte_from_sram_buffer (target, data);
309 static int imx31_write_data (struct nand_device_s *nand, uint16_t data)
311 LOG_ERROR ("write_data() not implemented");
312 return ERROR_NAND_OPERATION_FAILED;
315 static int imx31_nand_ready (struct nand_device_s *nand, int timeout)
317 return imx31_controller_ready (nand, timeout);
320 static int imx31_register_commands (struct command_context_s *cmd_ctx)
325 static int imx31_reset (struct nand_device_s *nand)
328 * validate target state
330 int validate_target_result;
331 validate_target_result = validate_target_state (nand);
332 if (validate_target_result != ERROR_OK)
334 return validate_target_result;
336 initialize_nf_controller (nand);
340 static int imx31_command (struct nand_device_s *nand, uint8_t command)
342 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
343 target_t *target = mx3_nf_info->target;
346 * validate target state
348 int validate_target_result;
349 validate_target_result = validate_target_state (nand);
350 if (validate_target_result != ERROR_OK)
352 return validate_target_result;
358 case NAND_CMD_READOOB:
359 command = NAND_CMD_READ0;
360 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
362 * read_block_data() to
367 command = NAND_CMD_READ0;
369 * offset == one half of page size
372 MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
374 in_sram_address = MX3_NF_MAIN_BUFFER0;
377 target_write_u16 (target, MX3_NF_FCMD, command);
379 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
381 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
384 poll_result = poll_for_complete_op (target, "command");
385 if (poll_result != ERROR_OK)
391 * reset cursor to begin of the buffer
393 sign_of_sequental_byte_read = 0;
396 case NAND_CMD_READID:
397 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
398 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
400 case NAND_CMD_STATUS:
401 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
402 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
405 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
406 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
409 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
414 static int imx31_address (struct nand_device_s *nand, uint8_t address)
416 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
417 target_t *target = mx3_nf_info->target;
420 * validate target state
422 int validate_target_result;
423 validate_target_result = validate_target_state (nand);
424 if (validate_target_result != ERROR_OK)
426 return validate_target_result;
430 target_write_u16 (target, MX3_NF_FADDR, address);
432 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
434 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
437 poll_result = poll_for_complete_op (target, "address");
438 if (poll_result != ERROR_OK)
446 static int imx31_controller_ready (struct nand_device_s *nand, int tout)
448 uint16_t poll_complete_status;
449 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
450 target_t *target = mx3_nf_info->target;
454 * validate target state
456 int validate_target_result;
457 validate_target_result = validate_target_state (nand);
458 if (validate_target_result != ERROR_OK)
460 return validate_target_result;
466 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
467 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
477 static int imx31_write_page (struct nand_device_s *nand, uint32_t page,
478 uint8_t * data, uint32_t data_size, uint8_t * oob,
481 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
482 target_t *target = mx3_nf_info->target;
486 LOG_ERROR (data_block_size_err_msg, data_size);
487 return ERROR_NAND_OPERATION_FAILED;
491 LOG_ERROR (data_block_size_err_msg, oob_size);
492 return ERROR_NAND_OPERATION_FAILED;
496 LOG_ERROR ("nothing to program");
497 return ERROR_NAND_OPERATION_FAILED;
501 * validate target state
504 retval = validate_target_state (nand);
505 if (retval != ERROR_OK)
511 int retval = ERROR_OK;
512 retval |= imx31_command(nand, NAND_CMD_SEQIN);
513 retval |= imx31_address(nand, 0x00);
514 retval |= imx31_address(nand, page & 0xff);
515 retval |= imx31_address(nand, (page >> 8) & 0xff);
516 if (nand->address_cycles >= 4)
518 retval |= imx31_address (nand, (page >> 16) & 0xff);
519 if (nand->address_cycles >= 5)
521 retval |= imx31_address (nand, (page >> 24) & 0xff);
524 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
527 if (mx3_nf_info->flags.hw_ecc_enabled)
530 * part of spare block will be overrided by hardware
534 ("part of spare block will be overrided by hardware ECC generator");
536 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
540 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
542 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
545 poll_result = poll_for_complete_op (target, "data input");
546 if (poll_result != ERROR_OK)
551 retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
552 if (retval != ERROR_OK)
558 * check status register
561 uint16_t nand_status_content;
563 retval |= imx31_command(nand, NAND_CMD_STATUS);
564 retval |= imx31_address(nand, 0x00);
565 retval |= do_data_output(nand);
566 if (retval != ERROR_OK)
568 LOG_ERROR (get_status_register_err_msg);
571 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
572 if (nand_status_content & 0x0001)
575 * is host-big-endian correctly ??
577 return ERROR_NAND_OPERATION_FAILED;
584 static int imx31_read_page (struct nand_device_s *nand, uint32_t page,
585 uint8_t * data, uint32_t data_size, uint8_t * oob,
588 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
589 target_t *target = mx3_nf_info->target;
593 LOG_ERROR (data_block_size_err_msg, data_size);
594 return ERROR_NAND_OPERATION_FAILED;
598 LOG_ERROR (data_block_size_err_msg, oob_size);
599 return ERROR_NAND_OPERATION_FAILED;
604 * validate target state
607 retval = validate_target_state(nand);
608 if (retval != ERROR_OK)
614 int retval = ERROR_OK;
615 retval |= imx31_command(nand, NAND_CMD_READ0);
616 retval |= imx31_address(nand, 0x00);
617 retval |= imx31_address(nand, page & 0xff);
618 retval |= imx31_address(nand, (page >> 8) & 0xff);
619 if (nand->address_cycles >= 4)
621 retval |= imx31_address(nand, (page >> 16) & 0xff);
622 if (nand->address_cycles >= 5)
624 retval |= imx31_address(nand, (page >> 24) & 0xff);
625 retval |= imx31_command(nand, NAND_CMD_READSTART);
628 retval |= do_data_output (nand);
629 if (retval != ERROR_OK)
636 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
641 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
648 static int test_iomux_settings (target_t * target, uint32_t address,
649 uint32_t mask, const char *text)
651 uint32_t register_content;
652 target_read_u32 (target, address, ®ister_content);
653 if ((register_content & mask) != (0x12121212 & mask))
655 LOG_ERROR ("IOMUX for {%s} is bad", text);
661 static int initialize_nf_controller (struct nand_device_s *nand)
663 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
664 target_t *target = mx3_nf_info->target;
666 * resets NAND flash controller in zero time ? I dont know.
668 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
671 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
672 if (target->endianness == TARGET_BIG_ENDIAN)
674 work_mode |= MX3_NF_BIT_BE_EN;
676 if (mx3_nf_info->flags.hw_ecc_enabled)
678 work_mode |= MX3_NF_BIT_ECC_EN;
680 target_write_u16 (target, MX3_NF_CFG1, work_mode);
683 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
685 target_write_u16 (target, MX3_NF_BUFCFG, 2);
688 target_read_u16 (target, MX3_NF_FWP, &temp);
689 if ((temp & 0x0007) == 1)
691 LOG_ERROR ("NAND flash is tight-locked, reset needed");
697 * unlock NAND flash for write
699 target_write_u16 (target, MX3_NF_FWP, 4);
700 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
701 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
703 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
705 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
707 * address of SRAM buffer
709 in_sram_address = MX3_NF_MAIN_BUFFER0;
710 sign_of_sequental_byte_read = 0;
714 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
716 static uint8_t even_byte = 0;
720 if (sign_of_sequental_byte_read == 0)
724 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
726 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
728 sign_of_sequental_byte_read = 0;
730 return ERROR_NAND_OPERATION_FAILED;
735 target_read_u16 (target, in_sram_address, &temp);
740 in_sram_address += 2;
744 *value = temp & 0xff;
748 sign_of_sequental_byte_read = 1;
752 static int get_next_halfword_from_sram_buffer (target_t * target,
755 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
757 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
759 return ERROR_NAND_OPERATION_FAILED;
763 target_read_u16 (target, in_sram_address, value);
764 in_sram_address += 2;
769 static int poll_for_complete_op (target_t * target, const char *text)
771 uint16_t poll_complete_status;
772 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
775 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
776 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
781 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
783 LOG_ERROR ("%s sending timeout", text);
784 return ERROR_NAND_OPERATION_FAILED;
789 static int validate_target_state (struct nand_device_s *nand)
791 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
792 target_t *target = mx3_nf_info->target;
794 if (target->state != TARGET_HALTED)
796 LOG_ERROR (target_not_halted_err_msg);
797 return ERROR_NAND_OPERATION_FAILED;
800 if (mx3_nf_info->flags.target_little_endian !=
801 (target->endianness == TARGET_LITTLE_ENDIAN))
804 * endianness changed after NAND controller probed
806 return ERROR_NAND_OPERATION_FAILED;
811 static int do_data_output (struct nand_device_s *nand)
813 mx3_nf_controller_t *mx3_nf_info = nand->controller_priv;
814 target_t *target = mx3_nf_info->target;
815 switch (mx3_nf_info->fin)
817 case MX3_NF_FIN_DATAOUT:
819 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
821 target_write_u16 (target, MX3_NF_CFG2,
822 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
826 poll_result = poll_for_complete_op (target, "data output");
827 if (poll_result != ERROR_OK)
832 mx3_nf_info->fin = MX3_NF_FIN_NONE;
836 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
837 && mx3_nf_info->flags.hw_ecc_enabled)
840 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
841 switch (ecc_status & 0x000c)
845 ("main area readed with 1 (correctable) error");
849 ("main area readed with more than 1 (incorrectable) error");
850 return ERROR_NAND_OPERATION_FAILED;
853 switch (ecc_status & 0x0003)
857 ("spare area readed with 1 (correctable) error");
861 ("main area readed with more than 1 (incorrectable) error");
862 return ERROR_NAND_OPERATION_FAILED;
867 case MX3_NF_FIN_NONE:
873 nand_flash_controller_t imx31_nand_flash_controller = {
875 .nand_device_command = &imx31_nand_device_command,
876 .register_commands = &imx31_register_commands,
878 .reset = &imx31_reset,
879 .command = &imx31_command,
880 .address = &imx31_address,
881 .write_data = &imx31_write_data,
882 .read_data = &imx31_read_data,
883 .write_page = &imx31_write_page,
884 .read_page = &imx31_read_page,
885 .controller_ready = &imx31_controller_ready,
886 .nand_ready = &imx31_nand_ready,