2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %d is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%x)";
46 static const char invalid_command_sequense_err_msg[] =
47 "invalid command sequence in %s";
48 static const char get_status_register_err_msg[] = "can't get NAND status";
49 static uint32_t in_sram_address;
50 unsigned char sign_of_sequental_byte_read;
52 static int test_iomux_settings (target_t * target, uint32_t value,
53 uint32_t mask, const char *text);
54 static int initialize_nf_controller (struct nand_device_s *device);
55 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
56 static int get_next_halfword_from_sram_buffer (target_t * target,
58 static int poll_for_complete_op (target_t * target, const char *text);
59 static int validate_target_state (struct nand_device_s *device);
60 static int do_data_output (struct nand_device_s *device);
62 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
63 char *cmd, char **args, int argc,
64 struct nand_device_s *device);
65 static int imx31_init (struct nand_device_s *device);
66 static int imx31_read_data (struct nand_device_s *device, void *data);
67 static int imx31_write_data (struct nand_device_s *device, uint16_t data);
68 static int imx31_nand_ready (struct nand_device_s *device, int timeout);
69 static int imx31_register_commands (struct command_context_s *cmd_ctx);
70 static int imx31_reset (struct nand_device_s *device);
71 static int imx31_command (struct nand_device_s *device, uint8_t command);
72 static int imx31_address (struct nand_device_s *device, uint8_t address);
73 static int imx31_controller_ready (struct nand_device_s *device, int tout);
74 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
75 uint8_t * data, uint32_t data_size, uint8_t * oob,
77 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
78 uint8_t * data, uint32_t data_size, uint8_t * oob,
81 nand_flash_controller_t imx31_nand_flash_controller = {
83 .nand_device_command = imx31_nand_device_command,
84 .register_commands = imx31_register_commands,
87 .command = imx31_command,
88 .address = imx31_address,
89 .write_data = imx31_write_data,
90 .read_data = imx31_read_data,
91 .write_page = imx31_write_page,
92 .read_page = imx31_read_page,
93 .controller_ready = imx31_controller_ready,
94 .nand_ready = imx31_nand_ready,
97 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
98 char *cmd, char **args, int argc,
99 struct nand_device_s *device)
101 mx3_nf_controller_t *mx3_nf_info;
102 mx3_nf_info = malloc (sizeof (mx3_nf_controller_t));
103 if (mx3_nf_info == NULL)
105 LOG_ERROR ("no memory for nand controller");
109 device->controller_priv = mx3_nf_info;
111 mx3_nf_info->target = get_target (args[1]);
112 if (mx3_nf_info->target == NULL)
114 LOG_ERROR ("target '%s' not defined", args[1]);
119 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
123 * check hwecc requirements
127 hwecc_needed = strcmp (args[2], "hwecc");
128 if (hwecc_needed == 0)
130 mx3_nf_info->flags.hw_ecc_enabled = 1;
134 mx3_nf_info->flags.hw_ecc_enabled = 0;
138 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
139 mx3_nf_info->fin = MX3_NF_FIN_NONE;
140 mx3_nf_info->flags.target_little_endian =
141 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
143 * testing host endianess
147 if (*(char *) &x == 1)
149 mx3_nf_info->flags.host_little_endian = 1;
153 mx3_nf_info->flags.host_little_endian = 0;
159 static int imx31_init (struct nand_device_s *device)
161 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
162 target_t *target = mx3_nf_info->target;
166 * validate target state
168 int validate_target_result;
169 validate_target_result = validate_target_state (device);
170 if (validate_target_result != ERROR_OK)
172 return validate_target_result;
177 uint16_t buffsize_register_content;
178 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
179 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
183 uint32_t pcsr_register_content;
184 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
185 if (!device->bus_width)
188 (pcsr_register_content & 0x80000000) ? 16 : 8;
192 pcsr_register_content |=
193 ((device->bus_width == 16) ? 0x80000000 : 0x00000000);
194 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
197 if (!device->page_size)
200 (pcsr_register_content & 0x40000000) ? 2048 : 512;
204 pcsr_register_content |=
205 ((device->page_size == 2048) ? 0x40000000 : 0x00000000);
206 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
208 if (mx3_nf_info->flags.one_kb_sram && (device->page_size == 2048))
211 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
216 uint32_t cgr_register_content;
217 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
218 if (!(cgr_register_content & 0x00000300))
220 LOG_ERROR ("clock gating to EMI disabled");
226 uint32_t gpr_register_content;
227 target_read_u32 (target, MX3_GPR, &gpr_register_content);
228 if (gpr_register_content & 0x00000060)
230 LOG_ERROR ("pins mode overrided by GPR");
237 * testing IOMUX settings; must be in "functional-mode output and
238 * functional-mode input" mode
241 test_iomux = ERROR_OK;
243 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
245 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
247 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
248 if (device->bus_width == 16)
251 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
254 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
257 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
260 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
263 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
264 "nfwe,nfre,nfale,nfcle");
265 if (test_iomux != ERROR_OK)
271 initialize_nf_controller (device);
275 uint16_t nand_status_content;
277 retval |= imx31_command (device, NAND_CMD_STATUS);
278 retval |= imx31_address (device, 0x00);
279 retval |= do_data_output (device);
280 if (retval != ERROR_OK)
282 LOG_ERROR (get_status_register_err_msg);
285 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
286 if (!(nand_status_content & 0x0080))
289 * is host-big-endian correctly ??
291 LOG_INFO ("NAND read-only");
292 mx3_nf_info->flags.nand_readonly = 1;
296 mx3_nf_info->flags.nand_readonly = 0;
302 static int imx31_read_data (struct nand_device_s *device, void *data)
304 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
305 target_t *target = mx3_nf_info->target;
308 * validate target state
310 int validate_target_result;
311 validate_target_result = validate_target_state (device);
312 if (validate_target_result != ERROR_OK)
314 return validate_target_result;
320 * get data from nand chip
322 int try_data_output_from_nand_chip;
323 try_data_output_from_nand_chip = do_data_output (device);
324 if (try_data_output_from_nand_chip != ERROR_OK)
326 return try_data_output_from_nand_chip;
330 if (device->bus_width == 16)
332 get_next_halfword_from_sram_buffer (target, data);
336 get_next_byte_from_sram_buffer (target, data);
342 static int imx31_write_data (struct nand_device_s *device, uint16_t data)
344 LOG_ERROR ("write_data() not implemented");
345 return ERROR_NAND_OPERATION_FAILED;
348 static int imx31_nand_ready (struct nand_device_s *device, int timeout)
350 return imx31_controller_ready (device, timeout);
353 static int imx31_register_commands (struct command_context_s *cmd_ctx)
358 static int imx31_reset (struct nand_device_s *device)
361 * validate target state
363 int validate_target_result;
364 validate_target_result = validate_target_state (device);
365 if (validate_target_result != ERROR_OK)
367 return validate_target_result;
369 initialize_nf_controller (device);
373 static int imx31_command (struct nand_device_s *device, uint8_t command)
375 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
376 target_t *target = mx3_nf_info->target;
379 * validate target state
381 int validate_target_result;
382 validate_target_result = validate_target_state (device);
383 if (validate_target_result != ERROR_OK)
385 return validate_target_result;
391 case NAND_CMD_READOOB:
392 command = NAND_CMD_READ0;
393 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
395 * read_block_data() to
400 command = NAND_CMD_READ0;
402 * offset == one half of page size
405 MX3_NF_MAIN_BUFFER0 + (device->page_size >> 1);
407 in_sram_address = MX3_NF_MAIN_BUFFER0;
410 target_write_u16 (target, MX3_NF_FCMD, command);
412 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
414 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
417 poll_result = poll_for_complete_op (target, "command");
418 if (poll_result != ERROR_OK)
424 * reset cursor to begin of the buffer
426 sign_of_sequental_byte_read = 0;
429 case NAND_CMD_READID:
430 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
431 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
433 case NAND_CMD_STATUS:
434 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
435 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
438 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
439 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
446 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
451 static int imx31_address (struct nand_device_s *device, uint8_t address)
453 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
454 target_t *target = mx3_nf_info->target;
457 * validate target state
459 int validate_target_result;
460 validate_target_result = validate_target_state (device);
461 if (validate_target_result != ERROR_OK)
463 return validate_target_result;
467 target_write_u16 (target, MX3_NF_FADDR, address);
469 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
471 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
474 poll_result = poll_for_complete_op (target, "address");
475 if (poll_result != ERROR_OK)
483 static int imx31_controller_ready (struct nand_device_s *device, int tout)
485 uint16_t poll_complete_status;
486 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
487 target_t *target = mx3_nf_info->target;
491 * validate target state
493 int validate_target_result;
494 validate_target_result = validate_target_state (device);
495 if (validate_target_result != ERROR_OK)
497 return validate_target_result;
503 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
504 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
514 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
515 uint8_t * data, uint32_t data_size, uint8_t * oob,
518 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
519 target_t *target = mx3_nf_info->target;
523 LOG_ERROR (data_block_size_err_msg, data_size);
524 return ERROR_NAND_OPERATION_FAILED;
528 LOG_ERROR (data_block_size_err_msg, oob_size);
529 return ERROR_NAND_OPERATION_FAILED;
533 LOG_ERROR ("nothing to program");
534 return ERROR_NAND_OPERATION_FAILED;
538 * validate target state
541 retval = validate_target_state (device);
542 if (retval != ERROR_OK)
548 int retval = ERROR_OK;
549 retval |= imx31_command (device, NAND_CMD_SEQIN);
550 retval |= imx31_address (device, 0x00);
551 retval |= imx31_address (device, page & 0xff);
552 retval |= imx31_address (device, (page >> 8) & 0xff);
553 if (device->address_cycles >= 4)
555 retval |= imx31_address (device, (page >> 16) & 0xff);
556 if (device->address_cycles >= 5)
558 retval |= imx31_address (device, (page >> 24) & 0xff);
561 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
564 if (mx3_nf_info->flags.hw_ecc_enabled)
567 * part of spare block will be overrided by hardware
571 ("part of spare block will be overrided by hardware ECC generator");
573 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
577 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
579 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
582 poll_result = poll_for_complete_op (target, "data input");
583 if (poll_result != ERROR_OK)
588 retval |= imx31_command (device, NAND_CMD_PAGEPROG);
589 if (retval != ERROR_OK)
595 * check status register
598 uint16_t nand_status_content;
600 retval |= imx31_command (device, NAND_CMD_STATUS);
601 retval |= imx31_address (device, 0x00);
602 retval |= do_data_output (device);
603 if (retval != ERROR_OK)
605 LOG_ERROR (get_status_register_err_msg);
608 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
609 if (nand_status_content & 0x0001)
612 * is host-big-endian correctly ??
614 return ERROR_NAND_OPERATION_FAILED;
621 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
622 uint8_t * data, uint32_t data_size, uint8_t * oob,
625 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
626 target_t *target = mx3_nf_info->target;
630 LOG_ERROR (data_block_size_err_msg, data_size);
631 return ERROR_NAND_OPERATION_FAILED;
635 LOG_ERROR (data_block_size_err_msg, oob_size);
636 return ERROR_NAND_OPERATION_FAILED;
641 * validate target state
644 retval = validate_target_state (device);
645 if (retval != ERROR_OK)
651 int retval = ERROR_OK;
652 retval |= imx31_command (device, NAND_CMD_READ0);
653 retval |= imx31_address (device, 0x00);
654 retval |= imx31_address (device, page & 0xff);
655 retval |= imx31_address (device, (page >> 8) & 0xff);
656 if (device->address_cycles >= 4)
658 retval |= imx31_address (device, (page >> 16) & 0xff);
659 if (device->address_cycles >= 5)
661 retval |= imx31_address (device, (page >> 24) & 0xff);
662 retval |= imx31_command (device, NAND_CMD_READSTART);
665 retval |= do_data_output (device);
666 if (retval != ERROR_OK)
673 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
678 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
685 static int test_iomux_settings (target_t * target, uint32_t address,
686 uint32_t mask, const char *text)
688 uint32_t register_content;
689 target_read_u32 (target, address, ®ister_content);
690 if ((register_content & mask) != (0x12121212 & mask))
692 LOG_ERROR ("IOMUX for {%s} is bad", text);
698 static int initialize_nf_controller (struct nand_device_s *device)
700 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
701 target_t *target = mx3_nf_info->target;
703 * resets NAND flash controller in zero time ? I dont know.
705 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
708 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
709 if (target->endianness == TARGET_BIG_ENDIAN)
711 work_mode |= MX3_NF_BIT_BE_EN;
713 if (mx3_nf_info->flags.hw_ecc_enabled)
715 work_mode |= MX3_NF_BIT_ECC_EN;
717 target_write_u16 (target, MX3_NF_CFG1, work_mode);
720 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
722 target_write_u16 (target, MX3_NF_BUFCFG, 2);
725 target_read_u16 (target, MX3_NF_FWP, &temp);
726 if ((temp & 0x0007) == 1)
728 LOG_ERROR ("NAND flash is tight-locked, reset needed");
734 * unlock NAND flash for write
736 target_write_u16 (target, MX3_NF_FWP, 4);
737 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
738 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
740 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
742 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
744 * address of SRAM buffer
746 in_sram_address = MX3_NF_MAIN_BUFFER0;
747 sign_of_sequental_byte_read = 0;
751 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
753 static uint8_t even_byte = 0;
757 if (sign_of_sequental_byte_read == 0)
761 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
763 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
765 sign_of_sequental_byte_read = 0;
767 return ERROR_NAND_OPERATION_FAILED;
772 target_read_u16 (target, in_sram_address, &temp);
777 in_sram_address += 2;
781 *value = temp & 0xff;
785 sign_of_sequental_byte_read = 1;
789 static int get_next_halfword_from_sram_buffer (target_t * target,
792 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
794 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
796 return ERROR_NAND_OPERATION_FAILED;
800 target_read_u16 (target, in_sram_address, value);
801 in_sram_address += 2;
806 static int poll_for_complete_op (target_t * target, const char *text)
808 uint16_t poll_complete_status;
809 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
812 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
813 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
818 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
820 LOG_ERROR ("%s sending timeout", text);
821 return ERROR_NAND_OPERATION_FAILED;
826 static int validate_target_state (struct nand_device_s *device)
828 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
829 target_t *target = mx3_nf_info->target;
831 if (target->state != TARGET_HALTED)
833 LOG_ERROR (target_not_halted_err_msg);
834 return ERROR_NAND_OPERATION_FAILED;
837 if (mx3_nf_info->flags.target_little_endian !=
838 (target->endianness == TARGET_LITTLE_ENDIAN))
841 * endianness changed after NAND controller probed
843 return ERROR_NAND_OPERATION_FAILED;
848 static int do_data_output (struct nand_device_s *device)
850 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
851 target_t *target = mx3_nf_info->target;
852 switch (mx3_nf_info->fin)
854 case MX3_NF_FIN_DATAOUT:
856 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
858 target_write_u16 (target, MX3_NF_CFG2,
859 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
863 poll_result = poll_for_complete_op (target, "data output");
864 if (poll_result != ERROR_OK)
869 mx3_nf_info->fin = MX3_NF_FIN_NONE;
873 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
874 && mx3_nf_info->flags.hw_ecc_enabled)
877 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
878 switch (ecc_status & 0x000c)
882 ("main area readed with 1 (correctable) error");
886 ("main area readed with more than 1 (incorrectable) error");
887 return ERROR_NAND_OPERATION_FAILED;
890 switch (ecc_status & 0x0003)
894 ("spare area readed with 1 (correctable) error");
898 ("main area readed with more than 1 (incorrectable) error");
899 return ERROR_NAND_OPERATION_FAILED;
904 case MX3_NF_FIN_NONE: