git.sur5r.net Git - openocd/blob - src/flash/nand/lpc3180.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *
   5  *   Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com>                *
   6  *   Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include "lpc3180.h"
  29 #include <target/target.h>
  30
  31
  32 static int lpc3180_reset(struct nand_device *nand);
  33 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
  34 static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
  35
  36
  37 #define ECC_OFFS   0x120
  38 #define SPARE_OFFS 0x140
  39 #define DATA_OFFS   0x200
  40
  41
  42 /* nand device lpc3180 <target#> <oscillator_frequency>
  43  */
  44 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
  45 {
  46         if (CMD_ARGC < 3)
  47         {
  48                 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
  49                 return ERROR_FLASH_BANK_INVALID;
  50         }
  51
  52         struct target *target = get_target(CMD_ARGV[1]);
  53         if (NULL == target)
  54         {
  55                 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
  56                 return ERROR_NAND_DEVICE_INVALID;
  57         }
  58
  59         uint32_t osc_freq;
  60         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  61
  62         struct lpc3180_nand_controller *lpc3180_info;
  63         lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
  64         nand->controller_priv = lpc3180_info;
  65
  66         lpc3180_info->target = target;
  67         lpc3180_info->osc_freq = osc_freq;
  68
  69         if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  70         {
  71                 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
  72         }
  73         lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  74         lpc3180_info->sw_write_protection = 0;
  75         lpc3180_info->sw_wp_lower_bound = 0x0;
  76         lpc3180_info->sw_wp_upper_bound = 0x0;
  77
  78         return ERROR_OK;
  79 }
  80
  81 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
  82 {
  83         int bypass = (pll_ctrl & 0x8000) >> 15;
  84         int direct = (pll_ctrl & 0x4000) >> 14;
  85         int feedback = (pll_ctrl & 0x2000) >> 13;
  86         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  87         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  88         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  89         int lock = (pll_ctrl & 0x1);
  90
  91         if (!lock)
  92                 LOG_WARNING("PLL is not locked");
  93
  94         if (!bypass && direct)  /* direct mode */
  95                 return (m * fclkin) / n;
  96
  97         if (bypass && !direct)  /* bypass mode */
  98                 return fclkin / (2 * p);
  99
 100         if (bypass & direct)    /* direct bypass mode */
 101                 return fclkin;
 102
 103         if (feedback)                   /* integer mode */
 104                 return m * (fclkin / n);
 105         else                                    /* non-integer mode */
 106                 return (m / (2 * p)) * (fclkin / n);
 107 }
 108
 109 static float lpc3180_cycle_time(struct lpc3180_nand_controller *lpc3180_info)
 110 {
 111         struct target *target = lpc3180_info->target;
 112         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 113         int sysclk;
 114         int hclk;
 115         int hclk_pll;
 116         float cycle;
 117
 118         /* calculate timings */
 119
 120         /* determine current SYSCLK (13'MHz or main oscillator) */
 121         target_read_u32(target, 0x40004050, &sysclk_ctrl);
 122
 123         if ((sysclk_ctrl & 1) == 0)
 124                 sysclk = lpc3180_info->osc_freq;
 125         else
 126                 sysclk = 13000;
 127
 128         /* determine selected HCLK source */
 129         target_read_u32(target, 0x40004044, &pwr_ctrl);
 130
 131         if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
 132         {
 133                 hclk = sysclk;
 134         }
 135         else
 136         {
 137                 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 138                 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
 139
 140                 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 141
 142                 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
 143                 {
 144                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 145                 }
 146                 else /* HCLK uses HCLK_PLL */
 147                 {
 148                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 149                 }
 150         }
 151
 152         LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
 153
 154         cycle = (1.0 / hclk) * 1000000.0;
 155
 156         return cycle;
 157 }
 158
 159 static int lpc3180_init(struct nand_device *nand)
 160 {
 161         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 162         struct target *target = lpc3180_info->target;
 163         int bus_width = nand->bus_width ? : 8;
 164         int address_cycles = nand->address_cycles ? : 3;
 165         int page_size = nand->page_size ? : 512;
 166
 167         if (target->state != TARGET_HALTED)
 168         {
 169                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 170                 return ERROR_NAND_OPERATION_FAILED;
 171         }
 172
 173         /* sanitize arguments */
 174         if ((bus_width != 8) && (bus_width != 16))
 175         {
 176                 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
 177                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 178         }
 179
 180         /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
 181          * would support 16 bit, too, so we just warn about this for now
 182          */
 183         if (bus_width == 16)
 184         {
 185                 LOG_WARNING("LPC3180 only supports 8 bit bus width");
 186         }
 187
 188         /* inform calling code about selected bus width */
 189         nand->bus_width = bus_width;
 190
 191         if ((address_cycles != 3) && (address_cycles != 4))
 192         {
 193                 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
 194                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 195         }
 196
 197         if ((page_size != 512) && (page_size != 2048))
 198         {
 199                 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
 200                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 201         }
 202
 203         /* select MLC controller if none is currently selected */
 204         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 205         {
 206                 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
 207                 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 208         }
 209
 210         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 211         {
 212                 uint32_t mlc_icr_value = 0x0;
 213                 float cycle;
 214                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 215
 216                 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
 217                 target_write_u32(target, 0x400040c8, 0x22);
 218
 219                 /* MLC_CEH = 0x0 (Force nCE assert) */
 220                 target_write_u32(target, 0x200b804c, 0x0);
 221
 222                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 223                 target_write_u32(target, 0x200b8044, 0xa25e);
 224
 225                 /* MLC_ICR = configuration */
 226                 if (lpc3180_info->sw_write_protection)
 227                         mlc_icr_value |= 0x8;
 228                 if (page_size == 2048)
 229                         mlc_icr_value |= 0x4;
 230                 if (address_cycles == 4)
 231                         mlc_icr_value |= 0x2;
 232                 if (bus_width == 16)
 233                         mlc_icr_value |= 0x1;
 234                 target_write_u32(target, 0x200b8030, mlc_icr_value);
 235
 236                 /* calculate NAND controller timings */
 237                 cycle = lpc3180_cycle_time(lpc3180_info);
 238
 239                 twp = ((40 / cycle) + 1);
 240                 twh = ((20 / cycle) + 1);
 241                 trp = ((30 / cycle) + 1);
 242                 treh = ((15 / cycle) + 1);
 243                 trhz = ((30 / cycle) + 1);
 244                 trbwb = ((100 / cycle) + 1);
 245                 tcea = ((45 / cycle) + 1);
 246
 247                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 248                 target_write_u32(target, 0x200b8044, 0xa25e);
 249
 250                 /* MLC_TIME_REG */
 251                 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
 252                         ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
 253                         ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
 254
 255                 lpc3180_reset(nand);
 256         }
 257         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 258         {
 259                 float cycle;
 260                 int r_setup, r_hold, r_width, r_rdy;
 261                 int w_setup, w_hold, w_width, w_rdy;
 262
 263                 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 264                 target_write_u32(target, 0x400040c8, 0x05);
 265
 266                 /* after reset set other registers of SLC so reset calling is here at the begining*/
 267                 lpc3180_reset(nand);
 268
 269                 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
 270                 target_write_u32(target, 0x20020014, 0x3e | (bus_width == 16) ? 1 : 0);
 271
 272                 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
 273                 target_write_u32(target, 0x20020020, 0x03);
 274
 275                 /* DMA configuration */
 276                 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
 277                 target_write_u32(target, 0x400040e8, 0x01);
 278                 /* DMACConfig = DMA enabled*/
 279                 target_write_u32(target, 0x31000030, 0x01);
 280
 281
 282                 /* calculate NAND controller timings */
 283                 cycle = lpc3180_cycle_time(lpc3180_info);
 284
 285                 r_setup = w_setup = 0;
 286                 r_hold = w_hold = 10 / cycle;
 287                 r_width = 30 / cycle;
 288                 w_width = 40 / cycle;
 289                 r_rdy = w_rdy = 100 / cycle;
 290
 291                 /* SLC_TAC: SLC timing arcs register */
 292                 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
 293                         ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) |  ((w_setup & 0xf) << 16) |
 294                         ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
 295
 296         }
 297
 298         return ERROR_OK;
 299 }
 300
 301 static int lpc3180_reset(struct nand_device *nand)
 302 {
 303         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 304         struct target *target = lpc3180_info->target;
 305
 306         if (target->state != TARGET_HALTED)
 307         {
 308                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 309                 return ERROR_NAND_OPERATION_FAILED;
 310         }
 311
 312         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 313         {
 314                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 315                 return ERROR_NAND_OPERATION_FAILED;
 316         }
 317         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 318         {
 319                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 320                 target_write_u32(target, 0x200b8000, 0xff);
 321
 322                 if (!lpc3180_controller_ready(nand, 100))
 323                 {
 324                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 325                         return ERROR_NAND_OPERATION_TIMEOUT;
 326                 }
 327         }
 328         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 329         {
 330                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 331                 target_write_u32(target, 0x20020010, 0x6);
 332
 333                 if (!lpc3180_controller_ready(nand, 100))
 334                 {
 335                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 336                         return ERROR_NAND_OPERATION_TIMEOUT;
 337                 }
 338         }
 339
 340         return ERROR_OK;
 341 }
 342
 343 static int lpc3180_command(struct nand_device *nand, uint8_t command)
 344 {
 345         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 346         struct target *target = lpc3180_info->target;
 347
 348         if (target->state != TARGET_HALTED)
 349         {
 350                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 351                 return ERROR_NAND_OPERATION_FAILED;
 352         }
 353
 354         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 355         {
 356                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 357                 return ERROR_NAND_OPERATION_FAILED;
 358         }
 359         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 360         {
 361                 /* MLC_CMD = command */
 362                 target_write_u32(target, 0x200b8000, command);
 363         }
 364         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 365         {
 366                 /* SLC_CMD = command */
 367                 target_write_u32(target, 0x20020008, command);
 368         }
 369
 370         return ERROR_OK;
 371 }
 372
 373 static int lpc3180_address(struct nand_device *nand, uint8_t address)
 374 {
 375         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 376         struct target *target = lpc3180_info->target;
 377
 378         if (target->state != TARGET_HALTED)
 379         {
 380                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 381                 return ERROR_NAND_OPERATION_FAILED;
 382         }
 383
 384         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 385         {
 386                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 387                 return ERROR_NAND_OPERATION_FAILED;
 388         }
 389         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 390         {
 391                 /* MLC_ADDR = address */
 392                 target_write_u32(target, 0x200b8004, address);
 393         }
 394         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 395         {
 396                 /* SLC_ADDR = address */
 397                 target_write_u32(target, 0x20020004, address);
 398         }
 399
 400         return ERROR_OK;
 401 }
 402
 403 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
 404 {
 405         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 406         struct target *target = lpc3180_info->target;
 407
 408         if (target->state != TARGET_HALTED)
 409         {
 410                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 411                 return ERROR_NAND_OPERATION_FAILED;
 412         }
 413
 414         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 415         {
 416                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 417                 return ERROR_NAND_OPERATION_FAILED;
 418         }
 419         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 420         {
 421                 /* MLC_DATA = data */
 422                 target_write_u32(target, 0x200b0000, data);
 423         }
 424         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 425         {
 426                 /* SLC_DATA = data */
 427                 target_write_u32(target, 0x20020000, data);
 428         }
 429
 430         return ERROR_OK;
 431 }
 432
 433 static int lpc3180_read_data(struct nand_device *nand, void *data)
 434 {
 435         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 436         struct target *target = lpc3180_info->target;
 437
 438         if (target->state != TARGET_HALTED)
 439         {
 440                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 441                 return ERROR_NAND_OPERATION_FAILED;
 442         }
 443
 444         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 445         {
 446                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 447                 return ERROR_NAND_OPERATION_FAILED;
 448         }
 449         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 450         {
 451                 /* data = MLC_DATA, use sized access */
 452                 if (nand->bus_width == 8)
 453                 {
 454                         uint8_t *data8 = data;
 455                         target_read_u8(target, 0x200b0000, data8);
 456                 }
 457                 else if (nand->bus_width == 16)
 458                 {
 459                         uint16_t *data16 = data;
 460                         target_read_u16(target, 0x200b0000, data16);
 461                 }
 462                 else
 463                 {
 464                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 465                         return ERROR_NAND_OPERATION_FAILED;
 466                 }
 467         }
 468         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 469         {
 470                 uint32_t data32;
 471
 472                 /* data = SLC_DATA, must use 32-bit access */
 473                 target_read_u32(target, 0x20020000, &data32);
 474
 475                 if (nand->bus_width == 8)
 476                 {
 477                         uint8_t *data8 = data;
 478                         *data8 = data32 & 0xff;
 479                 }
 480                 else if (nand->bus_width == 16)
 481                 {
 482                         uint16_t *data16 = data;
 483                         *data16 = data32 & 0xffff;
 484                 }
 485                 else
 486                 {
 487                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 488                         return ERROR_NAND_OPERATION_FAILED;
 489                 }
 490         }
 491
 492         return ERROR_OK;
 493 }
 494
 495 static int lpc3180_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 496 {
 497         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 498         struct target *target = lpc3180_info->target;
 499         int retval;
 500         uint8_t status;
 501         uint8_t *page_buffer;
 502
 503         if (target->state != TARGET_HALTED)
 504         {
 505                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 506                 return ERROR_NAND_OPERATION_FAILED;
 507         }
 508
 509         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 510         {
 511                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 512                 return ERROR_NAND_OPERATION_FAILED;
 513         }
 514         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 515         {
 516                 uint8_t *oob_buffer;
 517                 int quarter, num_quarters;
 518
 519                 if (!data && oob)
 520                 {
 521                         LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
 522                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 523                 }
 524
 525                 if (oob && (oob_size > 24))
 526                 {
 527                         LOG_ERROR("LPC3180 MLC controller can't write more "
 528                                 "than 6 bytes for each quarter's OOB data");
 529                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 530                 }
 531
 532                 if (data_size > (uint32_t)nand->page_size)
 533                 {
 534                         LOG_ERROR("data size exceeds page size");
 535                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 536                 }
 537
 538                 /* MLC_CMD = sequential input */
 539                 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 540
 541                 page_buffer = malloc(512);
 542                 oob_buffer = malloc(6);
 543
 544                 if (nand->page_size == 512)
 545                 {
 546                         /* MLC_ADDR = 0x0 (one column cycle) */
 547                         target_write_u32(target, 0x200b8004, 0x0);
 548
 549                         /* MLC_ADDR = row */
 550                         target_write_u32(target, 0x200b8004, page & 0xff);
 551                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 552
 553                         if (nand->address_cycles == 4)
 554                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 555                 }
 556                 else
 557                 {
 558                         /* MLC_ADDR = 0x0 (two column cycles) */
 559                         target_write_u32(target, 0x200b8004, 0x0);
 560                         target_write_u32(target, 0x200b8004, 0x0);
 561
 562                         /* MLC_ADDR = row */
 563                         target_write_u32(target, 0x200b8004, page & 0xff);
 564                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 565                 }
 566
 567                 /* when using the MLC controller, we have to treat a large page device
 568                  * as being made out of four quarters, each the size of a small page device
 569                  */
 570                 num_quarters = (nand->page_size == 2048) ? 4 : 1;
 571
 572                 for (quarter = 0; quarter < num_quarters; quarter++)
 573                 {
 574                         int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 575                         int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 576
 577                         memset(page_buffer, 0xff, 512);
 578                         if (data)
 579                         {
 580                                 memcpy(page_buffer, data, thisrun_data_size);
 581                                 data_size -= thisrun_data_size;
 582                                 data += thisrun_data_size;
 583                         }
 584
 585                         memset(oob_buffer, 0xff, 6);
 586                         if (oob)
 587                         {
 588                                 memcpy(oob_buffer, oob, thisrun_oob_size);
 589                                 oob_size -= thisrun_oob_size;
 590                                 oob += thisrun_oob_size;
 591                         }
 592
 593                         /* write MLC_ECC_ENC_REG to start encode cycle */
 594                         target_write_u32(target, 0x200b8008, 0x0);
 595
 596                         target_write_memory(target, 0x200a8000,
 597                                         4, 128, page_buffer);
 598                         target_write_memory(target, 0x200a8000,
 599                                         1, 6, oob_buffer);
 600
 601                         /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 602                         target_write_u32(target, 0x200b8010, 0x0);
 603
 604                         if (!lpc3180_controller_ready(nand, 1000))
 605                         {
 606                                 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
 607                                 return ERROR_NAND_OPERATION_FAILED;
 608                         }
 609                 }
 610
 611                 /* MLC_CMD = auto program command */
 612                 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 613
 614                 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
 615                 {
 616                         LOG_ERROR("couldn't read status");
 617                         return ERROR_NAND_OPERATION_FAILED;
 618                 }
 619
 620                 if (status & NAND_STATUS_FAIL)
 621                 {
 622                         LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
 623                         return ERROR_NAND_OPERATION_FAILED;
 624                 }
 625
 626                 free(page_buffer);
 627                 free(oob_buffer);
 628         }
 629         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 630         {
 631
 632                /**********************************************************************
 633                *     Write both SLC NAND flash page main area and spare area.
 634                *     Small page -
 635                *      ------------------------------------------
 636                *     |    512 bytes main   |   16 bytes spare   |
 637                *      ------------------------------------------
 638                *     Large page -
 639                *      ------------------------------------------
 640                *     |   2048 bytes main   |   64 bytes spare   |
 641                *      ------------------------------------------
 642                *     If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
 643                *     data is written to the 3rd word of the spare area. The ECC
 644                *     generated for the 2nd 256-byte data is written to the 4th word
 645                *     of the spare area. The ECC generated for the 3rd 256-byte data is
 646                *     written to the 7th word of the spare area. The ECC generated
 647                *     for the 4th 256-byte data is written to the 8th word of the
 648                *     spare area and so on.
 649                *
 650                **********************************************************************/
 651
 652                int i=0,target_mem_base;
 653                uint8_t *ecc_flash_buffer;
 654                struct working_area *pworking_area;
 655
 656
 657                 if(lpc3180_info->is_bulk){
 658
 659                     if (!data && oob){
 660                         /*if oob only mode is active original method is used as SLC controller hangs during DMA interworking. Anyway the code supports the oob only mode below. */
 661                 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
 662         }
 663                     retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
 664                     if (ERROR_OK != retval)
 665                         return retval;
 666
 667                     /* allocate a working area */
 668                     if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
 669                         LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
 670                         return ERROR_FLASH_OPERATION_FAILED;
 671                     }
 672                     if (target->working_area_phys%4){
 673                         LOG_ERROR("Reserve the physical target working area at word boundary");
 674                         return ERROR_FLASH_OPERATION_FAILED;
 675                     }
 676                     if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
 677                     {
 678                         LOG_ERROR("no working area specified, can't read LPC internal flash");
 679                         return ERROR_FLASH_OPERATION_FAILED;
 680                     }
 681                     target_mem_base = target->working_area_phys;
 682
 683
 684                     if (nand->page_size == 2048)
 685                     {
 686                         page_buffer = malloc(2048);
 687                     }
 688                     else
 689                     {
 690                         page_buffer = malloc(512);
 691                     }
 692
 693                     ecc_flash_buffer = malloc(64);
 694
 695                     /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA write to SLC, WIDTH = bus_width) */
 696                     target_write_u32(target, 0x20020014, 0x3c);
 697
 698                     if( data && !oob){
 699                         /* set DMA LLI-s in target memory and in DMA*/
 700                         for(i=0;i<nand->page_size/0x100;i++){
 701
 702                             int tmp;
 703                             /* -------LLI for 256 byte block---------*/
 704                             /* DMACC0SrcAddr = SRAM */
 705                             target_write_u32(target,target_mem_base+0+i*32,target_mem_base+DATA_OFFS+i*256 );
 706                             if(i==0) target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
 707                             /* DMACCxDestAddr = SLC_DMA_DATA */
 708                             target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
 709                             if(i==0)  target_write_u32(target,0x31000104,0x20020038 );
 710                             /* DMACCxLLI = next element */
 711                             tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
 712                             target_write_u32(target,target_mem_base+8+i*32, tmp );
 713                             if(i==0) target_write_u32(target,0x31000108, tmp );
 714                             /* DMACCxControl =  TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 715                             Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
 716                             Destination increment = 0, Terminal count interrupt enable bit = 0*/
 717                             target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 718                             if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 719
 720                             /* -------LLI for 3 byte ECC---------*/
 721                             /* DMACC0SrcAddr = SLC_ECC*/
 722                             target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
 723                             /* DMACCxDestAddr = SRAM */
 724                             target_write_u32(target,target_mem_base+20+i*32,target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4 );
 725                             /* DMACCxLLI = next element */
 726                                 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
 727                             target_write_u32(target,target_mem_base+24+i*32, tmp );
 728                             /* DMACCxControl =  TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
 729                             Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
 730                             Destination increment = 1, Terminal count interrupt enable bit = 0*/
 731                             target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
 732                         }
 733                     }
 734                     else if (data && oob){
 735                         /* -------LLI for 512 or 2048 bytes page---------*/
 736                         /* DMACC0SrcAddr = SRAM */
 737                         target_write_u32(target,target_mem_base,target_mem_base+DATA_OFFS );
 738                         target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
 739                         /* DMACCxDestAddr = SLC_DMA_DATA */
 740                         target_write_u32(target,target_mem_base+4,0x20020038 );
 741                         target_write_u32(target,0x31000104,0x20020038 );
 742                         /* DMACCxLLI = next element */
 743                         target_write_u32(target,target_mem_base+8, (target_mem_base+32)&0xfffffffc );
 744                         target_write_u32(target,0x31000108, (target_mem_base+32)&0xfffffffc );
 745                         /* DMACCxControl =  TransferSize =512 or 128, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 746                         Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
 747                         Destination increment = 0, Terminal count interrupt enable bit = 0*/
 748                         target_write_u32(target,target_mem_base+12,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 749                         target_write_u32(target,0x3100010c,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 750                         i = 1;
 751                     }
 752                     else if (!data && oob){
 753                         i = 0;
 754                     }
 755
 756                     /* -------LLI for spare area---------*/
 757                     /* DMACC0SrcAddr = SRAM*/
 758                     target_write_u32(target,target_mem_base+0+i*32,target_mem_base+SPARE_OFFS );
 759                     if(i==0) target_write_u32(target,0x31000100,target_mem_base+SPARE_OFFS );
 760                     /* DMACCxDestAddr = SLC_DMA_DATA */
 761                     target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
 762                     if(i==0) target_write_u32(target,0x31000104,0x20020038 );
 763                     /* DMACCxLLI = next element = NULL */
 764                     target_write_u32(target,target_mem_base+8+i*32, 0 );
 765                     if(i==0) target_write_u32(target,0x31000108,0 );
 766                     /* DMACCxControl =  TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 767                     Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
 768                     Destination increment = 0, Terminal count interrupt enable bit = 0*/
 769                     target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 770                     if(i==0) target_write_u32(target,0x3100010c,(nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31 );
 771
 772
 773
 774                     memset(ecc_flash_buffer, 0xff, 64);
 775                     if( oob ){
 776                         memcpy(ecc_flash_buffer,oob, oob_size);
 777                     }
 778                     target_write_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
 779
 780                     if (data){
 781                         memset(page_buffer, 0xff, nand->page_size == 2048?2048:512);
 782                         memcpy(page_buffer,data, data_size);
 783                         target_write_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
 784                     }
 785
 786                     free(page_buffer);
 787                     free(ecc_flash_buffer);
 788
 789                     /* Enable DMA after channel set up !
 790                         LLI only works when DMA is the flow controller!
 791                     */
 792                     /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
 793                     target_write_u32(target,0x31000110,   1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
 794
 795
 796
 797                      /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
 798                      target_write_u32(target, 0x20020010, 0x3);
 799
 800                     /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
 801                      target_write_u32(target, 0x20020028, 2);
 802
 803                     /* SLC_TC */
 804                     if (!data && oob)
 805                        target_write_u32(target, 0x20020030,  (nand->page_size==2048?0x10:0x04));
 806                     else
 807                        target_write_u32(target, 0x20020030,  (nand->page_size==2048?0x840:0x210));
 808
 809                     nand_write_finish(nand);
 810
 811
 812                     if (!lpc3180_tc_ready(nand, 1000))
 813                     {
 814                         LOG_ERROR("timeout while waiting for completion of DMA");
 815                         return ERROR_NAND_OPERATION_FAILED;
 816                     }
 817
 818                 target_free_working_area(target,pworking_area);
 819
 820                 LOG_INFO("Page =  0x%" PRIx32 " was written.",page);
 821
 822                 }
 823                 else
 824                     return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
 825         }
 826
 827
 828         return ERROR_OK;
 829 }
 830
 831 static int lpc3180_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 832 {
 833         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 834         struct target *target = lpc3180_info->target;
 835         uint8_t *page_buffer;
 836
 837         if (target->state != TARGET_HALTED)
 838         {
 839                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 840                 return ERROR_NAND_OPERATION_FAILED;
 841         }
 842
 843         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 844         {
 845                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 846                 return ERROR_NAND_OPERATION_FAILED;
 847         }
 848         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 849         {
 850                 uint8_t *oob_buffer;
 851                 uint32_t page_bytes_done = 0;
 852                 uint32_t oob_bytes_done = 0;
 853                 uint32_t mlc_isr;
 854
 855 #if 0
 856                 if (oob && (oob_size > 6))
 857                 {
 858                         LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
 859                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 860                 }
 861 #endif
 862
 863                 if (data_size > (uint32_t)nand->page_size)
 864                 {
 865                         LOG_ERROR("data size exceeds page size");
 866                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 867                 }
 868
 869                 if (nand->page_size == 2048)
 870                 {
 871                         page_buffer = malloc(2048);
 872                         oob_buffer = malloc(64);
 873                 }
 874                 else
 875                 {
 876                         page_buffer = malloc(512);
 877                         oob_buffer = malloc(16);
 878                 }
 879
 880                 if (!data && oob)
 881                 {
 882                         /* MLC_CMD = Read OOB
 883                          * we can use the READOOB command on both small and large page devices,
 884                          * as the controller translates the 0x50 command to a 0x0 with appropriate
 885                          * positioning of the serial buffer read pointer
 886                          */
 887                         target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
 888                 }
 889                 else
 890                 {
 891                         /* MLC_CMD = Read0 */
 892                         target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
 893                 }
 894
 895                 if (nand->page_size == 512)
 896                 {
 897                         /* small page device */
 898                         /* MLC_ADDR = 0x0 (one column cycle) */
 899                         target_write_u32(target, 0x200b8004, 0x0);
 900
 901                         /* MLC_ADDR = row */
 902                         target_write_u32(target, 0x200b8004, page & 0xff);
 903                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 904
 905                         if (nand->address_cycles == 4)
 906                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 907                 }
 908                 else
 909                 {
 910                         /* large page device */
 911                         /* MLC_ADDR = 0x0 (two column cycles) */
 912                         target_write_u32(target, 0x200b8004, 0x0);
 913                         target_write_u32(target, 0x200b8004, 0x0);
 914
 915                         /* MLC_ADDR = row */
 916                         target_write_u32(target, 0x200b8004, page & 0xff);
 917                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 918
 919                         /* MLC_CMD = Read Start */
 920                         target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
 921                 }
 922
 923                 while (page_bytes_done < (uint32_t)nand->page_size)
 924                 {
 925                         /* MLC_ECC_AUTO_DEC_REG = dummy */
 926                         target_write_u32(target, 0x200b8014, 0xaa55aa55);
 927
 928                         if (!lpc3180_controller_ready(nand, 1000))
 929                         {
 930                                 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
 931                                 return ERROR_NAND_OPERATION_FAILED;
 932                         }
 933
 934                         target_read_u32(target, 0x200b8048, &mlc_isr);
 935
 936                         if (mlc_isr & 0x8)
 937                         {
 938                                 if (mlc_isr & 0x40)
 939                                 {
 940                                         LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr);
 941                                         return ERROR_NAND_OPERATION_FAILED;
 942                                 }
 943
 944                                 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr & 0x30) >> 4) + 1)));
 945                         }
 946
 947                         if (data)
 948                         {
 949                                 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
 950                         }
 951
 952                         if (oob)
 953                         {
 954                                 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
 955                         }
 956
 957                         page_bytes_done += 512;
 958                         oob_bytes_done += 16;
 959                 }
 960
 961                 if (data)
 962                         memcpy(data, page_buffer, data_size);
 963
 964                 if (oob)
 965                         memcpy(oob, oob_buffer, oob_size);
 966
 967                 free(page_buffer);
 968                 free(oob_buffer);
 969         }
 970         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 971         {
 972
 973            /**********************************************************************
 974            *     Read both SLC NAND flash page main area and spare area.
 975            *     Small page -
 976            *      ------------------------------------------
 977            *     |    512 bytes main   |   16 bytes spare   |
 978            *      ------------------------------------------
 979            *     Large page -
 980            *      ------------------------------------------
 981            *     |   2048 bytes main   |   64 bytes spare   |
 982            *      ------------------------------------------
 983            *     If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
 984            *     data is compared with the 3rd word of the spare area. The ECC
 985            *     generated for the 2nd 256-byte data is compared with the 4th word
 986            *     of the spare area. The ECC generated for the 3rd 256-byte data is
 987            *     compared with the 7th word of the spare area. The ECC generated
 988            *     for the 4th 256-byte data is compared with the 8th word of the
 989            *     spare area and so on.
 990            *
 991            **********************************************************************/
 992
 993            int retval,i,target_mem_base;
 994            uint8_t *ecc_hw_buffer;
 995            uint8_t *ecc_flash_buffer;
 996            struct working_area *pworking_area;
 997
 998            if(lpc3180_info->is_bulk){
 999
1000                 /* read always the data and also oob areas*/
1001
1002                 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1003                 if (ERROR_OK != retval)
1004                         return retval;
1005
1006                 /* allocate a working area */
1007                 if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
1008                     LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
1009                     return ERROR_FLASH_OPERATION_FAILED;
1010                 }
1011                 if (target->working_area_phys%4){
1012                     LOG_ERROR("Reserve the physical target working area at word boundary");
1013                     return ERROR_FLASH_OPERATION_FAILED;
1014                 }
1015                 if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
1016                 {
1017                     LOG_ERROR("no working area specified, can't read LPC internal flash");
1018                     return ERROR_FLASH_OPERATION_FAILED;
1019                 }
1020                 target_mem_base = target->working_area_phys;
1021
1022                 if (nand->page_size == 2048)
1023                 {
1024                     page_buffer = malloc(2048);
1025                 }
1026                 else
1027                 {
1028                     page_buffer = malloc(512);
1029                 }
1030
1031                 ecc_hw_buffer = malloc(32);
1032                 ecc_flash_buffer = malloc(64);
1033
1034                 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
1035                 target_write_u32(target, 0x20020014, 0x3e);
1036
1037                 /* set DMA LLI-s in target memory and in DMA*/
1038                 for(i=0;i<nand->page_size/0x100;i++){
1039                     int tmp;
1040                     /* -------LLI for 256 byte block---------*/
1041                     /* DMACC0SrcAddr = SLC_DMA_DATA*/
1042                     target_write_u32(target,target_mem_base+0+i*32,0x20020038 );
1043                     if(i==0) target_write_u32(target,0x31000100,0x20020038 );
1044                     /* DMACCxDestAddr = SRAM */
1045                     target_write_u32(target,target_mem_base+4+i*32,target_mem_base+DATA_OFFS+i*256 );
1046                     if(i==0)  target_write_u32(target,0x31000104,target_mem_base+DATA_OFFS );
1047                     /* DMACCxLLI = next element */
1048                     tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
1049                     target_write_u32(target,target_mem_base+8+i*32, tmp );
1050                     if(i==0) target_write_u32(target,0x31000108, tmp );
1051                     /* DMACCxControl =  TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1052                     Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1053                     Destination increment = 1, Terminal count interrupt enable bit = 0*/
1054                     target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1055                     if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1056
1057                     /* -------LLI for 3 byte ECC---------*/
1058                     /* DMACC0SrcAddr = SLC_ECC*/
1059                     target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
1060                     /* DMACCxDestAddr = SRAM */
1061                     target_write_u32(target,target_mem_base+20+i*32,target_mem_base+ECC_OFFS+i*4 );
1062                     /* DMACCxLLI = next element */
1063                     tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
1064                     target_write_u32(target,target_mem_base+24+i*32, tmp );
1065                     /* DMACCxControl =  TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
1066                     Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1067                     Destination increment = 1, Terminal count interrupt enable bit = 0*/
1068                     target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1069
1070
1071                 }
1072
1073                 /* -------LLI for spare area---------*/
1074                 /* DMACC0SrcAddr = SLC_DMA_DATA*/
1075                 target_write_u32(target,target_mem_base+0+i*32,0x20020038 );
1076                 /* DMACCxDestAddr = SRAM */
1077                 target_write_u32(target,target_mem_base+4+i*32,target_mem_base+SPARE_OFFS );
1078                 /* DMACCxLLI = next element = NULL */
1079                 target_write_u32(target,target_mem_base+8+i*32, 0 );
1080                 /* DMACCxControl =  TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1081                 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1082                 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1083                 target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1084
1085                 /* Enable DMA after channel set up !
1086                     LLI only works when DMA is the flow controller!
1087                 */
1088                 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1089                 target_write_u32(target,0x31000110,   1 | 1<<1 | 1<<6 |  2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1090
1091
1092                  /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1093                 target_write_u32(target, 0x20020010, 0x3);
1094
1095                 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1096                 target_write_u32(target, 0x20020028, 2);
1097
1098                 /* SLC_TC */
1099                 target_write_u32(target, 0x20020030,  (nand->page_size==2048?0x840:0x210));
1100
1101                 if (!lpc3180_tc_ready(nand, 1000))
1102                 {
1103                     LOG_ERROR("timeout while waiting for completion of DMA");
1104                     free(page_buffer);
1105                     free(ecc_hw_buffer);
1106                     free(ecc_flash_buffer);
1107                     target_free_working_area(target,pworking_area);
1108                     return ERROR_NAND_OPERATION_FAILED;
1109                 }
1110
1111                 if (data){
1112                     target_read_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
1113                     memcpy(data, page_buffer, data_size);
1114
1115                     LOG_INFO("Page =  0x%" PRIx32 " was read.",page);
1116
1117                     /* check hw generated ECC for each 256 bytes block with the saved ECC in flash spare area*/
1118                     int idx = nand->page_size/0x200 ;
1119                     target_read_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
1120                     target_read_memory(target, target_mem_base+ECC_OFFS, 4, 8, ecc_hw_buffer);
1121                     for(i=0;i<idx;i++){
1122                         if( (0x00ffffff&*(uint32_t *)(void *)(ecc_hw_buffer+i*8)) != (0x00ffffff&*(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)) )
1123                             LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+1,page);
1124                         if( (0x00ffffff&*(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) != (0x00ffffff&*(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)) )
1125                             LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+2,page);
1126                     }
1127                 }
1128
1129                 if (oob)
1130                     memcpy(oob, ecc_flash_buffer, oob_size);
1131
1132                 free(page_buffer);
1133                 free(ecc_hw_buffer);
1134                 free(ecc_flash_buffer);
1135
1136                 target_free_working_area(target,pworking_area);
1137
1138             }
1139             else
1140                 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
1141         }
1142
1143         return ERROR_OK;
1144 }
1145
1146 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
1147 {
1148         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1149         struct target *target = lpc3180_info->target;
1150
1151         if (target->state != TARGET_HALTED)
1152         {
1153                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1154                 return ERROR_NAND_OPERATION_FAILED;
1155         }
1156
1157         LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
1158
1159         do
1160         {
1161                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1162                 {
1163                         uint8_t status;
1164
1165                         /* Read MLC_ISR, wait for controller to become ready */
1166                         target_read_u8(target, 0x200b8048, &status);
1167
1168                         if (status & 2) {
1169                                 LOG_DEBUG("lpc3180_controller_ready count=%d",
1170                                                 timeout);
1171                                 return 1;
1172                         }
1173                 }
1174                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1175                 {
1176                         uint32_t status;
1177
1178                         /* Read SLC_STAT and check READY bit */
1179                         target_read_u32(target, 0x20020018, &status);
1180
1181                         if (status & 1) {
1182                                 LOG_DEBUG("lpc3180_controller_ready count=%d",
1183                                                 timeout);
1184                                 return 1;
1185                         }
1186                 }
1187
1188                 alive_sleep(1);
1189         } while (timeout-- > 0);
1190
1191         return 0;
1192 }
1193
1194 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
1195 {
1196         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1197         struct target *target = lpc3180_info->target;
1198
1199         if (target->state != TARGET_HALTED)
1200         {
1201                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1202                 return ERROR_NAND_OPERATION_FAILED;
1203         }
1204
1205         LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
1206
1207         do
1208         {
1209                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1210                 {
1211                         uint8_t status = 0x0;
1212
1213                         /* Read MLC_ISR, wait for NAND flash device to become ready */
1214                         target_read_u8(target, 0x200b8048, &status);
1215
1216                         if (status & 1) {
1217                                 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1218                                                 timeout);
1219                                 return 1;
1220                         }
1221                 }
1222                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1223                 {
1224                         uint32_t status = 0x0;
1225
1226                         /* Read SLC_STAT and check READY bit */
1227                         target_read_u32(target, 0x20020018, &status);
1228
1229                         if (status & 1) {
1230                                 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1231                                                 timeout);
1232                                 return 1;
1233                         }
1234                 }
1235
1236                 alive_sleep(1);
1237         } while (timeout-- > 0);
1238
1239         return 0;
1240 }
1241
1242 static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
1243 {
1244         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1245         struct target *target = lpc3180_info->target;
1246
1247         if (target->state != TARGET_HALTED)
1248         {
1249                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1250                 return ERROR_NAND_OPERATION_FAILED;
1251         }
1252
1253       LOG_DEBUG("lpc3180_tc_ready count start=%d",
1254                           timeout);
1255
1256         do
1257         {
1258                 if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1259                 {
1260                    uint32_t status = 0x0;
1261                         /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1262                         target_read_u32(target, 0x2002001c, &status);
1263
1264                         if (status & 2){
1265                         LOG_DEBUG("lpc3180_tc_ready count=%d",
1266                                             timeout);
1267                         return 1;
1268                     }
1269                 }
1270
1271                 alive_sleep(1);
1272         } while (timeout-- > 0);
1273
1274         return 0;
1275 }
1276
1277
1278 COMMAND_HANDLER(handle_lpc3180_select_command)
1279 {
1280         struct lpc3180_nand_controller *lpc3180_info = NULL;
1281         char *selected[] =
1282         {
1283                 "no", "mlc", "slc"
1284         };
1285
1286         if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1287         {
1288                 return ERROR_COMMAND_SYNTAX_ERROR;
1289         }
1290
1291         unsigned num;
1292         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1293         struct nand_device *nand = get_nand_device_by_num(num);
1294         if (!nand)
1295         {
1296                 command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
1297                 return ERROR_OK;
1298         }
1299
1300         lpc3180_info = nand->controller_priv;
1301
1302         if (CMD_ARGC >= 2)
1303         {
1304                 if (strcmp(CMD_ARGV[1], "mlc") == 0)
1305                 {
1306                         lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
1307                 }
1308                 else if (strcmp(CMD_ARGV[1], "slc") == 0)
1309                 {
1310                         lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
1311                    if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0){
1312                         lpc3180_info->is_bulk = 1;
1313                    }
1314                    else{
1315                         lpc3180_info->is_bulk = 0;
1316                    }
1317                 }
1318                 else
1319                 {
1320                         return ERROR_COMMAND_SYNTAX_ERROR;
1321                 }
1322         }
1323
1324       if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1325         command_print(CMD_CTX, "%s controller selected", selected[lpc3180_info->selected_controller]);
1326       else{
1327             command_print(CMD_CTX, lpc3180_info->is_bulk?"%s controller selected bulk mode is avaliable":"%s controller selected bulk mode is not avaliable", selected[lpc3180_info->selected_controller]);
1328       }
1329
1330
1331         return ERROR_OK;
1332 }
1333
1334 static const struct command_registration lpc3180_exec_command_handlers[] = {
1335         {
1336                 .name = "select",
1337                 .handler = handle_lpc3180_select_command,
1338                 .mode = COMMAND_EXEC,
1339                 .help = "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1340                 .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
1341         },
1342         COMMAND_REGISTRATION_DONE
1343 };
1344 static const struct command_registration lpc3180_command_handler[] = {
1345         {
1346                 .name = "lpc3180",
1347                 .mode = COMMAND_ANY,
1348                 .help = "LPC3180 NAND flash controller commands",
1349                 .chain = lpc3180_exec_command_handlers,
1350         },
1351         COMMAND_REGISTRATION_DONE
1352 };
1353
1354 struct nand_flash_controller lpc3180_nand_controller = {
1355         .name = "lpc3180",
1356         .commands = lpc3180_command_handler,
1357         .nand_device_command = lpc3180_nand_device_command,
1358         .init = lpc3180_init,
1359         .reset = lpc3180_reset,
1360         .command = lpc3180_command,
1361         .address = lpc3180_address,
1362         .write_data = lpc3180_write_data,
1363         .read_data = lpc3180_read_data,
1364         .write_page = lpc3180_write_page,
1365         .read_page = lpc3180_read_page,
1366         .controller_ready = lpc3180_controller_ready,
1367         .nand_ready = lpc3180_nand_ready,
1368 };