1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
26 * Freescale iMX OpenOCD NAND Flash controller support.
27 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; mxc_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
46 #include <target/target.h>
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
53 #undef _MXC_PRINT_STAT
54 /* #define _MXC_PRINT_STAT */
56 static const char target_not_halted_err_msg[] =
57 "target must be halted to use mxc NAND flash controller";
58 static const char data_block_size_err_msg[] =
59 "minimal granularity is one half-word, %" PRId32 " is incorrect";
60 static const char sram_buffer_bounds_err_msg[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
62 static const char get_status_register_err_msg[] = "can't get NAND status";
63 static uint32_t in_sram_address;
64 static unsigned char sign_of_sequental_byte_read;
66 static int initialize_nf_controller(struct nand_device *nand);
67 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
68 static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value);
69 static int poll_for_complete_op(struct target *target, const char *text);
70 static int validate_target_state(struct nand_device *nand);
71 static int do_data_output(struct nand_device *nand);
73 static int mxc_command(struct nand_device *nand, uint8_t command);
74 static int mxc_address(struct nand_device *nand, uint8_t address);
76 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
78 struct mxc_nf_controller *mxc_nf_info;
82 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
83 if (mxc_nf_info == NULL) {
84 LOG_ERROR("no memory for nand controller");
87 nand->controller_priv = mxc_nf_info;
90 LOG_ERROR("use \"nand device mxc target noecc|hwecc\"");
95 * check hwecc requirements
97 hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
98 if (hwecc_needed == 0)
99 mxc_nf_info->flags.hw_ecc_enabled = 1;
101 mxc_nf_info->flags.hw_ecc_enabled = 0;
103 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
104 mxc_nf_info->fin = MXC_NF_FIN_NONE;
105 mxc_nf_info->flags.target_little_endian =
106 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
109 * testing host endianness
112 if (*(char *) &x == 1)
113 mxc_nf_info->flags.host_little_endian = 1;
115 mxc_nf_info->flags.host_little_endian = 0;
119 static int mxc_init(struct nand_device *nand)
121 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
122 struct target *target = nand->target;
124 int validate_target_result;
125 uint16_t buffsize_register_content;
126 uint32_t pcsr_register_content;
128 uint16_t nand_status_content;
130 * validate target state
132 validate_target_result = validate_target_state(nand);
133 if (validate_target_result != ERROR_OK)
134 return validate_target_result;
136 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
137 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
139 target_read_u32(target, MXC_FMCR, &pcsr_register_content);
140 if (!nand->bus_width) {
141 /* bus_width not yet defined. Read it from MXC_FMCR */
143 (pcsr_register_content & MXC_FMCR_NF_16BIT_SEL) ? 16 : 8;
145 /* bus_width forced in soft. Sync it to MXC_FMCR */
146 pcsr_register_content |=
147 ((nand->bus_width == 16) ? MXC_FMCR_NF_16BIT_SEL : 0x00000000);
148 target_write_u32(target, MXC_FMCR, pcsr_register_content);
150 if (nand->bus_width == 16)
151 LOG_DEBUG("MXC_NF : bus is 16-bit width");
153 LOG_DEBUG("MXC_NF : bus is 8-bit width");
155 if (!nand->page_size) {
156 nand->page_size = (pcsr_register_content & MXC_FMCR_NF_FMS) ? 2048 : 512;
158 pcsr_register_content |=
159 ((nand->page_size == 2048) ? MXC_FMCR_NF_FMS : 0x00000000);
160 target_write_u32(target, MXC_FMCR, pcsr_register_content);
162 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
163 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
164 "pagesize 2048 is incompatible with it");
166 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
169 initialize_nf_controller(nand);
172 retval |= mxc_command(nand, NAND_CMD_STATUS);
173 retval |= mxc_address(nand, 0x00);
174 retval |= do_data_output(nand);
175 if (retval != ERROR_OK) {
176 LOG_ERROR(get_status_register_err_msg);
179 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
180 if (!(nand_status_content & 0x0080)) {
181 LOG_INFO("NAND read-only");
182 mxc_nf_info->flags.nand_readonly = 1;
184 mxc_nf_info->flags.nand_readonly = 0;
189 static int mxc_read_data(struct nand_device *nand, void *data)
191 struct target *target = nand->target;
192 int validate_target_result;
193 int try_data_output_from_nand_chip;
195 * validate target state
197 validate_target_result = validate_target_state(nand);
198 if (validate_target_result != ERROR_OK)
199 return validate_target_result;
202 * get data from nand chip
204 try_data_output_from_nand_chip = do_data_output(nand);
205 if (try_data_output_from_nand_chip != ERROR_OK) {
206 LOG_ERROR("mxc_read_data : read data failed : '%x'",
207 try_data_output_from_nand_chip);
208 return try_data_output_from_nand_chip;
211 if (nand->bus_width == 16)
212 get_next_halfword_from_sram_buffer(target, data);
214 get_next_byte_from_sram_buffer(target, data);
219 static int mxc_write_data(struct nand_device *nand, uint16_t data)
221 LOG_ERROR("write_data() not implemented");
222 return ERROR_NAND_OPERATION_FAILED;
225 static int mxc_reset(struct nand_device *nand)
228 * validate target state
230 int validate_target_result;
231 validate_target_result = validate_target_state(nand);
232 if (validate_target_result != ERROR_OK)
233 return validate_target_result;
234 initialize_nf_controller(nand);
238 static int mxc_command(struct nand_device *nand, uint8_t command)
240 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
241 struct target *target = nand->target;
242 int validate_target_result;
245 * validate target state
247 validate_target_result = validate_target_state(nand);
248 if (validate_target_result != ERROR_OK)
249 return validate_target_result;
252 case NAND_CMD_READOOB:
253 command = NAND_CMD_READ0;
254 /* set read point for data_read() and read_block_data() to
255 * spare area in SRAM buffer
257 in_sram_address = MXC_NF_SPARE_BUFFER0;
260 command = NAND_CMD_READ0;
262 * offset == one half of page size
264 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
267 in_sram_address = MXC_NF_MAIN_BUFFER0;
271 target_write_u16(target, MXC_NF_FCMD, command);
273 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
275 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
276 poll_result = poll_for_complete_op(target, "command");
277 if (poll_result != ERROR_OK)
280 * reset cursor to begin of the buffer
282 sign_of_sequental_byte_read = 0;
283 /* Handle special read command and adjust NF_CFG2(FDO) */
285 case NAND_CMD_READID:
286 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
287 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
289 case NAND_CMD_STATUS:
290 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
291 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
292 target_write_u16 (target, MXC_NF_BUFADDR, 0);
296 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
297 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
300 /* Ohter command use the default 'One page data out' FDO */
301 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
307 static int mxc_address(struct nand_device *nand, uint8_t address)
309 struct target *target = nand->target;
310 int validate_target_result;
313 * validate target state
315 validate_target_result = validate_target_state(nand);
316 if (validate_target_result != ERROR_OK)
317 return validate_target_result;
319 target_write_u16(target, MXC_NF_FADDR, address);
321 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
323 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
324 poll_result = poll_for_complete_op(target, "address");
325 if (poll_result != ERROR_OK)
331 static int mxc_nand_ready(struct nand_device *nand, int tout)
333 uint16_t poll_complete_status;
334 struct target *target = nand->target;
335 int validate_target_result;
338 * validate target state
340 validate_target_result = validate_target_state(nand);
341 if (validate_target_result != ERROR_OK)
342 return validate_target_result;
345 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
346 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
355 static int mxc_write_page(struct nand_device *nand, uint32_t page,
356 uint8_t *data, uint32_t data_size,
357 uint8_t *oob, uint32_t oob_size)
359 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
360 struct target *target = nand->target;
362 uint16_t nand_status_content;
363 uint16_t swap1, swap2, new_swap1;
366 LOG_ERROR(data_block_size_err_msg, data_size);
367 return ERROR_NAND_OPERATION_FAILED;
370 LOG_ERROR(data_block_size_err_msg, oob_size);
371 return ERROR_NAND_OPERATION_FAILED;
374 LOG_ERROR("nothing to program");
375 return ERROR_NAND_OPERATION_FAILED;
378 * validate target state
380 retval = validate_target_state(nand);
381 if (retval != ERROR_OK)
384 in_sram_address = MXC_NF_MAIN_BUFFER0;
385 sign_of_sequental_byte_read = 0;
387 retval |= mxc_command(nand, NAND_CMD_SEQIN);
388 retval |= mxc_address(nand, 0); /* col */
389 retval |= mxc_address(nand, 0); /* col */
390 retval |= mxc_address(nand, page & 0xff); /* page address */
391 retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
392 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
394 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
396 if (mxc_nf_info->flags.hw_ecc_enabled) {
398 * part of spare block will be overrided by hardware
401 LOG_DEBUG("part of spare block will be overrided "
402 "by hardware ECC generator");
404 target_write_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
406 /* BI-swap - work-around of mxc NFC for NAND device with page == 2kb */
407 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
409 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
410 return ERROR_NAND_OPERATION_FAILED;
412 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
413 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
414 swap2 = (swap1 << 8) | (swap2 & 0xFF);
416 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
417 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
419 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
421 target_write_u16(target, MXC_NF_BUFADDR, 0);
422 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
423 poll_result = poll_for_complete_op(target, "data input");
424 if (poll_result != ERROR_OK)
427 target_write_u16(target, MXC_NF_BUFADDR, 1);
428 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
429 poll_result = poll_for_complete_op(target, "data input");
430 if (poll_result != ERROR_OK)
433 target_write_u16(target, MXC_NF_BUFADDR, 2);
434 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
435 poll_result = poll_for_complete_op(target, "data input");
436 if (poll_result != ERROR_OK)
439 target_write_u16(target, MXC_NF_BUFADDR, 3);
440 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
441 poll_result = poll_for_complete_op(target, "data input");
442 if (poll_result != ERROR_OK)
445 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
446 if (retval != ERROR_OK)
450 * check status register
453 retval |= mxc_command(nand, NAND_CMD_STATUS);
454 target_write_u16 (target, MXC_NF_BUFADDR, 0);
455 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
456 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
457 retval |= do_data_output(nand);
458 if (retval != ERROR_OK) {
459 LOG_ERROR(get_status_register_err_msg);
462 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
463 if (nand_status_content & 0x0001) {
465 * page not correctly written
467 return ERROR_NAND_OPERATION_FAILED;
469 #ifdef _MXC_PRINT_STAT
470 LOG_INFO("%d bytes newly written", data_size);
475 static int mxc_read_page(struct nand_device *nand, uint32_t page,
476 uint8_t *data, uint32_t data_size,
477 uint8_t *oob, uint32_t oob_size)
479 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
480 struct target *target = nand->target;
482 uint16_t swap1, swap2, new_swap1;
485 LOG_ERROR(data_block_size_err_msg, data_size);
486 return ERROR_NAND_OPERATION_FAILED;
489 LOG_ERROR(data_block_size_err_msg, oob_size);
490 return ERROR_NAND_OPERATION_FAILED;
494 * validate target state
496 retval = validate_target_state(nand);
497 if (retval != ERROR_OK) {
500 /* Reset address_cycles before mxc_command ?? */
501 retval = mxc_command(nand, NAND_CMD_READ0);
502 if (retval != ERROR_OK) return retval;
503 retval = mxc_address(nand, 0); /* col */
504 if (retval != ERROR_OK) return retval;
505 retval = mxc_address(nand, 0); /* col */
506 if (retval != ERROR_OK) return retval;
507 retval = mxc_address(nand, page & 0xff); /* page address */
508 if (retval != ERROR_OK) return retval;
509 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
510 if (retval != ERROR_OK) return retval;
511 retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
512 if (retval != ERROR_OK) return retval;
513 retval = mxc_command(nand, NAND_CMD_READSTART);
514 if (retval != ERROR_OK) return retval;
516 target_write_u16(target, MXC_NF_BUFADDR, 0);
517 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
518 retval = do_data_output(nand);
519 if (retval != ERROR_OK) {
520 LOG_ERROR("MXC_NF : Error reading page 0");
523 /* Test nand page size to know how much MAIN_BUFFER must be written */
524 target_write_u16(target, MXC_NF_BUFADDR, 1);
525 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
526 retval = do_data_output(nand);
527 if (retval != ERROR_OK) {
528 LOG_ERROR("MXC_NF : Error reading page 1");
531 target_write_u16(target, MXC_NF_BUFADDR, 2);
532 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
533 retval = do_data_output(nand);
534 if (retval != ERROR_OK) {
535 LOG_ERROR("MXC_NF : Error reading page 2");
538 target_write_u16(target, MXC_NF_BUFADDR, 3);
539 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
540 retval = do_data_output(nand);
541 if (retval != ERROR_OK) {
542 LOG_ERROR("MXC_NF : Error reading page 3");
545 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
546 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
547 target_read_u16(target, MXC_NF_SPARE_BUFFER3 + 4, &swap2);
548 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
549 swap2 = (swap1 << 8) | (swap2 & 0xFF);
550 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
551 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
554 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
556 target_read_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
558 #ifdef _MXC_PRINT_STAT
560 /* When Operation Status is read (when page is erased),
561 * this function is used but data_size is null.
563 LOG_INFO("%d bytes newly read", data_size);
569 static int initialize_nf_controller(struct nand_device *nand)
571 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
572 struct target *target = nand->target;
576 * resets NAND flash controller in zero time ? I dont know.
578 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
579 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
580 if (target->endianness == TARGET_BIG_ENDIAN) {
581 LOG_DEBUG("MXC_NF : work in Big Endian mode");
582 work_mode |= MXC_NF_BIT_BE_EN;
584 LOG_DEBUG("MXC_NF : work in Little Endian mode");
586 if (mxc_nf_info->flags.hw_ecc_enabled) {
587 LOG_DEBUG("MXC_NF : work with ECC mode");
588 work_mode |= MXC_NF_BIT_ECC_EN;
590 LOG_DEBUG("MXC_NF : work without ECC mode");
592 target_write_u16(target, MXC_NF_CFG1, work_mode);
594 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
596 target_write_u16(target, MXC_NF_BUFCFG, 2);
597 target_read_u16(target, MXC_NF_FWP, &temp);
598 if ((temp & 0x0007) == 1) {
599 LOG_ERROR("NAND flash is tight-locked, reset needed");
604 * unlock NAND flash for write
606 target_write_u16(target, MXC_NF_FWP, 4);
607 target_write_u16(target, MXC_NF_LOCKSTART, 0x0000);
608 target_write_u16(target, MXC_NF_LOCKEND, 0xFFFF);
610 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
612 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
614 * address of SRAM buffer
616 in_sram_address = MXC_NF_MAIN_BUFFER0;
617 sign_of_sequental_byte_read = 0;
621 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
623 static uint8_t even_byte = 0;
628 if (sign_of_sequental_byte_read == 0)
631 if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
632 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
634 sign_of_sequental_byte_read = 0;
636 return ERROR_NAND_OPERATION_FAILED;
638 target_read_u16(target, in_sram_address, &temp);
642 in_sram_address += 2;
644 *value = temp & 0xff;
648 sign_of_sequental_byte_read = 1;
652 static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value)
654 if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
655 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
657 return ERROR_NAND_OPERATION_FAILED;
659 target_read_u16(target, in_sram_address, value);
660 in_sram_address += 2;
665 static int poll_for_complete_op(struct target *target, const char *text)
667 uint16_t poll_complete_status;
668 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
669 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
670 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
675 if (!(poll_complete_status & MXC_NF_BIT_OP_DONE)) {
676 LOG_ERROR("%s sending timeout", text);
677 return ERROR_NAND_OPERATION_FAILED;
682 static int validate_target_state(struct nand_device *nand)
684 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
685 struct target *target = nand->target;
687 if (target->state != TARGET_HALTED) {
688 LOG_ERROR(target_not_halted_err_msg);
689 return ERROR_NAND_OPERATION_FAILED;
692 if (mxc_nf_info->flags.target_little_endian !=
693 (target->endianness == TARGET_LITTLE_ENDIAN)) {
695 * endianness changed after NAND controller probed
697 return ERROR_NAND_OPERATION_FAILED;
702 static int do_data_output(struct nand_device *nand)
704 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
705 struct target *target = nand->target;
708 switch (mxc_nf_info->fin) {
709 case MXC_NF_FIN_DATAOUT:
711 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
713 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
714 poll_result = poll_for_complete_op(target, "data output");
715 if (poll_result != ERROR_OK)
718 mxc_nf_info->fin = MXC_NF_FIN_NONE;
722 if ((mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE) &&
723 mxc_nf_info->flags.hw_ecc_enabled) {
724 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
725 switch (ecc_status & 0x000c) {
727 LOG_INFO("main area readed with 1 (correctable) error");
730 LOG_INFO("main area readed with more than 1 (incorrectable) error");
731 return ERROR_NAND_OPERATION_FAILED;
734 switch (ecc_status & 0x0003) {
736 LOG_INFO("spare area readed with 1 (correctable) error");
739 LOG_INFO("main area readed with more than 1 (incorrectable) error");
740 return ERROR_NAND_OPERATION_FAILED;
745 case MXC_NF_FIN_NONE:
751 struct nand_flash_controller mxc_nand_flash_controller = {
753 .nand_device_command = &mxc_nand_device_command,
756 .command = &mxc_command,
757 .address = &mxc_address,
758 .write_data = &mxc_write_data,
759 .read_data = &mxc_read_data,
760 .write_page = &mxc_write_page,
761 .read_page = &mxc_read_page,
762 .nand_ready = &mxc_nand_ready,