git.sur5r.net Git - openocd/blob - src/flash/nand/mx2.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 /*
  26  * Freescale iMX OpenOCD NAND Flash controller support.
  27  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  28  */
  29
  30 /*
  31  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  32  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  33  * "nand write # file 0", "nand verify"
  34  *
  35  * get_next_halfword_from_sram_buffer() not tested
  36  * !! all function only tested with 2k page nand device; mxc_write_page
  37  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  38  * !! oob must be be used due to NFS bug
  39 */
  40 #ifdef HAVE_CONFIG_H
  41 #include "config.h"
  42 #endif
  43
  44 #include "imp.h"
  45 #include "mx2.h"
  46 #include <target/target.h>
  47
  48 /* This permits to print (in LOG_INFO) how much bytes
  49  * has been written after a page read or write.
  50  * This is useful when OpenOCD is used with a graphical
  51  * front-end to estimate progression of the global read/write
  52  */
  53 #undef _MXC_PRINT_STAT
  54 /* #define _MXC_PRINT_STAT */
  55
  56 static const char target_not_halted_err_msg[] =
  57         "target must be halted to use mxc NAND flash controller";
  58 static const char data_block_size_err_msg[] =
  59         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  60 static const char sram_buffer_bounds_err_msg[] =
  61         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  62 static const char get_status_register_err_msg[] = "can't get NAND status";
  63 static uint32_t in_sram_address;
  64 static unsigned char sign_of_sequental_byte_read;
  65
  66 static int initialize_nf_controller(struct nand_device *nand);
  67 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  68 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  69 static int poll_for_complete_op(struct nand_device *nand, const char *text);
  70 static int validate_target_state(struct nand_device *nand);
  71 static int do_data_output(struct nand_device *nand);
  72
  73 static int mxc_command(struct nand_device *nand, uint8_t command);
  74 static int mxc_address(struct nand_device *nand, uint8_t address);
  75
  76 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  77 {
  78         struct mxc_nf_controller *mxc_nf_info;
  79         int hwecc_needed;
  80         int x;
  81
  82         mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  83         if (mxc_nf_info == NULL) {
  84                 LOG_ERROR("no memory for nand controller");
  85                 return ERROR_FAIL;
  86         }
  87         nand->controller_priv = mxc_nf_info;
  88
  89         if (CMD_ARGC < 4) {
  90                 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc [biswap]\"");
  91                 return ERROR_FAIL;
  92         }
  93
  94         /*
  95          * check board type
  96          */
  97         if (strcmp(CMD_ARGV[2], "mx27") == 0)
  98                 mxc_nf_info->mxc_base_addr = 0xD8000000;
  99         else if (strcmp(CMD_ARGV[2], "mx31") == 0)
 100                 mxc_nf_info->mxc_base_addr = 0xB8000000;
 101         else if (strcmp(CMD_ARGV[2], "mx35") == 0)
 102                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 103
 104         /*
 105          * check hwecc requirements
 106          */
 107         hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
 108         if (hwecc_needed == 0)
 109                 mxc_nf_info->flags.hw_ecc_enabled = 1;
 110         else
 111                 mxc_nf_info->flags.hw_ecc_enabled = 0;
 112
 113         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 114         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 115         mxc_nf_info->flags.target_little_endian =
 116         (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 117
 118         /*
 119          * should factory bad block indicator be swaped
 120          * as a workaround for how the nfc handles pages.
 121          */
 122         if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
 123                 LOG_DEBUG("BI-swap enabled");
 124                 mxc_nf_info->flags.biswap_enabled = 1;
 125         }
 126
 127         /*
 128          * testing host endianness
 129          */
 130         x = 1;
 131         if (*(char *) &x == 1)
 132                 mxc_nf_info->flags.host_little_endian = 1;
 133         else
 134                 mxc_nf_info->flags.host_little_endian = 0;
 135         return ERROR_OK;
 136 }
 137
 138 static int mxc_init(struct nand_device *nand)
 139 {
 140         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 141         struct target *target = nand->target;
 142
 143         int validate_target_result;
 144         uint16_t buffsize_register_content;
 145         uint32_t pcsr_register_content;
 146         int retval;
 147         uint16_t nand_status_content;
 148         /*
 149          * validate target state
 150          */
 151         validate_target_result = validate_target_state(nand);
 152         if (validate_target_result != ERROR_OK)
 153                 return validate_target_result;
 154
 155         target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
 156         mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 157
 158         target_read_u32(target, MXC_FMCR, &pcsr_register_content);
 159         if (!nand->bus_width) {
 160                 /* bus_width not yet defined. Read it from MXC_FMCR */
 161                 nand->bus_width =
 162                         (pcsr_register_content & MXC_FMCR_NF_16BIT_SEL) ? 16 : 8;
 163         } else {
 164                 /* bus_width forced in soft. Sync it to MXC_FMCR */
 165                 pcsr_register_content |=
 166                         ((nand->bus_width == 16) ? MXC_FMCR_NF_16BIT_SEL : 0x00000000);
 167                 target_write_u32(target, MXC_FMCR, pcsr_register_content);
 168         }
 169         if (nand->bus_width == 16)
 170                 LOG_DEBUG("MXC_NF : bus is 16-bit width");
 171         else
 172                 LOG_DEBUG("MXC_NF : bus is 8-bit width");
 173
 174         if (!nand->page_size) {
 175                 nand->page_size = (pcsr_register_content & MXC_FMCR_NF_FMS) ? 2048 : 512;
 176         } else {
 177                 pcsr_register_content |=
 178                         ((nand->page_size == 2048) ? MXC_FMCR_NF_FMS : 0x00000000);
 179                 target_write_u32(target, MXC_FMCR, pcsr_register_content);
 180         }
 181         if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 182                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 183                           "pagesize 2048 is incompatible with it");
 184         } else {
 185                 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
 186         }
 187
 188         initialize_nf_controller(nand);
 189
 190         retval = ERROR_OK;
 191         retval |= mxc_command(nand, NAND_CMD_STATUS);
 192         retval |= mxc_address(nand, 0x00);
 193         retval |= do_data_output(nand);
 194         if (retval != ERROR_OK) {
 195                 LOG_ERROR(get_status_register_err_msg);
 196                 return ERROR_FAIL;
 197         }
 198         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 199         if (!(nand_status_content & 0x0080)) {
 200                 LOG_INFO("NAND read-only");
 201                 mxc_nf_info->flags.nand_readonly = 1;
 202         } else {
 203                 mxc_nf_info->flags.nand_readonly = 0;
 204         }
 205         return ERROR_OK;
 206 }
 207
 208 static int mxc_read_data(struct nand_device *nand, void *data)
 209 {
 210         int validate_target_result;
 211         int try_data_output_from_nand_chip;
 212         /*
 213          * validate target state
 214          */
 215         validate_target_result = validate_target_state(nand);
 216         if (validate_target_result != ERROR_OK)
 217                 return validate_target_result;
 218
 219         /*
 220          * get data from nand chip
 221          */
 222         try_data_output_from_nand_chip = do_data_output(nand);
 223         if (try_data_output_from_nand_chip != ERROR_OK) {
 224                 LOG_ERROR("mxc_read_data : read data failed : '%x'",
 225                                   try_data_output_from_nand_chip);
 226                 return try_data_output_from_nand_chip;
 227         }
 228
 229         if (nand->bus_width == 16)
 230                 get_next_halfword_from_sram_buffer(nand, data);
 231         else
 232                 get_next_byte_from_sram_buffer(nand, data);
 233
 234         return ERROR_OK;
 235 }
 236
 237 static int mxc_write_data(struct nand_device *nand, uint16_t data)
 238 {
 239         LOG_ERROR("write_data() not implemented");
 240         return ERROR_NAND_OPERATION_FAILED;
 241 }
 242
 243 static int mxc_reset(struct nand_device *nand)
 244 {
 245         /*
 246          * validate target state
 247          */
 248         int validate_target_result;
 249         validate_target_result = validate_target_state(nand);
 250         if (validate_target_result != ERROR_OK)
 251                 return validate_target_result;
 252         initialize_nf_controller(nand);
 253         return ERROR_OK;
 254 }
 255
 256 static int mxc_command(struct nand_device *nand, uint8_t command)
 257 {
 258         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 259         struct target *target = nand->target;
 260         int validate_target_result;
 261         int poll_result;
 262         /*
 263          * validate target state
 264          */
 265         validate_target_result = validate_target_state(nand);
 266         if (validate_target_result != ERROR_OK)
 267                 return validate_target_result;
 268
 269         switch (command) {
 270         case NAND_CMD_READOOB:
 271                 command = NAND_CMD_READ0;
 272                 /* set read point for data_read() and read_block_data() to
 273                  * spare area in SRAM buffer
 274                  */
 275                 in_sram_address = MXC_NF_SPARE_BUFFER0;
 276                 break;
 277         case NAND_CMD_READ1:
 278                 command = NAND_CMD_READ0;
 279                 /*
 280                  * offset == one half of page size
 281                  */
 282                 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 283                 break;
 284         default:
 285                 in_sram_address = MXC_NF_MAIN_BUFFER0;
 286                 break;
 287         }
 288
 289         target_write_u16(target, MXC_NF_FCMD, command);
 290         /*
 291          * start command input operation (set MXC_NF_BIT_OP_DONE==0)
 292          */
 293         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
 294         poll_result = poll_for_complete_op(nand, "command");
 295         if (poll_result != ERROR_OK)
 296                 return poll_result;
 297         /*
 298          * reset cursor to begin of the buffer
 299          */
 300         sign_of_sequental_byte_read = 0;
 301         /* Handle special read command and adjust NF_CFG2(FDO) */
 302         switch (command) {
 303         case NAND_CMD_READID:
 304                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
 305                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 306                 break;
 307         case NAND_CMD_STATUS:
 308                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 309                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 310                 target_write_u16 (target, MXC_NF_BUFADDR, 0);
 311                 in_sram_address = 0;
 312                 break;
 313         case NAND_CMD_READ0:
 314                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 315                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 316                 break;
 317         default:
 318                 /* Ohter command use the default 'One page data out' FDO */
 319                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 320                 break;
 321         }
 322         return ERROR_OK;
 323 }
 324
 325 static int mxc_address(struct nand_device *nand, uint8_t address)
 326 {
 327         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 328         struct target *target = nand->target;
 329         int validate_target_result;
 330         int poll_result;
 331         /*
 332          * validate target state
 333          */
 334         validate_target_result = validate_target_state(nand);
 335         if (validate_target_result != ERROR_OK)
 336                 return validate_target_result;
 337
 338         target_write_u16(target, MXC_NF_FADDR, address);
 339         /*
 340          * start address input operation (set MXC_NF_BIT_OP_DONE==0)
 341          */
 342         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
 343         poll_result = poll_for_complete_op(nand, "address");
 344         if (poll_result != ERROR_OK)
 345                 return poll_result;
 346
 347         return ERROR_OK;
 348 }
 349
 350 static int mxc_nand_ready(struct nand_device *nand, int tout)
 351 {
 352         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 353         struct target *target = nand->target;
 354         uint16_t poll_complete_status;
 355         int validate_target_result;
 356
 357         /*
 358          * validate target state
 359          */
 360         validate_target_result = validate_target_state(nand);
 361         if (validate_target_result != ERROR_OK)
 362                 return validate_target_result;
 363
 364         do {
 365                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 366                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 367                         return tout;
 368
 369                 alive_sleep(1);
 370         }
 371         while (tout-- > 0);
 372         return tout;
 373 }
 374
 375 static int mxc_write_page(struct nand_device *nand, uint32_t page,
 376                                                         uint8_t *data, uint32_t data_size,
 377                                                         uint8_t *oob, uint32_t oob_size)
 378 {
 379         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 380         struct target *target = nand->target;
 381         int retval;
 382         uint16_t nand_status_content;
 383         uint16_t swap1, swap2, new_swap1;
 384         int poll_result;
 385         if (data_size % 2) {
 386                 LOG_ERROR(data_block_size_err_msg, data_size);
 387                 return ERROR_NAND_OPERATION_FAILED;
 388         }
 389         if (oob_size % 2) {
 390                 LOG_ERROR(data_block_size_err_msg, oob_size);
 391                 return ERROR_NAND_OPERATION_FAILED;
 392         }
 393         if (!data) {
 394                 LOG_ERROR("nothing to program");
 395                 return ERROR_NAND_OPERATION_FAILED;
 396         }
 397         /*
 398          * validate target state
 399          */
 400         retval = validate_target_state(nand);
 401         if (retval != ERROR_OK)
 402                 return retval;
 403
 404         in_sram_address = MXC_NF_MAIN_BUFFER0;
 405         sign_of_sequental_byte_read = 0;
 406         retval = ERROR_OK;
 407         retval |= mxc_command(nand, NAND_CMD_SEQIN);
 408         retval |= mxc_address(nand, 0); /* col */
 409         retval |= mxc_address(nand, 0); /* col */
 410         retval |= mxc_address(nand, page & 0xff); /* page address */
 411         retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
 412         retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
 413
 414         target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 415         if (oob) {
 416                 if (mxc_nf_info->flags.hw_ecc_enabled) {
 417                         /*
 418                          * part of spare block will be overrided by hardware
 419                          * ECC generator
 420                          */
 421                         LOG_DEBUG("part of spare block will be overrided "
 422                                   "by hardware ECC generator");
 423                 }
 424                 target_write_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size,     oob);
 425         }
 426
 427         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 428                 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
 429                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 430                 if (oob) {
 431                         LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
 432                         return ERROR_NAND_OPERATION_FAILED;
 433                 }
 434                 swap2 = 0xffff;  /* Spare buffer unused forced to 0xffff */
 435                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 436                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 437                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 438                 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
 439         }
 440
 441         /*
 442          * start data input operation (set MXC_NF_BIT_OP_DONE==0)
 443          */
 444         target_write_u16(target, MXC_NF_BUFADDR, 0);
 445         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 446         poll_result = poll_for_complete_op(nand, "data input");
 447         if (poll_result != ERROR_OK)
 448                 return poll_result;
 449
 450         target_write_u16(target, MXC_NF_BUFADDR, 1);
 451         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 452         poll_result = poll_for_complete_op(nand, "data input");
 453         if (poll_result != ERROR_OK)
 454                 return poll_result;
 455
 456         target_write_u16(target, MXC_NF_BUFADDR, 2);
 457         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 458         poll_result = poll_for_complete_op(nand, "data input");
 459         if (poll_result != ERROR_OK)
 460                 return poll_result;
 461
 462         target_write_u16(target, MXC_NF_BUFADDR, 3);
 463         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 464         poll_result = poll_for_complete_op(nand, "data input");
 465         if (poll_result != ERROR_OK)
 466                 return poll_result;
 467
 468         retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
 469         if (retval != ERROR_OK)
 470                 return retval;
 471
 472         /*
 473          * check status register
 474          */
 475         retval = ERROR_OK;
 476         retval |= mxc_command(nand, NAND_CMD_STATUS);
 477         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 478         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 479         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 480         retval |= do_data_output(nand);
 481         if (retval != ERROR_OK) {
 482                 LOG_ERROR(get_status_register_err_msg);
 483                 return retval;
 484         }
 485         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 486         if (nand_status_content & 0x0001) {
 487                 /*
 488                  * page not correctly written
 489                  */
 490                 return ERROR_NAND_OPERATION_FAILED;
 491         }
 492 #ifdef _MXC_PRINT_STAT
 493         LOG_INFO("%d bytes newly written", data_size);
 494 #endif
 495         return ERROR_OK;
 496 }
 497
 498 static int mxc_read_page(struct nand_device *nand, uint32_t page,
 499                                                    uint8_t *data, uint32_t data_size,
 500                                                    uint8_t *oob, uint32_t oob_size)
 501 {
 502         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 503         struct target *target = nand->target;
 504         int retval;
 505         uint16_t swap1, swap2, new_swap1;
 506
 507         if (data_size % 2) {
 508                 LOG_ERROR(data_block_size_err_msg, data_size);
 509                 return ERROR_NAND_OPERATION_FAILED;
 510         }
 511         if (oob_size % 2) {
 512                 LOG_ERROR(data_block_size_err_msg, oob_size);
 513                 return ERROR_NAND_OPERATION_FAILED;
 514         }
 515
 516         /*
 517          * validate target state
 518          */
 519         retval = validate_target_state(nand);
 520         if (retval != ERROR_OK) {
 521                 return retval;
 522         }
 523         /* Reset address_cycles before mxc_command ?? */
 524         retval = mxc_command(nand, NAND_CMD_READ0);
 525         if (retval != ERROR_OK) return retval;
 526         retval = mxc_address(nand, 0); /* col */
 527         if (retval != ERROR_OK) return retval;
 528         retval = mxc_address(nand, 0); /* col */
 529         if (retval != ERROR_OK) return retval;
 530         retval = mxc_address(nand, page & 0xff); /* page address */
 531         if (retval != ERROR_OK) return retval;
 532         retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
 533         if (retval != ERROR_OK) return retval;
 534         retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
 535         if (retval != ERROR_OK) return retval;
 536         retval = mxc_command(nand, NAND_CMD_READSTART);
 537         if (retval != ERROR_OK) return retval;
 538
 539         target_write_u16(target, MXC_NF_BUFADDR, 0);
 540         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 541         retval = do_data_output(nand);
 542         if (retval != ERROR_OK) {
 543                 LOG_ERROR("MXC_NF : Error reading page 0");
 544                 return retval;
 545         }
 546         /* Test nand page size to know how much MAIN_BUFFER must be written */
 547         target_write_u16(target, MXC_NF_BUFADDR, 1);
 548         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 549         retval = do_data_output(nand);
 550         if (retval != ERROR_OK) {
 551                 LOG_ERROR("MXC_NF : Error reading page 1");
 552                 return retval;
 553         }
 554         target_write_u16(target, MXC_NF_BUFADDR, 2);
 555         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 556         retval = do_data_output(nand);
 557         if (retval != ERROR_OK) {
 558                 LOG_ERROR("MXC_NF : Error reading page 2");
 559                 return retval;
 560         }
 561         target_write_u16(target, MXC_NF_BUFADDR, 3);
 562         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 563         retval = do_data_output(nand);
 564         if (retval != ERROR_OK) {
 565                 LOG_ERROR("MXC_NF : Error reading page 3");
 566                 return retval;
 567         }
 568
 569         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 570                 /* BI-swap -  work-around of mxc NFC for NAND device with page == 2k */
 571                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 572                 target_read_u16(target, MXC_NF_SPARE_BUFFER3 + 4, &swap2);
 573                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 574                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 575                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 576                 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
 577         }
 578
 579         if (data)
 580                 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 581         if (oob)
 582                 target_read_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
 583
 584 #ifdef _MXC_PRINT_STAT
 585         if (data_size > 0) {
 586                 /* When Operation Status is read (when page is erased),
 587                  * this function is used but data_size is null.
 588                  */
 589                 LOG_INFO("%d bytes newly read", data_size);
 590         }
 591 #endif
 592         return ERROR_OK;
 593 }
 594
 595 static int initialize_nf_controller(struct nand_device *nand)
 596 {
 597         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 598         struct target *target = nand->target;
 599         uint16_t work_mode;
 600         uint16_t temp;
 601         /*
 602          * resets NAND flash controller in zero time ? I dont know.
 603          */
 604         target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 605         work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
 606         if (target->endianness == TARGET_BIG_ENDIAN) {
 607                 LOG_DEBUG("MXC_NF : work in Big Endian mode");
 608                 work_mode |= MXC_NF_BIT_BE_EN;
 609         } else {
 610                 LOG_DEBUG("MXC_NF : work in Little Endian mode");
 611         }
 612         if (mxc_nf_info->flags.hw_ecc_enabled) {
 613                 LOG_DEBUG("MXC_NF : work with ECC mode");
 614                 work_mode |= MXC_NF_BIT_ECC_EN;
 615         } else {
 616                 LOG_DEBUG("MXC_NF : work without ECC mode");
 617         }
 618         target_write_u16(target, MXC_NF_CFG1, work_mode);
 619         /*
 620          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 621          */
 622         target_write_u16(target, MXC_NF_BUFCFG, 2);
 623         target_read_u16(target, MXC_NF_FWP, &temp);
 624         if ((temp & 0x0007) == 1) {
 625                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 626                 return ERROR_FAIL;
 627         }
 628
 629         /*
 630          * unlock NAND flash for write
 631          */
 632         target_write_u16(target, MXC_NF_FWP, 4);
 633         target_write_u16(target, MXC_NF_LOCKSTART, 0x0000);
 634         target_write_u16(target, MXC_NF_LOCKEND, 0xFFFF);
 635         /*
 636          * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
 637          */
 638         target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
 639         /*
 640          * address of SRAM buffer
 641          */
 642         in_sram_address = MXC_NF_MAIN_BUFFER0;
 643         sign_of_sequental_byte_read = 0;
 644         return ERROR_OK;
 645 }
 646
 647 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
 648 {
 649         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 650         struct target *target = nand->target;
 651         static uint8_t even_byte = 0;
 652         uint16_t temp;
 653         /*
 654          * host-big_endian ??
 655          */
 656         if (sign_of_sequental_byte_read == 0)
 657                 even_byte = 0;
 658
 659         if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
 660                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 661                 *value = 0;
 662                 sign_of_sequental_byte_read = 0;
 663                 even_byte = 0;
 664                 return ERROR_NAND_OPERATION_FAILED;
 665         } else {
 666                 target_read_u16(target, in_sram_address, &temp);
 667                 if (even_byte) {
 668                         *value = temp >> 8;
 669                         even_byte = 0;
 670                         in_sram_address += 2;
 671                 } else {
 672                         *value = temp & 0xff;
 673                         even_byte = 1;
 674                 }
 675         }
 676         sign_of_sequental_byte_read = 1;
 677         return ERROR_OK;
 678 }
 679
 680 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
 681 {
 682         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 683         struct target *target = nand->target;
 684
 685         if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
 686                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 687                 *value = 0;
 688                 return ERROR_NAND_OPERATION_FAILED;
 689         } else {
 690                 target_read_u16(target, in_sram_address, value);
 691                 in_sram_address += 2;
 692         }
 693         return ERROR_OK;
 694 }
 695
 696 static int poll_for_complete_op(struct nand_device *nand, const char *text)
 697 {
 698         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 699         struct target *target = nand->target;
 700         uint16_t poll_complete_status;
 701
 702         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
 703                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 704                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 705                         break;
 706
 707                 usleep(10);
 708         }
 709         if (!(poll_complete_status & MXC_NF_BIT_OP_DONE)) {
 710                 LOG_ERROR("%s sending timeout", text);
 711                 return ERROR_NAND_OPERATION_FAILED;
 712         }
 713         return ERROR_OK;
 714 }
 715
 716 static int validate_target_state(struct nand_device *nand)
 717 {
 718         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 719         struct target *target = nand->target;
 720
 721         if (target->state != TARGET_HALTED) {
 722                 LOG_ERROR(target_not_halted_err_msg);
 723                 return ERROR_NAND_OPERATION_FAILED;
 724         }
 725
 726         if (mxc_nf_info->flags.target_little_endian !=
 727             (target->endianness == TARGET_LITTLE_ENDIAN)) {
 728                 /*
 729                  * endianness changed after NAND controller probed
 730                  */
 731                 return ERROR_NAND_OPERATION_FAILED;
 732         }
 733         return ERROR_OK;
 734 }
 735
 736 static int do_data_output(struct nand_device *nand)
 737 {
 738         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 739         struct target *target = nand->target;
 740         int poll_result;
 741         uint16_t ecc_status;
 742         switch (mxc_nf_info->fin) {
 743         case MXC_NF_FIN_DATAOUT:
 744                 /*
 745                  * start data output operation (set MXC_NF_BIT_OP_DONE==0)
 746                  */
 747                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
 748                 poll_result = poll_for_complete_op(nand, "data output");
 749                 if (poll_result != ERROR_OK)
 750                         return poll_result;
 751
 752                 mxc_nf_info->fin = MXC_NF_FIN_NONE;
 753                 /*
 754                  * ECC stuff
 755                  */
 756                 if ((mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE) &&
 757                         mxc_nf_info->flags.hw_ecc_enabled) {
 758                         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 759                         switch (ecc_status & 0x000c) {
 760                         case 1 << 2:
 761                                 LOG_INFO("main area readed with 1 (correctable) error");
 762                                 break;
 763                         case 2 << 2:
 764                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 765                                 return ERROR_NAND_OPERATION_FAILED;
 766                                         break;
 767                         }
 768                         switch (ecc_status & 0x0003) {
 769                         case 1:
 770                                 LOG_INFO("spare area readed with 1 (correctable) error");
 771                                 break;
 772                         case 2:
 773                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 774                                 return ERROR_NAND_OPERATION_FAILED;
 775                                 break;
 776                         }
 777                 }
 778                 break;
 779         case MXC_NF_FIN_NONE:
 780                 break;
 781         }
 782         return ERROR_OK;
 783 }
 784
 785 struct nand_flash_controller mxc_nand_flash_controller = {
 786         .name                                   = "mxc",
 787         .nand_device_command    = &mxc_nand_device_command,
 788         .init                                   = &mxc_init,
 789         .reset                                  = &mxc_reset,
 790         .command                                = &mxc_command,
 791         .address                                = &mxc_address,
 792         .write_data                             = &mxc_write_data,
 793         .read_data                              = &mxc_read_data,
 794         .write_page                             = &mxc_write_page,
 795         .read_page                              = &mxc_read_page,
 796         .nand_ready                             = &mxc_nand_ready,
 797 };