git.sur5r.net Git - openocd/blob - src/flash/nand/mx2.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 /*
  26  * Freescale iMX2* OpenOCD NAND Flash controller support.
  27  * based on Freescale iMX3* OpenOCD NAND Flash controller support.
  28  */
  29
  30 /*
  31  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
  32  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  33  * "nand write # file 0", "nand verify"
  34  *
  35  * get_next_halfword_from_sram_buffer() not tested
  36  * !! all function only tested with 2k page nand device; imx27_write_page
  37  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  38  * !! oob must be be used due to NFS bug
  39 */
  40 #ifdef HAVE_CONFIG_H
  41 #include "config.h"
  42 #endif
  43
  44 #include "imp.h"
  45 #include "mx2.h"
  46 #include <target/target.h>
  47
  48 /* This permits to print (in LOG_INFO) how much bytes
  49  * has been written after a page read or write.
  50  * This is useful when OpenOCD is used with a graphical
  51  * front-end to estimate progression of the global read/write
  52  */
  53 #undef _MX2_PRINT_STAT
  54 //#define _MX2_PRINT_STAT
  55
  56 static const char target_not_halted_err_msg[] =
  57         "target must be halted to use mx2 NAND flash controller";
  58 static const char data_block_size_err_msg[] =
  59         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  60 static const char sram_buffer_bounds_err_msg[] =
  61         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  62 static const char get_status_register_err_msg[] = "can't get NAND status";
  63 static uint32_t in_sram_address;
  64 static unsigned char sign_of_sequental_byte_read;
  65
  66 static int initialize_nf_controller(struct nand_device *nand);
  67 static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value);
  68 static int get_next_halfword_from_sram_buffer(struct target * target,
  69                                                uint16_t * value);
  70 static int poll_for_complete_op(struct target * target, const char *text);
  71 static int validate_target_state(struct nand_device *nand);
  72 static int do_data_output(struct nand_device *nand);
  73
  74 static int imx27_command(struct nand_device *nand, uint8_t command);
  75 static int imx27_address(struct nand_device *nand, uint8_t address);
  76
  77 NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
  78 {
  79         struct mx2_nf_controller *mx2_nf_info;
  80         int hwecc_needed;
  81         int x;
  82         mx2_nf_info = malloc(sizeof(struct mx2_nf_controller));
  83         if (mx2_nf_info == NULL) {
  84                 LOG_ERROR("no memory for nand controller");
  85                 return ERROR_FAIL;
  86         }
  87
  88         nand->controller_priv = mx2_nf_info;
  89         mx2_nf_info->target = get_target(CMD_ARGV[1]);
  90         if (mx2_nf_info->target == NULL) {
  91                 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
  92                 return ERROR_FAIL;
  93         }
  94         if (CMD_ARGC < 3) {
  95                 LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
  96                 return ERROR_FAIL;
  97         }
  98         /*
  99          * check hwecc requirements
 100          */
 101
 102         hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
 103         if (hwecc_needed == 0)
 104                 mx2_nf_info->flags.hw_ecc_enabled = 1;
 105         else
 106                 mx2_nf_info->flags.hw_ecc_enabled = 0;
 107
 108         mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
 109         mx2_nf_info->fin = MX2_NF_FIN_NONE;
 110         mx2_nf_info->flags.target_little_endian =
 111         (mx2_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
 112         /*
 113          * testing host endianess
 114          */
 115         x = 1;
 116         if (*(char *) &x == 1)
 117                 mx2_nf_info->flags.host_little_endian = 1;
 118         else
 119                 mx2_nf_info->flags.host_little_endian = 0;
 120         return ERROR_OK;
 121 }
 122
 123 static int imx27_init(struct nand_device *nand)
 124 {
 125         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 126         struct target *target = mx2_nf_info->target;
 127
 128         int validate_target_result;
 129         uint16_t buffsize_register_content;
 130         uint32_t pcsr_register_content;
 131         int retval;
 132         uint16_t nand_status_content;
 133         /*
 134          * validate target state
 135          */
 136         validate_target_result = validate_target_state(nand);
 137         if (validate_target_result != ERROR_OK)
 138                 return validate_target_result;
 139
 140         target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content);
 141         mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 142
 143         target_read_u32(target, MX2_FMCR, &pcsr_register_content);
 144         if (!nand->bus_width) {
 145                 /* bus_width not yet defined. Read it from MX2_FMCR */
 146                 nand->bus_width =
 147                     (pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8;
 148         } else {
 149                 /* bus_width forced in soft. Sync it to MX2_FMCR */
 150                 pcsr_register_content |=
 151                     ((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000);
 152                 target_write_u32(target, MX2_FMCR, pcsr_register_content);
 153         }
 154         if (nand->bus_width == 16)
 155                 LOG_DEBUG("MX2_NF : bus is 16-bit width");
 156         else
 157                 LOG_DEBUG("MX2_NF : bus is 8-bit width");
 158
 159         if (!nand->page_size) {
 160                 nand->page_size =
 161                     (pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512;
 162         } else {
 163                 pcsr_register_content |=
 164                     ((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000);
 165                 target_write_u32(target, MX2_FMCR, pcsr_register_content);
 166         }
 167         if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 168                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 169                           "pagesize 2048 is incompatible with it");
 170         } else {
 171                 LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
 172         }
 173
 174         initialize_nf_controller(nand);
 175
 176         retval = ERROR_OK;
 177         retval |= imx27_command(nand, NAND_CMD_STATUS);
 178         retval |= imx27_address(nand, 0x00);
 179         retval |= do_data_output(nand);
 180         if (retval != ERROR_OK) {
 181                 LOG_ERROR(get_status_register_err_msg);
 182                 return ERROR_FAIL;
 183         }
 184         target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
 185         if (!(nand_status_content & 0x0080)) {
 186                 LOG_INFO("NAND read-only");
 187                 mx2_nf_info->flags.nand_readonly = 1;
 188         } else {
 189                 mx2_nf_info->flags.nand_readonly = 0;
 190         }
 191         return ERROR_OK;
 192 }
 193
 194 static int imx27_read_data(struct nand_device *nand, void *data)
 195 {
 196         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 197         struct target *target = mx2_nf_info->target;
 198         int validate_target_result;
 199         int try_data_output_from_nand_chip;
 200         /*
 201          * validate target state
 202          */
 203         validate_target_result = validate_target_state(nand);
 204         if (validate_target_result != ERROR_OK)
 205                 return validate_target_result;
 206
 207         /*
 208          * get data from nand chip
 209          */
 210         try_data_output_from_nand_chip = do_data_output(nand);
 211         if (try_data_output_from_nand_chip != ERROR_OK) {
 212                 LOG_ERROR("imx27_read_data : read data failed : '%x'",
 213                           try_data_output_from_nand_chip);
 214                 return try_data_output_from_nand_chip;
 215         }
 216
 217         if (nand->bus_width == 16)
 218             get_next_halfword_from_sram_buffer(target, data);
 219         else
 220             get_next_byte_from_sram_buffer(target, data);
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int imx27_write_data(struct nand_device *nand, uint16_t data)
 226 {
 227         LOG_ERROR("write_data() not implemented");
 228         return ERROR_NAND_OPERATION_FAILED;
 229 }
 230
 231 static int imx27_reset(struct nand_device *nand)
 232 {
 233         /*
 234          * validate target state
 235          */
 236         int validate_target_result;
 237         validate_target_result = validate_target_state(nand);
 238         if (validate_target_result != ERROR_OK)
 239             return validate_target_result;
 240         initialize_nf_controller(nand);
 241         return ERROR_OK;
 242 }
 243
 244 static int imx27_command(struct nand_device *nand, uint8_t command)
 245 {
 246         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 247         struct target *target = mx2_nf_info->target;
 248         int validate_target_result;
 249         int poll_result;
 250         /*
 251          * validate target state
 252          */
 253         validate_target_result = validate_target_state(nand);
 254         if (validate_target_result != ERROR_OK)
 255                 return validate_target_result;
 256
 257         switch(command) {
 258         case NAND_CMD_READOOB:
 259                 command = NAND_CMD_READ0;
 260                 /* set read point for data_read() and read_block_data() to
 261                  * spare area in SRAM buffer
 262                  */
 263                 in_sram_address = MX2_NF_SPARE_BUFFER0;
 264                 break;
 265         case NAND_CMD_READ1:
 266                 command = NAND_CMD_READ0;
 267                 /*
 268                  * offset == one half of page size
 269                  */
 270                 in_sram_address =
 271                     MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 272                 break;
 273         default:
 274                 in_sram_address = MX2_NF_MAIN_BUFFER0;
 275                 break;
 276         }
 277
 278         target_write_u16(target, MX2_NF_FCMD, command);
 279         /*
 280          * start command input operation (set MX2_NF_BIT_OP_DONE==0)
 281          */
 282         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI);
 283         poll_result = poll_for_complete_op(target, "command");
 284         if (poll_result != ERROR_OK)
 285                 return poll_result;
 286         /*
 287          * reset cursor to begin of the buffer
 288          */
 289         sign_of_sequental_byte_read = 0;
 290         /* Handle special read command and adjust NF_CFG2(FDO) */
 291         switch(command) {
 292         case NAND_CMD_READID:
 293                 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID;
 294                 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 295                 break;
 296         case NAND_CMD_STATUS:
 297                 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
 298                 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 299                 target_write_u16 (target, MX2_NF_BUFADDR, 0);
 300                 in_sram_address = 0;
 301                 break;
 302         case NAND_CMD_READ0:
 303                 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 304                 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
 305                 break;
 306         default:
 307                 /* Ohter command use the default 'One page data out' FDO */
 308                 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
 309                 break;
 310         }
 311         return ERROR_OK;
 312 }
 313
 314 static int imx27_address(struct nand_device *nand, uint8_t address)
 315 {
 316         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 317         struct target *target = mx2_nf_info->target;
 318         int validate_target_result;
 319         int poll_result;
 320         /*
 321          * validate target state
 322          */
 323         validate_target_result = validate_target_state(nand);
 324         if (validate_target_result != ERROR_OK)
 325                 return validate_target_result;
 326
 327         target_write_u16(target, MX2_NF_FADDR, address);
 328         /*
 329          * start address input operation (set MX2_NF_BIT_OP_DONE==0)
 330          */
 331         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI);
 332         poll_result = poll_for_complete_op(target, "address");
 333         if (poll_result != ERROR_OK)
 334                 return poll_result;
 335
 336         return ERROR_OK;
 337 }
 338
 339 static int imx27_nand_ready(struct nand_device *nand, int tout)
 340 {
 341         uint16_t poll_complete_status;
 342         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 343         struct target *target = mx2_nf_info->target;
 344         int validate_target_result;
 345
 346         /*
 347          * validate target state
 348          */
 349         validate_target_result = validate_target_state(nand);
 350         if (validate_target_result != ERROR_OK)
 351                 return validate_target_result;
 352
 353         do {
 354                 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
 355                 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
 356                         return tout;
 357
 358                 alive_sleep(1);
 359         }
 360         while (tout-- > 0);
 361         return tout;
 362 }
 363
 364 static int imx27_write_page(struct nand_device *nand, uint32_t page,
 365                              uint8_t * data, uint32_t data_size, uint8_t * oob,
 366                              uint32_t oob_size)
 367 {
 368         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 369         struct target *target = mx2_nf_info->target;
 370         int retval;
 371         uint16_t nand_status_content;
 372         uint16_t swap1, swap2, new_swap1;
 373         int poll_result;
 374         if (data_size % 2) {
 375                 LOG_ERROR(data_block_size_err_msg, data_size);
 376                 return ERROR_NAND_OPERATION_FAILED;
 377         }
 378         if (oob_size % 2) {
 379                 LOG_ERROR(data_block_size_err_msg, oob_size);
 380                 return ERROR_NAND_OPERATION_FAILED;
 381         }
 382         if (!data) {
 383                 LOG_ERROR("nothing to program");
 384                 return ERROR_NAND_OPERATION_FAILED;
 385         }
 386         /*
 387          * validate target state
 388          */
 389         retval = validate_target_state(nand);
 390         if (retval != ERROR_OK)
 391                 return retval;
 392
 393         in_sram_address = MX2_NF_MAIN_BUFFER0;
 394         sign_of_sequental_byte_read = 0;
 395         retval = ERROR_OK;
 396         retval |= imx27_command(nand, NAND_CMD_SEQIN);
 397         retval |= imx27_address(nand, 0); //col
 398         retval |= imx27_address(nand, 0); //col
 399         retval |= imx27_address(nand, page & 0xff); //page address
 400         retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
 401         retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
 402
 403         target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
 404         if (oob) {
 405                 if (mx2_nf_info->flags.hw_ecc_enabled) {
 406                         /*
 407                          * part of spare block will be overrided by hardware
 408                          * ECC generator
 409                          */
 410                         LOG_DEBUG("part of spare block will be overrided "
 411                                   "by hardware ECC generator");
 412                 }
 413                 target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
 414                                     oob);
 415         }
 416         //BI-swap -  work-around of imx27 NFC for NAND device with page == 2kb
 417         target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
 418         if (oob) {
 419                 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
 420                           "in mx2 driver");
 421                 return ERROR_NAND_OPERATION_FAILED;
 422         }
 423         //target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
 424         swap2 = 0xffff;  //Spare buffer unused forced to 0xffff
 425         new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 426         swap2 = (swap1 << 8) | (swap2 & 0xFF);
 427
 428         target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
 429         target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
 430         /*
 431          * start data input operation (set MX2_NF_BIT_OP_DONE==0)
 432          */
 433         target_write_u16(target, MX2_NF_BUFADDR, 0);
 434         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 435         poll_result = poll_for_complete_op(target, "data input");
 436         if (poll_result != ERROR_OK)
 437                 return poll_result;
 438
 439         target_write_u16(target, MX2_NF_BUFADDR, 1);
 440         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 441         poll_result = poll_for_complete_op(target, "data input");
 442         if (poll_result != ERROR_OK)
 443                 return poll_result;
 444
 445         target_write_u16(target, MX2_NF_BUFADDR, 2);
 446         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 447         poll_result = poll_for_complete_op(target, "data input");
 448         if (poll_result != ERROR_OK)
 449                 return poll_result;
 450
 451         target_write_u16(target, MX2_NF_BUFADDR, 3);
 452         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 453         poll_result = poll_for_complete_op(target, "data input");
 454         if (poll_result != ERROR_OK)
 455                 return poll_result;
 456
 457         retval |= imx27_command(nand, NAND_CMD_PAGEPROG);
 458         if (retval != ERROR_OK)
 459                 return retval;
 460
 461         /*
 462          * check status register
 463          */
 464         retval = ERROR_OK;
 465         retval |= imx27_command(nand, NAND_CMD_STATUS);
 466         target_write_u16 (target, MX2_NF_BUFADDR, 0);
 467         mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
 468         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 469         retval |= do_data_output(nand);
 470         if (retval != ERROR_OK) {
 471                 LOG_ERROR (get_status_register_err_msg);
 472                 return retval;
 473         }
 474         target_read_u16 (target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
 475         if (nand_status_content & 0x0001) {
 476                 /*
 477                  * page not correctly written
 478                  */
 479                 return ERROR_NAND_OPERATION_FAILED;
 480         }
 481 #ifdef _MX2_PRINT_STAT
 482         LOG_INFO("%d bytes newly written", data_size);
 483 #endif
 484         return ERROR_OK;
 485 }
 486
 487 static int imx27_read_page(struct nand_device *nand, uint32_t page,
 488                             uint8_t * data, uint32_t data_size, uint8_t * oob,
 489                             uint32_t oob_size)
 490 {
 491         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 492         struct target *target = mx2_nf_info->target;
 493         int retval;
 494         uint16_t swap1, swap2, new_swap1;
 495         if (data_size % 2) {
 496             LOG_ERROR(data_block_size_err_msg, data_size);
 497             return ERROR_NAND_OPERATION_FAILED;
 498         }
 499         if (oob_size % 2) {
 500             LOG_ERROR(data_block_size_err_msg, oob_size);
 501             return ERROR_NAND_OPERATION_FAILED;
 502         }
 503
 504         /*
 505          * validate target state
 506          */
 507         retval = validate_target_state(nand);
 508         if (retval != ERROR_OK) {
 509                 return retval;
 510         }
 511         /* Reset address_cycles before imx27_command ?? */
 512         retval = ERROR_OK;
 513         retval |= imx27_command(nand, NAND_CMD_READ0);
 514
 515         retval |= imx27_address(nand, 0); //col
 516         retval |= imx27_address(nand, 0); //col
 517         retval |= imx27_address(nand, page & 0xff); //page address
 518         retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
 519         retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
 520         retval |= imx27_command(nand, NAND_CMD_READSTART);
 521
 522         target_write_u16(target, MX2_NF_BUFADDR, 0);
 523         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 524         retval = do_data_output(nand);
 525         if (retval != ERROR_OK) {
 526                 LOG_ERROR("MX2_NF : Error reading page 0");
 527                 return retval;
 528         }
 529         //Test nand page size to know how much MAIN_BUFFER must be written
 530         target_write_u16(target, MX2_NF_BUFADDR, 1);
 531         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 532         retval = do_data_output(nand);
 533         if (retval != ERROR_OK) {
 534                 LOG_ERROR("MX2_NF : Error reading page 1");
 535                 return retval;
 536         }
 537         target_write_u16(target, MX2_NF_BUFADDR, 2);
 538         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 539         retval = do_data_output(nand);
 540         if (retval != ERROR_OK) {
 541                 LOG_ERROR("MX2_NF : Error reading page 2");
 542                 return retval;
 543         }
 544         target_write_u16(target, MX2_NF_BUFADDR, 3);
 545         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 546         retval = do_data_output(nand);
 547         if (retval != ERROR_OK) {
 548                 LOG_ERROR("MX2_NF : Error reading page 3");
 549                 return retval;
 550         }
 551         //BI-swap -  work-around of imx27 NFC for NAND device with page == 2k
 552         target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
 553         target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
 554         new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 555         swap2 = (swap1 << 8) | (swap2 & 0xFF);
 556         target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
 557         target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
 558
 559         if (data)
 560                 target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
 561         if (oob)
 562                 target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
 563                                     oob);
 564 #ifdef _MX2_PRINT_STAT
 565         if (data_size > 0) {
 566                 /* When Operation Status is read (when page is erased),
 567                  * this function is used but data_size is null.
 568                  */
 569                 LOG_INFO("%d bytes newly read", data_size);
 570         }
 571 #endif
 572         return ERROR_OK;
 573 }
 574
 575 static int initialize_nf_controller(struct nand_device *nand)
 576 {
 577         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 578         struct target *target = mx2_nf_info->target;
 579         uint16_t work_mode;
 580         uint16_t temp;
 581         /*
 582          * resets NAND flash controller in zero time ? I dont know.
 583          */
 584         target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN);
 585         work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */
 586         if (target->endianness == TARGET_BIG_ENDIAN) {
 587                 LOG_DEBUG("MX2_NF : work in Big Endian mode");
 588                 work_mode |= MX2_NF_BIT_BE_EN;
 589         } else {
 590                 LOG_DEBUG("MX2_NF : work in Little Endian mode");
 591         }
 592         if (mx2_nf_info->flags.hw_ecc_enabled) {
 593                 LOG_DEBUG("MX2_NF : work with ECC mode");
 594                 work_mode |= MX2_NF_BIT_ECC_EN;
 595         } else {
 596                 LOG_DEBUG("MX2_NF : work without ECC mode");
 597         }
 598         target_write_u16(target, MX2_NF_CFG1, work_mode);
 599         /*
 600          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 601          */
 602         target_write_u16(target, MX2_NF_BUFCFG, 2);
 603         target_read_u16(target, MX2_NF_FWP, &temp);
 604         if ((temp & 0x0007) == 1) {
 605                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 606                 return ERROR_FAIL;
 607         }
 608
 609         /*
 610          * unlock NAND flash for write
 611          */
 612         target_write_u16(target, MX2_NF_FWP, 4);
 613         target_write_u16(target, MX2_NF_LOCKSTART, 0x0000);
 614         target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF);
 615         /*
 616          * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
 617          */
 618         target_write_u16(target, MX2_NF_BUFADDR, 0x0000);
 619         /*
 620          * address of SRAM buffer
 621          */
 622         in_sram_address = MX2_NF_MAIN_BUFFER0;
 623         sign_of_sequental_byte_read = 0;
 624         return ERROR_OK;
 625 }
 626
 627 static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value)
 628 {
 629         static uint8_t even_byte = 0;
 630         uint16_t temp;
 631         /*
 632          * host-big_endian ??
 633          */
 634         if (sign_of_sequental_byte_read == 0)
 635                 even_byte = 0;
 636
 637         if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
 638                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 639                 *value = 0;
 640                 sign_of_sequental_byte_read = 0;
 641                 even_byte = 0;
 642                 return ERROR_NAND_OPERATION_FAILED;
 643         } else {
 644                 target_read_u16(target, in_sram_address, &temp);
 645                 if (even_byte) {
 646                         *value = temp >> 8;
 647                         even_byte = 0;
 648                         in_sram_address += 2;
 649                 } else {
 650                         *value = temp & 0xff;
 651                         even_byte = 1;
 652                 }
 653         }
 654         sign_of_sequental_byte_read = 1;
 655         return ERROR_OK;
 656 }
 657
 658 static int get_next_halfword_from_sram_buffer(struct target * target,
 659                                                uint16_t * value)
 660 {
 661         if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
 662                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 663                 *value = 0;
 664                 return ERROR_NAND_OPERATION_FAILED;
 665         } else {
 666                 target_read_u16(target, in_sram_address, value);
 667                 in_sram_address += 2;
 668         }
 669         return ERROR_OK;
 670 }
 671
 672 static int poll_for_complete_op(struct target * target, const char *text)
 673 {
 674         uint16_t poll_complete_status;
 675         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
 676                 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
 677                 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
 678                         break;
 679
 680                 usleep(10);
 681         }
 682         if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) {
 683                 LOG_ERROR("%s sending timeout", text);
 684                 return ERROR_NAND_OPERATION_FAILED;
 685         }
 686         return ERROR_OK;
 687 }
 688
 689 static int validate_target_state(struct nand_device *nand)
 690 {
 691         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 692         struct target *target = mx2_nf_info->target;
 693
 694         if (target->state != TARGET_HALTED) {
 695                 LOG_ERROR(target_not_halted_err_msg);
 696                 return ERROR_NAND_OPERATION_FAILED;
 697         }
 698
 699         if (mx2_nf_info->flags.target_little_endian !=
 700              (target->endianness == TARGET_LITTLE_ENDIAN)) {
 701                 /*
 702                  * endianness changed after NAND controller probed
 703                  */
 704                 return ERROR_NAND_OPERATION_FAILED;
 705         }
 706         return ERROR_OK;
 707 }
 708
 709 static int do_data_output(struct nand_device *nand)
 710 {
 711         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 712         struct target *target = mx2_nf_info->target;
 713         int poll_result;
 714         uint16_t ecc_status;
 715         switch(mx2_nf_info->fin) {
 716         case MX2_NF_FIN_DATAOUT:
 717                 /*
 718                  * start data output operation (set MX2_NF_BIT_OP_DONE==0)
 719                  */
 720                 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype));
 721                 poll_result = poll_for_complete_op(target, "data output");
 722                 if (poll_result != ERROR_OK)
 723                         return poll_result;
 724
 725                 mx2_nf_info->fin = MX2_NF_FIN_NONE;
 726                 /*
 727                  * ECC stuff
 728                  */
 729                 if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) {
 730                         target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status);
 731                         switch(ecc_status & 0x000c) {
 732                         case 1 << 2:
 733                                 LOG_INFO("main area readed with 1 (correctable) error");
 734                                 break;
 735                         case 2 << 2:
 736                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 737                                 return ERROR_NAND_OPERATION_FAILED;
 738                                 break;
 739                         }
 740                         switch(ecc_status & 0x0003) {
 741                         case 1:
 742                                 LOG_INFO("spare area readed with 1 (correctable) error");
 743                                 break;
 744                         case 2:
 745                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 746                                 return ERROR_NAND_OPERATION_FAILED;
 747                                 break;
 748                         }
 749                 }
 750                 break;
 751         case MX2_NF_FIN_NONE:
 752                 break;
 753         }
 754         return ERROR_OK;
 755 }
 756
 757 struct nand_flash_controller imx27_nand_flash_controller = {
 758         .name                   = "imx27",
 759         .nand_device_command    = &imx27_nand_device_command,
 760         .init                   = &imx27_init,
 761         .reset                  = &imx27_reset,
 762         .command                = &imx27_command,
 763         .address                = &imx27_address,
 764         .write_data             = &imx27_write_data,
 765         .read_data              = &imx27_read_data,
 766         .write_page             = &imx27_write_page,
 767         .read_page              = &imx27_read_page,
 768         .nand_ready             = &imx27_nand_ready,
 769 };