git.sur5r.net Git - openocd/blob - src/flash/nand/mx2.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 /*
  26  * Freescale iMX2* OpenOCD NAND Flash controller support.
  27  * based on Freescale iMX3* OpenOCD NAND Flash controller support.
  28  */
  29
  30 /*
  31  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
  32  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  33  * "nand write # file 0", "nand verify"
  34  *
  35  * get_next_halfword_from_sram_buffer() not tested
  36  * !! all function only tested with 2k page nand device; imx27_write_page
  37  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  38  * !! oob must be be used due to NFS bug
  39 */
  40 #ifdef HAVE_CONFIG_H
  41 #include "config.h"
  42 #endif
  43
  44 #include "imp.h"
  45 #include "mx2.h"
  46 #include <target/target.h>
  47
  48 /* This permits to print (in LOG_INFO) how much bytes
  49  * has been written after a page read or write.
  50  * This is useful when OpenOCD is used with a graphical
  51  * front-end to estimate progression of the global read/write
  52  */
  53 #undef _MX2_PRINT_STAT
  54 //#define _MX2_PRINT_STAT
  55
  56 static const char target_not_halted_err_msg[] =
  57         "target must be halted to use mx2 NAND flash controller";
  58 static const char data_block_size_err_msg[] =
  59         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  60 static const char sram_buffer_bounds_err_msg[] =
  61         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  62 static const char get_status_register_err_msg[] = "can't get NAND status";
  63 static uint32_t in_sram_address;
  64 unsigned char sign_of_sequental_byte_read;
  65
  66 static int initialize_nf_controller(struct nand_device *nand);
  67 static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value);
  68 static int get_next_halfword_from_sram_buffer(struct target * target,
  69                                                uint16_t * value);
  70 static int poll_for_complete_op(struct target * target, const char *text);
  71 static int validate_target_state(struct nand_device *nand);
  72 static int do_data_output(struct nand_device *nand);
  73
  74 static int imx27_command(struct nand_device *nand, uint8_t command);
  75 static int imx27_address(struct nand_device *nand, uint8_t address);
  76 static int imx27_controller_ready(struct nand_device *nand, int tout);
  77
  78 NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
  79 {
  80         struct mx2_nf_controller *mx2_nf_info;
  81         int hwecc_needed;
  82         int x;
  83         mx2_nf_info = malloc(sizeof(struct mx2_nf_controller));
  84         if (mx2_nf_info == NULL) {
  85                 LOG_ERROR("no memory for nand controller");
  86                 return ERROR_FAIL;
  87         }
  88
  89         nand->controller_priv = mx2_nf_info;
  90         mx2_nf_info->target = get_target(CMD_ARGV[1]);
  91         if (mx2_nf_info->target == NULL) {
  92                 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
  93                 return ERROR_FAIL;
  94         }
  95         if (CMD_ARGC < 3) {
  96                 LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
  97                 return ERROR_FAIL;
  98         }
  99         /*
 100          * check hwecc requirements
 101          */
 102
 103         hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
 104         if (hwecc_needed == 0)
 105                 mx2_nf_info->flags.hw_ecc_enabled = 1;
 106         else
 107                 mx2_nf_info->flags.hw_ecc_enabled = 0;
 108
 109         mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
 110         mx2_nf_info->fin = MX2_NF_FIN_NONE;
 111         mx2_nf_info->flags.target_little_endian =
 112         (mx2_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
 113         /*
 114          * testing host endianess
 115          */
 116         x = 1;
 117         if (*(char *) &x == 1)
 118                 mx2_nf_info->flags.host_little_endian = 1;
 119         else
 120                 mx2_nf_info->flags.host_little_endian = 0;
 121         return ERROR_OK;
 122 }
 123
 124 static int imx27_init(struct nand_device *nand)
 125 {
 126         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 127         struct target *target = mx2_nf_info->target;
 128
 129         int validate_target_result;
 130         uint16_t buffsize_register_content;
 131         uint32_t pcsr_register_content;
 132         int retval;
 133         uint16_t nand_status_content;
 134         /*
 135          * validate target state
 136          */
 137         validate_target_result = validate_target_state(nand);
 138         if (validate_target_result != ERROR_OK)
 139                 return validate_target_result;
 140
 141         target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content);
 142         mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 143
 144         target_read_u32(target, MX2_FMCR, &pcsr_register_content);
 145         if (!nand->bus_width) {
 146                 /* bus_width not yet defined. Read it from MX2_FMCR */
 147                 nand->bus_width =
 148                     (pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8;
 149         } else {
 150                 /* bus_width forced in soft. Sync it to MX2_FMCR */
 151                 pcsr_register_content |=
 152                     ((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000);
 153                 target_write_u32(target, MX2_FMCR, pcsr_register_content);
 154         }
 155         if (nand->bus_width == 16)
 156                 LOG_DEBUG("MX2_NF : bus is 16-bit width");
 157         else
 158                 LOG_DEBUG("MX2_NF : bus is 8-bit width");
 159
 160         if (!nand->page_size) {
 161                 nand->page_size =
 162                     (pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512;
 163         } else {
 164                 pcsr_register_content |=
 165                     ((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000);
 166                 target_write_u32(target, MX2_FMCR, pcsr_register_content);
 167         }
 168         if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 169                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 170                           "pagesize 2048 is incompatible with it");
 171         } else {
 172                 LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
 173         }
 174
 175         initialize_nf_controller(nand);
 176
 177         retval = ERROR_OK;
 178         retval |= imx27_command(nand, NAND_CMD_STATUS);
 179         retval |= imx27_address(nand, 0x00);
 180         retval |= do_data_output(nand);
 181         if (retval != ERROR_OK) {
 182                 LOG_ERROR(get_status_register_err_msg);
 183                 return ERROR_FAIL;
 184         }
 185         target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
 186         if (!(nand_status_content & 0x0080)) {
 187                 LOG_INFO("NAND read-only");
 188                 mx2_nf_info->flags.nand_readonly = 1;
 189         } else {
 190                 mx2_nf_info->flags.nand_readonly = 0;
 191         }
 192         return ERROR_OK;
 193 }
 194
 195 static int imx27_read_data(struct nand_device *nand, void *data)
 196 {
 197         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 198         struct target *target = mx2_nf_info->target;
 199         int validate_target_result;
 200         int try_data_output_from_nand_chip;
 201         /*
 202          * validate target state
 203          */
 204         validate_target_result = validate_target_state(nand);
 205         if (validate_target_result != ERROR_OK)
 206                 return validate_target_result;
 207
 208         /*
 209          * get data from nand chip
 210          */
 211         try_data_output_from_nand_chip = do_data_output(nand);
 212         if (try_data_output_from_nand_chip != ERROR_OK) {
 213                 LOG_ERROR("imx27_read_data : read data failed : '%x'",
 214                           try_data_output_from_nand_chip);
 215                 return try_data_output_from_nand_chip;
 216         }
 217
 218         if (nand->bus_width == 16)
 219             get_next_halfword_from_sram_buffer(target, data);
 220         else
 221             get_next_byte_from_sram_buffer(target, data);
 222
 223         return ERROR_OK;
 224 }
 225
 226 static int imx27_write_data(struct nand_device *nand, uint16_t data)
 227 {
 228         LOG_ERROR("write_data() not implemented");
 229         return ERROR_NAND_OPERATION_FAILED;
 230 }
 231
 232 static int imx27_nand_ready(struct nand_device *nand, int timeout)
 233 {
 234         return imx27_controller_ready(nand, timeout);
 235 }
 236
 237 static int imx27_reset(struct nand_device *nand)
 238 {
 239         /*
 240          * validate target state
 241          */
 242         int validate_target_result;
 243         validate_target_result = validate_target_state(nand);
 244         if (validate_target_result != ERROR_OK)
 245             return validate_target_result;
 246         initialize_nf_controller(nand);
 247         return ERROR_OK;
 248 }
 249
 250 static int imx27_command(struct nand_device *nand, uint8_t command)
 251 {
 252         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 253         struct target *target = mx2_nf_info->target;
 254         int validate_target_result;
 255         int poll_result;
 256         /*
 257          * validate target state
 258          */
 259         validate_target_result = validate_target_state(nand);
 260         if (validate_target_result != ERROR_OK)
 261                 return validate_target_result;
 262
 263         switch(command) {
 264         case NAND_CMD_READOOB:
 265                 command = NAND_CMD_READ0;
 266                 /* set read point for data_read() and read_block_data() to
 267                  * spare area in SRAM buffer
 268                  */
 269                 in_sram_address = MX2_NF_SPARE_BUFFER0;
 270                 break;
 271         case NAND_CMD_READ1:
 272                 command = NAND_CMD_READ0;
 273                 /*
 274                  * offset == one half of page size
 275                  */
 276                 in_sram_address =
 277                     MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 278                 break;
 279         default:
 280                 in_sram_address = MX2_NF_MAIN_BUFFER0;
 281                 break;
 282         }
 283
 284         target_write_u16(target, MX2_NF_FCMD, command);
 285         /*
 286          * start command input operation (set MX2_NF_BIT_OP_DONE==0)
 287          */
 288         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI);
 289         poll_result = poll_for_complete_op(target, "command");
 290         if (poll_result != ERROR_OK)
 291                 return poll_result;
 292         /*
 293          * reset cursor to begin of the buffer
 294          */
 295         sign_of_sequental_byte_read = 0;
 296         /* Handle special read command and adjust NF_CFG2(FDO) */
 297         switch(command) {
 298         case NAND_CMD_READID:
 299                 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID;
 300                 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 301                 break;
 302         case NAND_CMD_STATUS:
 303                 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
 304                 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 305                 target_write_u16 (target, MX2_NF_BUFADDR, 0);
 306                 in_sram_address = 0;
 307                 break;
 308         case NAND_CMD_READ0:
 309                 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 310                 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
 311                 break;
 312         default:
 313                 /* Ohter command use the default 'One page data out' FDO */
 314                 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
 315                 break;
 316         }
 317         return ERROR_OK;
 318 }
 319
 320 static int imx27_address(struct nand_device *nand, uint8_t address)
 321 {
 322         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 323         struct target *target = mx2_nf_info->target;
 324         int validate_target_result;
 325         int poll_result;
 326         /*
 327          * validate target state
 328          */
 329         validate_target_result = validate_target_state(nand);
 330         if (validate_target_result != ERROR_OK)
 331                 return validate_target_result;
 332
 333         target_write_u16(target, MX2_NF_FADDR, address);
 334         /*
 335          * start address input operation (set MX2_NF_BIT_OP_DONE==0)
 336          */
 337         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI);
 338         poll_result = poll_for_complete_op(target, "address");
 339         if (poll_result != ERROR_OK)
 340                 return poll_result;
 341
 342         return ERROR_OK;
 343 }
 344
 345 static int imx27_controller_ready(struct nand_device *nand, int tout)
 346 {
 347         uint16_t poll_complete_status;
 348         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 349         struct target *target = mx2_nf_info->target;
 350         int validate_target_result;
 351
 352         /*
 353          * validate target state
 354          */
 355         validate_target_result = validate_target_state(nand);
 356         if (validate_target_result != ERROR_OK)
 357                 return validate_target_result;
 358
 359         do {
 360                 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
 361                 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
 362                         return tout;
 363
 364                 alive_sleep(1);
 365         }
 366         while (tout-- > 0);
 367         return tout;
 368 }
 369
 370 static int imx27_write_page(struct nand_device *nand, uint32_t page,
 371                              uint8_t * data, uint32_t data_size, uint8_t * oob,
 372                              uint32_t oob_size)
 373 {
 374         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 375         struct target *target = mx2_nf_info->target;
 376         int retval;
 377         uint16_t nand_status_content;
 378         uint16_t swap1, swap2, new_swap1;
 379         int poll_result;
 380         if (data_size % 2) {
 381                 LOG_ERROR(data_block_size_err_msg, data_size);
 382                 return ERROR_NAND_OPERATION_FAILED;
 383         }
 384         if (oob_size % 2) {
 385                 LOG_ERROR(data_block_size_err_msg, oob_size);
 386                 return ERROR_NAND_OPERATION_FAILED;
 387         }
 388         if (!data) {
 389                 LOG_ERROR("nothing to program");
 390                 return ERROR_NAND_OPERATION_FAILED;
 391         }
 392         /*
 393          * validate target state
 394          */
 395         retval = validate_target_state(nand);
 396         if (retval != ERROR_OK)
 397                 return retval;
 398
 399         in_sram_address = MX2_NF_MAIN_BUFFER0;
 400         sign_of_sequental_byte_read = 0;
 401         retval = ERROR_OK;
 402         retval |= imx27_command(nand, NAND_CMD_SEQIN);
 403         retval |= imx27_address(nand, 0); //col
 404         retval |= imx27_address(nand, 0); //col
 405         retval |= imx27_address(nand, page & 0xff); //page address
 406         retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
 407         retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
 408
 409         target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
 410         if (oob) {
 411                 if (mx2_nf_info->flags.hw_ecc_enabled) {
 412                         /*
 413                          * part of spare block will be overrided by hardware
 414                          * ECC generator
 415                          */
 416                         LOG_DEBUG("part of spare block will be overrided "
 417                                   "by hardware ECC generator");
 418                 }
 419                 target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
 420                                     oob);
 421         }
 422         //BI-swap -  work-around of imx27 NFC for NAND device with page == 2kb
 423         target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
 424         if (oob) {
 425                 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
 426                           "in mx2 driver");
 427                 return ERROR_NAND_OPERATION_FAILED;
 428         }
 429         //target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
 430         swap2 = 0xffff;  //Spare buffer unused forced to 0xffff
 431         new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 432         swap2 = (swap1 << 8) | (swap2 & 0xFF);
 433
 434         target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
 435         target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
 436         /*
 437          * start data input operation (set MX2_NF_BIT_OP_DONE==0)
 438          */
 439         target_write_u16(target, MX2_NF_BUFADDR, 0);
 440         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 441         poll_result = poll_for_complete_op(target, "data input");
 442         if (poll_result != ERROR_OK)
 443                 return poll_result;
 444
 445         target_write_u16(target, MX2_NF_BUFADDR, 1);
 446         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 447         poll_result = poll_for_complete_op(target, "data input");
 448         if (poll_result != ERROR_OK)
 449                 return poll_result;
 450
 451         target_write_u16(target, MX2_NF_BUFADDR, 2);
 452         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 453         poll_result = poll_for_complete_op(target, "data input");
 454         if (poll_result != ERROR_OK)
 455                 return poll_result;
 456
 457         target_write_u16(target, MX2_NF_BUFADDR, 3);
 458         target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
 459         poll_result = poll_for_complete_op(target, "data input");
 460         if (poll_result != ERROR_OK)
 461                 return poll_result;
 462
 463         retval |= imx27_command(nand, NAND_CMD_PAGEPROG);
 464         if (retval != ERROR_OK)
 465                 return retval;
 466
 467         /*
 468          * check status register
 469          */
 470         retval = ERROR_OK;
 471         retval |= imx27_command(nand, NAND_CMD_STATUS);
 472         target_write_u16 (target, MX2_NF_BUFADDR, 0);
 473         mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
 474         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 475         retval |= do_data_output(nand);
 476         if (retval != ERROR_OK) {
 477                 LOG_ERROR (get_status_register_err_msg);
 478                 return retval;
 479         }
 480         target_read_u16 (target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
 481         if (nand_status_content & 0x0001) {
 482                 /*
 483                  * page not correctly written
 484                  */
 485                 return ERROR_NAND_OPERATION_FAILED;
 486         }
 487 #ifdef _MX2_PRINT_STAT
 488         LOG_INFO("%d bytes newly written", data_size);
 489 #endif
 490         return ERROR_OK;
 491 }
 492
 493 static int imx27_read_page(struct nand_device *nand, uint32_t page,
 494                             uint8_t * data, uint32_t data_size, uint8_t * oob,
 495                             uint32_t oob_size)
 496 {
 497         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 498         struct target *target = mx2_nf_info->target;
 499         int retval;
 500         uint16_t swap1, swap2, new_swap1;
 501         if (data_size % 2) {
 502             LOG_ERROR(data_block_size_err_msg, data_size);
 503             return ERROR_NAND_OPERATION_FAILED;
 504         }
 505         if (oob_size % 2) {
 506             LOG_ERROR(data_block_size_err_msg, oob_size);
 507             return ERROR_NAND_OPERATION_FAILED;
 508         }
 509
 510         /*
 511          * validate target state
 512          */
 513         retval = validate_target_state(nand);
 514         if (retval != ERROR_OK) {
 515                 return retval;
 516         }
 517         /* Reset address_cycles before imx27_command ?? */
 518         retval = ERROR_OK;
 519         retval |= imx27_command(nand, NAND_CMD_READ0);
 520
 521         retval |= imx27_address(nand, 0); //col
 522         retval |= imx27_address(nand, 0); //col
 523         retval |= imx27_address(nand, page & 0xff); //page address
 524         retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
 525         retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
 526         retval |= imx27_command(nand, NAND_CMD_READSTART);
 527
 528         target_write_u16(target, MX2_NF_BUFADDR, 0);
 529         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 530         retval = do_data_output(nand);
 531         if (retval != ERROR_OK) {
 532                 LOG_ERROR("MX2_NF : Error reading page 0");
 533                 return retval;
 534         }
 535         //Test nand page size to know how much MAIN_BUFFER must be written
 536         target_write_u16(target, MX2_NF_BUFADDR, 1);
 537         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 538         retval = do_data_output(nand);
 539         if (retval != ERROR_OK) {
 540                 LOG_ERROR("MX2_NF : Error reading page 1");
 541                 return retval;
 542         }
 543         target_write_u16(target, MX2_NF_BUFADDR, 2);
 544         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 545         retval = do_data_output(nand);
 546         if (retval != ERROR_OK) {
 547                 LOG_ERROR("MX2_NF : Error reading page 2");
 548                 return retval;
 549         }
 550         target_write_u16(target, MX2_NF_BUFADDR, 3);
 551         mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
 552         retval = do_data_output(nand);
 553         if (retval != ERROR_OK) {
 554                 LOG_ERROR("MX2_NF : Error reading page 3");
 555                 return retval;
 556         }
 557         //BI-swap -  work-around of imx27 NFC for NAND device with page == 2k
 558         target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
 559         target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
 560         new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 561         swap2 = (swap1 << 8) | (swap2 & 0xFF);
 562         target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
 563         target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
 564
 565         if (data)
 566                 target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
 567         if (oob)
 568                 target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
 569                                     oob);
 570 #ifdef _MX2_PRINT_STAT
 571         if (data_size > 0) {
 572                 /* When Operation Status is read (when page is erased),
 573                  * this function is used but data_size is null.
 574                  */
 575                 LOG_INFO("%d bytes newly read", data_size);
 576         }
 577 #endif
 578         return ERROR_OK;
 579 }
 580
 581 static int initialize_nf_controller(struct nand_device *nand)
 582 {
 583         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 584         struct target *target = mx2_nf_info->target;
 585         uint16_t work_mode;
 586         uint16_t temp;
 587         /*
 588          * resets NAND flash controller in zero time ? I dont know.
 589          */
 590         target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN);
 591         work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */
 592         if (target->endianness == TARGET_BIG_ENDIAN) {
 593                 LOG_DEBUG("MX2_NF : work in Big Endian mode");
 594                 work_mode |= MX2_NF_BIT_BE_EN;
 595         } else {
 596                 LOG_DEBUG("MX2_NF : work in Little Endian mode");
 597         }
 598         if (mx2_nf_info->flags.hw_ecc_enabled) {
 599                 LOG_DEBUG("MX2_NF : work with ECC mode");
 600                 work_mode |= MX2_NF_BIT_ECC_EN;
 601         } else {
 602                 LOG_DEBUG("MX2_NF : work without ECC mode");
 603         }
 604         target_write_u16(target, MX2_NF_CFG1, work_mode);
 605         /*
 606          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 607          */
 608         target_write_u16(target, MX2_NF_BUFCFG, 2);
 609         target_read_u16(target, MX2_NF_FWP, &temp);
 610         if ((temp & 0x0007) == 1) {
 611                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 612                 return ERROR_FAIL;
 613         }
 614
 615         /*
 616          * unlock NAND flash for write
 617          */
 618         target_write_u16(target, MX2_NF_FWP, 4);
 619         target_write_u16(target, MX2_NF_LOCKSTART, 0x0000);
 620         target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF);
 621         /*
 622          * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
 623          */
 624         target_write_u16(target, MX2_NF_BUFADDR, 0x0000);
 625         /*
 626          * address of SRAM buffer
 627          */
 628         in_sram_address = MX2_NF_MAIN_BUFFER0;
 629         sign_of_sequental_byte_read = 0;
 630         return ERROR_OK;
 631 }
 632
 633 static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value)
 634 {
 635         static uint8_t even_byte = 0;
 636         uint16_t temp;
 637         /*
 638          * host-big_endian ??
 639          */
 640         if (sign_of_sequental_byte_read == 0)
 641                 even_byte = 0;
 642
 643         if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
 644                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 645                 *value = 0;
 646                 sign_of_sequental_byte_read = 0;
 647                 even_byte = 0;
 648                 return ERROR_NAND_OPERATION_FAILED;
 649         } else {
 650                 target_read_u16(target, in_sram_address, &temp);
 651                 if (even_byte) {
 652                         *value = temp >> 8;
 653                         even_byte = 0;
 654                         in_sram_address += 2;
 655                 } else {
 656                         *value = temp & 0xff;
 657                         even_byte = 1;
 658                 }
 659         }
 660         sign_of_sequental_byte_read = 1;
 661         return ERROR_OK;
 662 }
 663
 664 static int get_next_halfword_from_sram_buffer(struct target * target,
 665                                                uint16_t * value)
 666 {
 667         if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
 668                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 669                 *value = 0;
 670                 return ERROR_NAND_OPERATION_FAILED;
 671         } else {
 672                 target_read_u16(target, in_sram_address, value);
 673                 in_sram_address += 2;
 674         }
 675         return ERROR_OK;
 676 }
 677
 678 static int poll_for_complete_op(struct target * target, const char *text)
 679 {
 680         uint16_t poll_complete_status;
 681         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
 682                 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
 683                 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
 684                         break;
 685
 686                 usleep(10);
 687         }
 688         if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) {
 689                 LOG_ERROR("%s sending timeout", text);
 690                 return ERROR_NAND_OPERATION_FAILED;
 691         }
 692         return ERROR_OK;
 693 }
 694
 695 static int validate_target_state(struct nand_device *nand)
 696 {
 697         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 698         struct target *target = mx2_nf_info->target;
 699
 700         if (target->state != TARGET_HALTED) {
 701                 LOG_ERROR(target_not_halted_err_msg);
 702                 return ERROR_NAND_OPERATION_FAILED;
 703         }
 704
 705         if (mx2_nf_info->flags.target_little_endian !=
 706              (target->endianness == TARGET_LITTLE_ENDIAN)) {
 707                 /*
 708                  * endianness changed after NAND controller probed
 709                  */
 710                 return ERROR_NAND_OPERATION_FAILED;
 711         }
 712         return ERROR_OK;
 713 }
 714
 715 static int do_data_output(struct nand_device *nand)
 716 {
 717         struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
 718         struct target *target = mx2_nf_info->target;
 719         int poll_result;
 720         uint16_t ecc_status;
 721         switch(mx2_nf_info->fin) {
 722         case MX2_NF_FIN_DATAOUT:
 723                 /*
 724                  * start data output operation (set MX2_NF_BIT_OP_DONE==0)
 725                  */
 726                 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype));
 727                 poll_result = poll_for_complete_op(target, "data output");
 728                 if (poll_result != ERROR_OK)
 729                         return poll_result;
 730
 731                 mx2_nf_info->fin = MX2_NF_FIN_NONE;
 732                 /*
 733                  * ECC stuff
 734                  */
 735                 if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) {
 736                         target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status);
 737                         switch(ecc_status & 0x000c) {
 738                         case 1 << 2:
 739                                 LOG_INFO("main area readed with 1 (correctable) error");
 740                                 break;
 741                         case 2 << 2:
 742                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 743                                 return ERROR_NAND_OPERATION_FAILED;
 744                                 break;
 745                         }
 746                         switch(ecc_status & 0x0003) {
 747                         case 1:
 748                                 LOG_INFO("spare area readed with 1 (correctable) error");
 749                                 break;
 750                         case 2:
 751                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 752                                 return ERROR_NAND_OPERATION_FAILED;
 753                                 break;
 754                         }
 755                 }
 756                 break;
 757         case MX2_NF_FIN_NONE:
 758                 break;
 759         }
 760         return ERROR_OK;
 761 }
 762
 763 struct nand_flash_controller imx27_nand_flash_controller = {
 764         .name                   = "imx27",
 765         .nand_device_command    = &imx27_nand_device_command,
 766         .init                   = &imx27_init,
 767         .reset                  = &imx27_reset,
 768         .command                = &imx27_command,
 769         .address                = &imx27_address,
 770         .write_data             = &imx27_write_data,
 771         .read_data              = &imx27_read_data,
 772         .write_page             = &imx27_write_page,
 773         .read_page              = &imx27_read_page,
 774         .controller_ready       = &imx27_controller_ready,
 775         .nand_ready             = &imx27_nand_ready,
 776 };