2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
22 * Freescale iMX3* OpenOCD NAND Flash controller support.
24 * Many thanks to Ben Dooks for writing s3c24xx driver.
28 driver tested with STMicro NAND512W3A @imx31
29 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
30 get_next_halfword_from_sram_buffer() not tested
38 #include <target/target.h>
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %" PRId32 " is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
46 static const char get_status_register_err_msg[] = "can't get NAND status";
47 static uint32_t in_sram_address;
48 static unsigned char sign_of_sequental_byte_read;
50 static int test_iomux_settings(struct target *target, uint32_t value,
51 uint32_t mask, const char *text);
52 static int initialize_nf_controller(struct nand_device *nand);
53 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
54 static int get_next_halfword_from_sram_buffer(struct target *target,
56 static int poll_for_complete_op(struct target *target, const char *text);
57 static int validate_target_state(struct nand_device *nand);
58 static int do_data_output(struct nand_device *nand);
60 static int imx31_command(struct nand_device *nand, uint8_t command);
61 static int imx31_address(struct nand_device *nand, uint8_t address);
63 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
65 struct mx3_nf_controller *mx3_nf_info;
66 mx3_nf_info = malloc(sizeof(struct mx3_nf_controller));
67 if (mx3_nf_info == NULL) {
68 LOG_ERROR("no memory for nand controller");
72 nand->controller_priv = mx3_nf_info;
75 return ERROR_COMMAND_SYNTAX_ERROR;
77 * check hwecc requirements
81 hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
82 if (hwecc_needed == 0)
83 mx3_nf_info->flags.hw_ecc_enabled = 1;
85 mx3_nf_info->flags.hw_ecc_enabled = 0;
88 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
89 mx3_nf_info->fin = MX3_NF_FIN_NONE;
90 mx3_nf_info->flags.target_little_endian =
91 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
96 static int imx31_init(struct nand_device *nand)
98 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
99 struct target *target = nand->target;
103 * validate target state
105 int validate_target_result;
106 validate_target_result = validate_target_state(nand);
107 if (validate_target_result != ERROR_OK)
108 return validate_target_result;
112 uint16_t buffsize_register_content;
113 target_read_u16(target, MX3_NF_BUFSIZ, &buffsize_register_content);
114 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
118 uint32_t pcsr_register_content;
119 target_read_u32(target, MX3_PCSR, &pcsr_register_content);
120 if (!nand->bus_width) {
121 nand->bus_width = (pcsr_register_content & 0x80000000) ? 16 : 8;
123 pcsr_register_content |= ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
124 target_write_u32(target, MX3_PCSR, pcsr_register_content);
127 if (!nand->page_size) {
128 nand->page_size = (pcsr_register_content & 0x40000000) ? 2048 : 512;
130 pcsr_register_content |= ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
131 target_write_u32(target, MX3_PCSR, pcsr_register_content);
133 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
134 LOG_ERROR("NAND controller have only 1 kb SRAM, "
135 "so pagesize 2048 is incompatible with it");
140 uint32_t cgr_register_content;
141 target_read_u32(target, MX3_CCM_CGR2, &cgr_register_content);
142 if (!(cgr_register_content & 0x00000300)) {
143 LOG_ERROR("clock gating to EMI disabled");
149 uint32_t gpr_register_content;
150 target_read_u32(target, MX3_GPR, &gpr_register_content);
151 if (gpr_register_content & 0x00000060) {
152 LOG_ERROR("pins mode overrided by GPR");
159 * testing IOMUX settings; must be in "functional-mode output and
160 * functional-mode input" mode
163 test_iomux = ERROR_OK;
164 test_iomux |= test_iomux_settings(target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
165 test_iomux |= test_iomux_settings(target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
166 test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x0000007f, "d7");
167 if (nand->bus_width == 16) {
168 test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x7f7f7f00, "d8,d9,d10");
169 test_iomux |= test_iomux_settings(target, 0x43fac0cc, 0x7f7f7f7f, "d11,d12,d13,d14");
170 test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x0000007f, "d15");
172 test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x7f7f7f00, "nfwp,nfce,nfrb");
173 test_iomux |= test_iomux_settings(target, 0x43fac0d4, 0x7f7f7f7f,
174 "nfwe,nfre,nfale,nfcle");
175 if (test_iomux != ERROR_OK)
179 initialize_nf_controller(nand);
183 uint16_t nand_status_content;
185 retval |= imx31_command(nand, NAND_CMD_STATUS);
186 retval |= imx31_address(nand, 0x00);
187 retval |= do_data_output(nand);
188 if (retval != ERROR_OK) {
189 LOG_ERROR(get_status_register_err_msg);
192 target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
193 if (!(nand_status_content & 0x0080)) {
195 * is host-big-endian correctly ??
197 LOG_INFO("NAND read-only");
198 mx3_nf_info->flags.nand_readonly = 1;
200 mx3_nf_info->flags.nand_readonly = 0;
205 static int imx31_read_data(struct nand_device *nand, void *data)
207 struct target *target = nand->target;
210 * validate target state
212 int validate_target_result;
213 validate_target_result = validate_target_state(nand);
214 if (validate_target_result != ERROR_OK)
215 return validate_target_result;
220 * get data from nand chip
222 int try_data_output_from_nand_chip;
223 try_data_output_from_nand_chip = do_data_output(nand);
224 if (try_data_output_from_nand_chip != ERROR_OK)
225 return try_data_output_from_nand_chip;
228 if (nand->bus_width == 16)
229 get_next_halfword_from_sram_buffer(target, data);
231 get_next_byte_from_sram_buffer(target, data);
236 static int imx31_write_data(struct nand_device *nand, uint16_t data)
238 LOG_ERROR("write_data() not implemented");
239 return ERROR_NAND_OPERATION_FAILED;
242 static int imx31_reset(struct nand_device *nand)
245 * validate target state
247 int validate_target_result;
248 validate_target_result = validate_target_state(nand);
249 if (validate_target_result != ERROR_OK)
250 return validate_target_result;
251 initialize_nf_controller(nand);
255 static int imx31_command(struct nand_device *nand, uint8_t command)
257 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
258 struct target *target = nand->target;
261 * validate target state
263 int validate_target_result;
264 validate_target_result = validate_target_state(nand);
265 if (validate_target_result != ERROR_OK)
266 return validate_target_result;
270 case NAND_CMD_READOOB:
271 command = NAND_CMD_READ0;
272 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
274 * read_block_data() to
279 command = NAND_CMD_READ0;
281 * offset == one half of page size
283 in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
286 in_sram_address = MX3_NF_MAIN_BUFFER0;
289 target_write_u16(target, MX3_NF_FCMD, command);
291 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
293 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
296 poll_result = poll_for_complete_op(target, "command");
297 if (poll_result != ERROR_OK)
301 * reset cursor to begin of the buffer
303 sign_of_sequental_byte_read = 0;
305 case NAND_CMD_READID:
306 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
307 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
309 case NAND_CMD_STATUS:
310 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
311 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
314 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
315 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
318 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
323 static int imx31_address(struct nand_device *nand, uint8_t address)
325 struct target *target = nand->target;
328 * validate target state
330 int validate_target_result;
331 validate_target_result = validate_target_state(nand);
332 if (validate_target_result != ERROR_OK)
333 return validate_target_result;
336 target_write_u16(target, MX3_NF_FADDR, address);
338 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
340 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
343 poll_result = poll_for_complete_op(target, "address");
344 if (poll_result != ERROR_OK)
350 static int imx31_nand_ready(struct nand_device *nand, int tout)
352 uint16_t poll_complete_status;
353 struct target *target = nand->target;
357 * validate target state
359 int validate_target_result;
360 validate_target_result = validate_target_state(nand);
361 if (validate_target_result != ERROR_OK)
362 return validate_target_result;
366 target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
367 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
370 } while (tout-- > 0);
374 static int imx31_write_page(struct nand_device *nand, uint32_t page,
375 uint8_t *data, uint32_t data_size, uint8_t *oob,
378 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
379 struct target *target = nand->target;
382 LOG_ERROR(data_block_size_err_msg, data_size);
383 return ERROR_NAND_OPERATION_FAILED;
386 LOG_ERROR(data_block_size_err_msg, oob_size);
387 return ERROR_NAND_OPERATION_FAILED;
390 LOG_ERROR("nothing to program");
391 return ERROR_NAND_OPERATION_FAILED;
395 * validate target state
398 retval = validate_target_state(nand);
399 if (retval != ERROR_OK)
403 int retval = ERROR_OK;
404 retval |= imx31_command(nand, NAND_CMD_SEQIN);
405 retval |= imx31_address(nand, 0x00);
406 retval |= imx31_address(nand, page & 0xff);
407 retval |= imx31_address(nand, (page >> 8) & 0xff);
408 if (nand->address_cycles >= 4) {
409 retval |= imx31_address(nand, (page >> 16) & 0xff);
410 if (nand->address_cycles >= 5)
411 retval |= imx31_address(nand, (page >> 24) & 0xff);
413 target_write_buffer(target, MX3_NF_MAIN_BUFFER0, data_size, data);
415 if (mx3_nf_info->flags.hw_ecc_enabled) {
417 * part of spare block will be overrided by hardware
420 LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
422 target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
425 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
427 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
430 poll_result = poll_for_complete_op(target, "data input");
431 if (poll_result != ERROR_OK)
434 retval |= imx31_command(nand, NAND_CMD_PAGEPROG);
435 if (retval != ERROR_OK)
439 * check status register
442 uint16_t nand_status_content;
444 retval |= imx31_command(nand, NAND_CMD_STATUS);
445 retval |= imx31_address(nand, 0x00);
446 retval |= do_data_output(nand);
447 if (retval != ERROR_OK) {
448 LOG_ERROR(get_status_register_err_msg);
451 target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
452 if (nand_status_content & 0x0001) {
454 * is host-big-endian correctly ??
456 return ERROR_NAND_OPERATION_FAILED;
463 static int imx31_read_page(struct nand_device *nand, uint32_t page,
464 uint8_t *data, uint32_t data_size, uint8_t *oob,
467 struct target *target = nand->target;
470 LOG_ERROR(data_block_size_err_msg, data_size);
471 return ERROR_NAND_OPERATION_FAILED;
474 LOG_ERROR(data_block_size_err_msg, oob_size);
475 return ERROR_NAND_OPERATION_FAILED;
480 * validate target state
483 retval = validate_target_state(nand);
484 if (retval != ERROR_OK)
488 int retval = ERROR_OK;
489 retval |= imx31_command(nand, NAND_CMD_READ0);
490 retval |= imx31_address(nand, 0x00);
491 retval |= imx31_address(nand, page & 0xff);
492 retval |= imx31_address(nand, (page >> 8) & 0xff);
493 if (nand->address_cycles >= 4) {
494 retval |= imx31_address(nand, (page >> 16) & 0xff);
495 if (nand->address_cycles >= 5) {
496 retval |= imx31_address(nand, (page >> 24) & 0xff);
497 retval |= imx31_command(nand, NAND_CMD_READSTART);
500 retval |= do_data_output(nand);
501 if (retval != ERROR_OK)
505 target_read_buffer(target, MX3_NF_MAIN_BUFFER0, data_size,
509 target_read_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size,
516 static int test_iomux_settings(struct target *target, uint32_t address,
517 uint32_t mask, const char *text)
519 uint32_t register_content;
520 target_read_u32(target, address, ®ister_content);
521 if ((register_content & mask) != (0x12121212 & mask)) {
522 LOG_ERROR("IOMUX for {%s} is bad", text);
528 static int initialize_nf_controller(struct nand_device *nand)
530 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
531 struct target *target = nand->target;
533 * resets NAND flash controller in zero time ? I dont know.
535 target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
538 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
539 if (target->endianness == TARGET_BIG_ENDIAN)
540 work_mode |= MX3_NF_BIT_BE_EN;
541 if (mx3_nf_info->flags.hw_ecc_enabled)
542 work_mode |= MX3_NF_BIT_ECC_EN;
543 target_write_u16(target, MX3_NF_CFG1, work_mode);
546 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
548 target_write_u16(target, MX3_NF_BUFCFG, 2);
551 target_read_u16(target, MX3_NF_FWP, &temp);
552 if ((temp & 0x0007) == 1) {
553 LOG_ERROR("NAND flash is tight-locked, reset needed");
559 * unlock NAND flash for write
561 target_write_u16(target, MX3_NF_FWP, 4);
562 target_write_u16(target, MX3_NF_LOCKSTART, 0x0000);
563 target_write_u16(target, MX3_NF_LOCKEND, 0xFFFF);
565 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
567 target_write_u16(target, MX3_NF_BUFADDR, 0x0000);
569 * address of SRAM buffer
571 in_sram_address = MX3_NF_MAIN_BUFFER0;
572 sign_of_sequental_byte_read = 0;
576 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
578 static uint8_t even_byte;
582 if (sign_of_sequental_byte_read == 0)
584 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
585 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
587 sign_of_sequental_byte_read = 0;
589 return ERROR_NAND_OPERATION_FAILED;
592 target_read_u16(target, in_sram_address, &temp);
596 in_sram_address += 2;
598 *value = temp & 0xff;
602 sign_of_sequental_byte_read = 1;
606 static int get_next_halfword_from_sram_buffer(struct target *target,
609 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
610 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
612 return ERROR_NAND_OPERATION_FAILED;
614 target_read_u16(target, in_sram_address, value);
615 in_sram_address += 2;
620 static int poll_for_complete_op(struct target *target, const char *text)
622 uint16_t poll_complete_status;
623 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
625 target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
626 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
629 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE)) {
630 LOG_ERROR("%s sending timeout", text);
631 return ERROR_NAND_OPERATION_FAILED;
636 static int validate_target_state(struct nand_device *nand)
638 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
639 struct target *target = nand->target;
641 if (target->state != TARGET_HALTED) {
642 LOG_ERROR(target_not_halted_err_msg);
643 return ERROR_NAND_OPERATION_FAILED;
646 if (mx3_nf_info->flags.target_little_endian !=
647 (target->endianness == TARGET_LITTLE_ENDIAN)) {
649 * endianness changed after NAND controller probed
651 return ERROR_NAND_OPERATION_FAILED;
656 static int do_data_output(struct nand_device *nand)
658 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
659 struct target *target = nand->target;
660 switch (mx3_nf_info->fin) {
661 case MX3_NF_FIN_DATAOUT:
663 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
665 target_write_u16 (target, MX3_NF_CFG2,
666 MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
669 poll_result = poll_for_complete_op(target, "data output");
670 if (poll_result != ERROR_OK)
673 mx3_nf_info->fin = MX3_NF_FIN_NONE;
677 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
678 && mx3_nf_info->flags.hw_ecc_enabled) {
680 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
681 switch (ecc_status & 0x000c) {
683 LOG_DEBUG("main area readed with 1 (correctable) error");
686 LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
687 return ERROR_NAND_OPERATION_FAILED;
690 switch (ecc_status & 0x0003) {
692 LOG_DEBUG("spare area readed with 1 (correctable) error");
695 LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
696 return ERROR_NAND_OPERATION_FAILED;
701 case MX3_NF_FIN_NONE:
707 struct nand_flash_controller imx31_nand_flash_controller = {
709 .usage = "nand device imx31 target noecc|hwecc",
710 .nand_device_command = &imx31_nand_device_command,
712 .reset = &imx31_reset,
713 .command = &imx31_command,
714 .address = &imx31_address,
715 .write_data = &imx31_write_data,
716 .read_data = &imx31_read_data,
717 .write_page = &imx31_write_page,
718 .read_page = &imx31_read_page,
719 .nand_ready = &imx31_nand_ready,