1 /***************************************************************************
2 * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico at marvell.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * NAND controller interface for Marvell Orion/Kirkwood SoCs.
31 #include <target/arm.h>
34 struct orion_nand_controller
36 struct target *target;
38 struct arm_nand_data io;
45 #define CHECK_HALTED \
47 if (target->state != TARGET_HALTED) { \
48 LOG_ERROR("NAND flash access requires halted target"); \
49 return ERROR_NAND_OPERATION_FAILED; \
53 static int orion_nand_command(struct nand_device *nand, uint8_t command)
55 struct orion_nand_controller *hw = nand->controller_priv;
56 struct target *target = hw->target;
59 target_write_u8(target, hw->cmd, command);
63 static int orion_nand_address(struct nand_device *nand, uint8_t address)
65 struct orion_nand_controller *hw = nand->controller_priv;
66 struct target *target = hw->target;
69 target_write_u8(target, hw->addr, address);
73 static int orion_nand_read(struct nand_device *nand, void *data)
75 struct orion_nand_controller *hw = nand->controller_priv;
76 struct target *target = hw->target;
79 target_read_u8(target, hw->data, data);
83 static int orion_nand_write(struct nand_device *nand, uint16_t data)
85 struct orion_nand_controller *hw = nand->controller_priv;
86 struct target *target = hw->target;
89 target_write_u8(target, hw->data, data);
93 static int orion_nand_slow_block_write(struct nand_device *nand, uint8_t *data, int size)
96 orion_nand_write(nand, *data++);
100 static int orion_nand_fast_block_write(struct nand_device *nand, uint8_t *data, int size)
102 struct orion_nand_controller *hw = nand->controller_priv;
105 hw->io.chunk_size = nand->page_size;
107 retval = arm_nandwrite(&hw->io, data, size);
108 if (retval == ERROR_NAND_NO_BUFFER)
109 retval = orion_nand_slow_block_write(nand, data, size);
114 static int orion_nand_reset(struct nand_device *nand)
116 return orion_nand_command(nand, NAND_CMD_RESET);
119 static int orion_nand_controller_ready(struct nand_device *nand, int timeout)
124 NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
126 struct orion_nand_controller *hw;
131 LOG_ERROR("arguments must be: <target_id> <NAND_address>\n");
132 return ERROR_NAND_DEVICE_INVALID;
135 hw = calloc(1, sizeof(*hw));
137 LOG_ERROR("no memory for nand controller\n");
138 return ERROR_NAND_DEVICE_INVALID;
141 nand->controller_priv = hw;
142 hw->target = get_target(CMD_ARGV[1]);
144 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
146 return ERROR_NAND_DEVICE_INVALID;
149 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], base);
154 hw->cmd = base + (1 << cle);
155 hw->addr = base + (1 << ale);
157 hw->io.target = hw->target;
158 hw->io.data = hw->data;
159 hw->io.op = ARM_NAND_NONE;
164 static int orion_nand_init(struct nand_device *nand)
169 struct nand_flash_controller orion_nand_controller =
172 .command = orion_nand_command,
173 .address = orion_nand_address,
174 .read_data = orion_nand_read,
175 .write_data = orion_nand_write,
176 .write_block_data = orion_nand_fast_block_write,
177 .reset = orion_nand_reset,
178 .controller_ready = orion_nand_controller_ready,
179 .nand_device_command = orion_nand_device_command,
180 .init = orion_nand_init,