git.sur5r.net Git - openocd/blob - src/flash/nand/orion.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Marvell Semiconductors, Inc.                    *
   3  *   Written by Nicolas Pitre <nico at marvell.com>                        *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 /*
  22  * NAND controller interface for Marvell Orion/Kirkwood SoCs.
  23  */
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include "arm_io.h"
  31 #include <target/arm.h>
  32
  33 struct orion_nand_controller {
  34         struct arm_nand_data    io;
  35
  36         uint32_t                cmd;
  37         uint32_t                addr;
  38         uint32_t                data;
  39 };
  40
  41 #define CHECK_HALTED \
  42         do { \
  43                 if (target->state != TARGET_HALTED) { \
  44                         LOG_ERROR("NAND flash access requires halted target"); \
  45                         return ERROR_NAND_OPERATION_FAILED; \
  46                 } \
  47         } while (0)
  48
  49 static int orion_nand_command(struct nand_device *nand, uint8_t command)
  50 {
  51         struct orion_nand_controller *hw = nand->controller_priv;
  52         struct target *target = nand->target;
  53
  54         CHECK_HALTED;
  55         target_write_u8(target, hw->cmd, command);
  56         return ERROR_OK;
  57 }
  58
  59 static int orion_nand_address(struct nand_device *nand, uint8_t address)
  60 {
  61         struct orion_nand_controller *hw = nand->controller_priv;
  62         struct target *target = nand->target;
  63
  64         CHECK_HALTED;
  65         target_write_u8(target, hw->addr, address);
  66         return ERROR_OK;
  67 }
  68
  69 static int orion_nand_read(struct nand_device *nand, void *data)
  70 {
  71         struct orion_nand_controller *hw = nand->controller_priv;
  72         struct target *target = nand->target;
  73
  74         CHECK_HALTED;
  75         target_read_u8(target, hw->data, data);
  76         return ERROR_OK;
  77 }
  78
  79 static int orion_nand_write(struct nand_device *nand, uint16_t data)
  80 {
  81         struct orion_nand_controller *hw = nand->controller_priv;
  82         struct target *target = nand->target;
  83
  84         CHECK_HALTED;
  85         target_write_u8(target, hw->data, data);
  86         return ERROR_OK;
  87 }
  88
  89 static int orion_nand_slow_block_write(struct nand_device *nand, uint8_t *data, int size)
  90 {
  91         while (size--)
  92                 orion_nand_write(nand, *data++);
  93         return ERROR_OK;
  94 }
  95
  96 static int orion_nand_fast_block_write(struct nand_device *nand, uint8_t *data, int size)
  97 {
  98         struct orion_nand_controller *hw = nand->controller_priv;
  99         int retval;
 100
 101         hw->io.chunk_size = nand->page_size;
 102
 103         retval = arm_nandwrite(&hw->io, data, size);
 104         if (retval == ERROR_NAND_NO_BUFFER)
 105                 retval = orion_nand_slow_block_write(nand, data, size);
 106
 107         return retval;
 108 }
 109
 110 static int orion_nand_reset(struct nand_device *nand)
 111 {
 112         return orion_nand_command(nand, NAND_CMD_RESET);
 113 }
 114
 115 NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
 116 {
 117         struct orion_nand_controller *hw;
 118         uint32_t base;
 119         uint8_t ale, cle;
 120
 121         if (CMD_ARGC != 3)
 122                 return ERROR_COMMAND_SYNTAX_ERROR;
 123
 124         hw = calloc(1, sizeof(*hw));
 125         if (!hw) {
 126                 LOG_ERROR("no memory for nand controller");
 127                 return ERROR_NAND_DEVICE_INVALID;
 128         }
 129
 130         nand->controller_priv = hw;
 131
 132         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], base);
 133         cle = 0;
 134         ale = 1;
 135
 136         hw->data = base;
 137         hw->cmd = base + (1 << cle);
 138         hw->addr = base + (1 << ale);
 139
 140         hw->io.target = nand->target;
 141         hw->io.data = hw->data;
 142         hw->io.op = ARM_NAND_NONE;
 143
 144         return ERROR_OK;
 145 }
 146
 147 static int orion_nand_init(struct nand_device *nand)
 148 {
 149         return ERROR_OK;
 150 }
 151
 152 struct nand_flash_controller orion_nand_controller = {
 153         .name = "orion",
 154         .usage = "<target_id> <NAND_address>",
 155         .command = orion_nand_command,
 156         .address = orion_nand_address,
 157         .read_data = orion_nand_read,
 158         .write_data = orion_nand_write,
 159         .write_block_data = orion_nand_fast_block_write,
 160         .reset = orion_nand_reset,
 161         .nand_device_command = orion_nand_device_command,
 162         .init = orion_nand_init,
 163 };