1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
34 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
45 //static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
47 static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
49 /* NAND flash controller
51 extern nand_flash_controller_t davinci_nand_controller;
52 extern nand_flash_controller_t lpc3180_nand_controller;
53 extern nand_flash_controller_t orion_nand_controller;
54 extern nand_flash_controller_t s3c2410_nand_controller;
55 extern nand_flash_controller_t s3c2412_nand_controller;
56 extern nand_flash_controller_t s3c2440_nand_controller;
57 extern nand_flash_controller_t s3c2443_nand_controller;
59 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
61 static nand_flash_controller_t *nand_flash_controllers[] =
63 &davinci_nand_controller,
64 &lpc3180_nand_controller,
65 &orion_nand_controller,
66 &s3c2410_nand_controller,
67 &s3c2412_nand_controller,
68 &s3c2440_nand_controller,
69 &s3c2443_nand_controller,
70 /* &boundary_scan_nand_controller, */
74 /* configured NAND devices and NAND Flash command handler */
75 static nand_device_t *nand_devices = NULL;
76 static command_t *nand_cmd;
80 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
83 * Pagesize; 0, 256, 512
84 * 0 get this information from the extended chip ID
85 * 256 256 Byte page size
86 * 512 512 Byte page size
88 static nand_info_t nand_flash_ids[] =
90 /* start "museum" IDs */
91 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
92 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
93 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
95 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
96 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
99 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
100 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
104 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
106 /* end "museum" IDs */
108 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
110 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
111 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
113 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
115 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
120 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
121 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
123 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
126 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
129 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
131 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
133 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
135 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
136 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
138 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
140 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
141 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
143 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
145 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
146 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
148 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
150 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
151 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
153 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
155 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
156 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
158 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
160 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
161 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
163 {NULL, 0, 0, 0, 0, 0 }
166 /* Manufacturer ID list
168 static nand_manufacturer_t nand_manuf_ids[] =
171 {NAND_MFR_TOSHIBA, "Toshiba"},
172 {NAND_MFR_SAMSUNG, "Samsung"},
173 {NAND_MFR_FUJITSU, "Fujitsu"},
174 {NAND_MFR_NATIONAL, "National"},
175 {NAND_MFR_RENESAS, "Renesas"},
176 {NAND_MFR_STMICRO, "ST Micro"},
177 {NAND_MFR_HYNIX, "Hynix"},
178 {NAND_MFR_MICRON, "Micron"},
183 * Define default oob placement schemes for large and small page devices
187 static nand_ecclayout_t nand_oob_8 = {
198 static nand_ecclayout_t nand_oob_16 = {
200 .eccpos = {0, 1, 2, 3, 6, 7},
206 static nand_ecclayout_t nand_oob_64 = {
209 40, 41, 42, 43, 44, 45, 46, 47,
210 48, 49, 50, 51, 52, 53, 54, 55,
211 56, 57, 58, 59, 60, 61, 62, 63},
217 /* nand device <nand_controller> [controller options]
219 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
226 LOG_WARNING("incomplete flash device nand configuration");
227 return ERROR_FLASH_BANK_INVALID;
230 for (i = 0; nand_flash_controllers[i]; i++)
232 nand_device_t *p, *c;
234 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
236 /* register flash specific commands */
237 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
239 LOG_ERROR("couldn't register '%s' commands", args[0]);
243 c = malloc(sizeof(nand_device_t));
245 c->controller = nand_flash_controllers[i];
246 c->controller_priv = NULL;
247 c->manufacturer = NULL;
250 c->address_cycles = 0;
255 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
257 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
262 /* put NAND device in linked list */
265 /* find last flash device */
266 for (p = nand_devices; p && p->next; p = p->next);
279 /* no valid NAND controller was found (i.e. the configuration option,
280 * didn't match one of the compiled-in controllers)
282 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
283 LOG_ERROR("compiled-in NAND flash controllers:");
284 for (i = 0; nand_flash_controllers[i]; i++)
286 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
292 int nand_register_commands(struct command_context_s *cmd_ctx)
294 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
296 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
301 int nand_init(struct command_context_s *cmd_ctx)
305 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
306 "list configured NAND flash devices");
307 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
308 "print info about NAND flash device <num>");
309 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
310 "identify NAND flash device <num>");
311 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
312 "check NAND flash device <num> for bad blocks [<first> <last>]");
313 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
314 "erase blocks on NAND flash device <num> <first> <last>");
315 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
316 "dump from NAND flash device <num> <filename> "
317 "<offset> <size> [oob_raw|oob_only]");
318 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
319 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc|oob_softecc_kw]");
320 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
321 "raw access to NAND flash device <num> ['enable'|'disable']");
327 nand_device_t *get_nand_device_by_num(int num)
332 for (p = nand_devices; p; p = p->next)
343 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
349 if ((first < 0) || (first >= device->num_blocks))
352 if ((last >= device->num_blocks) || (last == -1))
353 last = device->num_blocks - 1;
355 for (i = first; i < last; i++)
357 nand_read_page(device, page, NULL, 0, oob, 6);
359 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
360 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
361 ((device->page_size == 2048) && (oob[0] != 0xff))))
363 LOG_WARNING("invalid block: %i", i);
364 device->blocks[i].is_bad = 1;
368 device->blocks[i].is_bad = 0;
371 page += (device->erase_size / device->page_size);
377 int nand_read_status(struct nand_device_s *device, u8 *status)
380 return ERROR_NAND_DEVICE_NOT_PROBED;
382 /* Send read status command */
383 device->controller->command(device, NAND_CMD_STATUS);
388 if (device->device->options & NAND_BUSWIDTH_16)
391 device->controller->read_data(device, &data);
392 *status = data & 0xff;
396 device->controller->read_data(device, status);
402 static int nand_poll_ready(struct nand_device_s *device, int timeout)
406 device->controller->command(device, NAND_CMD_STATUS);
408 if (device->device->options & NAND_BUSWIDTH_16) {
410 device->controller->read_data(device, &data);
411 status = data & 0xff;
413 device->controller->read_data(device, &status);
415 if (status & NAND_STATUS_READY)
420 return (status & NAND_STATUS_READY) != 0;
423 int nand_probe(struct nand_device_s *device)
425 u8 manufacturer_id, device_id;
430 /* clear device data */
431 device->device = NULL;
432 device->manufacturer = NULL;
434 /* clear device parameters */
435 device->bus_width = 0;
436 device->address_cycles = 0;
437 device->page_size = 0;
438 device->erase_size = 0;
440 /* initialize controller (device parameters are zero, use controller default) */
441 if ((retval = device->controller->init(device) != ERROR_OK))
445 case ERROR_NAND_OPERATION_FAILED:
446 LOG_DEBUG("controller initialization failed");
447 return ERROR_NAND_OPERATION_FAILED;
448 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
449 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
450 return ERROR_NAND_OPERATION_FAILED;
452 LOG_ERROR("BUG: unknown controller initialization failure");
453 return ERROR_NAND_OPERATION_FAILED;
457 device->controller->command(device, NAND_CMD_RESET);
458 device->controller->reset(device);
460 device->controller->command(device, NAND_CMD_READID);
461 device->controller->address(device, 0x0);
463 if (device->bus_width == 8)
465 device->controller->read_data(device, &manufacturer_id);
466 device->controller->read_data(device, &device_id);
471 device->controller->read_data(device, &data_buf);
472 manufacturer_id = data_buf & 0xff;
473 device->controller->read_data(device, &data_buf);
474 device_id = data_buf & 0xff;
477 for (i = 0; nand_flash_ids[i].name; i++)
479 if (nand_flash_ids[i].id == device_id)
481 device->device = &nand_flash_ids[i];
486 for (i = 0; nand_manuf_ids[i].name; i++)
488 if (nand_manuf_ids[i].id == manufacturer_id)
490 device->manufacturer = &nand_manuf_ids[i];
495 if (!device->manufacturer)
497 device->manufacturer = &nand_manuf_ids[0];
498 device->manufacturer->id = manufacturer_id;
503 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
504 manufacturer_id, device_id);
505 return ERROR_NAND_OPERATION_FAILED;
508 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
510 /* initialize device parameters */
513 if (device->device->options & NAND_BUSWIDTH_16)
514 device->bus_width = 16;
516 device->bus_width = 8;
518 /* Do we need extended device probe information? */
519 if (device->device->page_size == 0 ||
520 device->device->erase_size == 0)
522 if (device->bus_width == 8)
524 device->controller->read_data(device, id_buff+3);
525 device->controller->read_data(device, id_buff+4);
526 device->controller->read_data(device, id_buff+5);
532 device->controller->read_data(device, &data_buf);
533 id_buff[3] = data_buf;
535 device->controller->read_data(device, &data_buf);
536 id_buff[4] = data_buf;
538 device->controller->read_data(device, &data_buf);
539 id_buff[5] = data_buf >> 8;
544 if (device->device->page_size == 0)
546 device->page_size = 1 << (10 + (id_buff[4] & 3));
548 else if (device->device->page_size == 256)
550 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
551 return ERROR_NAND_OPERATION_FAILED;
555 device->page_size = device->device->page_size;
558 /* number of address cycles */
559 if (device->page_size <= 512)
561 /* small page devices */
562 if (device->device->chip_size <= 32)
563 device->address_cycles = 3;
564 else if (device->device->chip_size <= 8*1024)
565 device->address_cycles = 4;
568 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
569 device->address_cycles = 5;
574 /* large page devices */
575 if (device->device->chip_size <= 128)
576 device->address_cycles = 4;
577 else if (device->device->chip_size <= 32*1024)
578 device->address_cycles = 5;
581 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
582 device->address_cycles = 6;
587 if (device->device->erase_size == 0)
589 switch ((id_buff[4] >> 4) & 3) {
591 device->erase_size = 64 << 10;
594 device->erase_size = 128 << 10;
597 device->erase_size = 256 << 10;
600 device->erase_size =512 << 10;
606 device->erase_size = device->device->erase_size;
609 /* initialize controller, but leave parameters at the controllers default */
610 if ((retval = device->controller->init(device) != ERROR_OK))
614 case ERROR_NAND_OPERATION_FAILED:
615 LOG_DEBUG("controller initialization failed");
616 return ERROR_NAND_OPERATION_FAILED;
617 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
618 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
619 device->bus_width, device->address_cycles, device->page_size);
620 return ERROR_NAND_OPERATION_FAILED;
622 LOG_ERROR("BUG: unknown controller initialization failure");
623 return ERROR_NAND_OPERATION_FAILED;
627 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
628 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
630 for (i = 0; i < device->num_blocks; i++)
632 device->blocks[i].size = device->erase_size;
633 device->blocks[i].offset = i * device->erase_size;
634 device->blocks[i].is_erased = -1;
635 device->blocks[i].is_bad = -1;
641 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
649 return ERROR_NAND_DEVICE_NOT_PROBED;
651 if ((first_block < 0) || (last_block > device->num_blocks))
652 return ERROR_INVALID_ARGUMENTS;
654 /* make sure we know if a block is bad before erasing it */
655 for (i = first_block; i <= last_block; i++)
657 if (device->blocks[i].is_bad == -1)
659 nand_build_bbt(device, i, last_block);
664 for (i = first_block; i <= last_block; i++)
666 /* Send erase setup command */
667 device->controller->command(device, NAND_CMD_ERASE1);
669 page = i * (device->erase_size / device->page_size);
671 /* Send page address */
672 if (device->page_size <= 512)
675 device->controller->address(device, page & 0xff);
676 device->controller->address(device, (page >> 8) & 0xff);
678 /* 3rd cycle only on devices with more than 32 MiB */
679 if (device->address_cycles >= 4)
680 device->controller->address(device, (page >> 16) & 0xff);
682 /* 4th cycle only on devices with more than 8 GiB */
683 if (device->address_cycles >= 5)
684 device->controller->address(device, (page >> 24) & 0xff);
689 device->controller->address(device, page & 0xff);
690 device->controller->address(device, (page >> 8) & 0xff);
692 /* 3rd cycle only on devices with more than 128 MiB */
693 if (device->address_cycles >= 5)
694 device->controller->address(device, (page >> 16) & 0xff);
697 /* Send erase confirm command */
698 device->controller->command(device, NAND_CMD_ERASE2);
700 retval = device->controller->nand_ready ?
701 device->controller->nand_ready(device, 1000) :
702 nand_poll_ready(device, 1000);
704 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
705 return ERROR_NAND_OPERATION_TIMEOUT;
708 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
710 LOG_ERROR("couldn't read status");
711 return ERROR_NAND_OPERATION_FAILED;
716 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
717 return ERROR_NAND_OPERATION_FAILED;
720 device->blocks[i].is_erased = 1;
727 static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
732 return ERROR_NAND_DEVICE_NOT_PROBED;
734 if (address % device->page_size)
736 LOG_ERROR("reads need to be page aligned");
737 return ERROR_NAND_OPERATION_FAILED;
740 page = malloc(device->page_size);
742 while (data_size > 0 )
744 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
748 page_address = address / device->page_size;
750 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
752 memcpy(data, page, thisrun_size);
754 address += thisrun_size;
755 data += thisrun_size;
756 data_size -= thisrun_size;
764 static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
769 return ERROR_NAND_DEVICE_NOT_PROBED;
771 if (address % device->page_size)
773 LOG_ERROR("writes need to be page aligned");
774 return ERROR_NAND_OPERATION_FAILED;
777 page = malloc(device->page_size);
779 while (data_size > 0 )
781 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
784 memset(page, 0xff, device->page_size);
785 memcpy(page, data, thisrun_size);
787 page_address = address / device->page_size;
789 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
791 address += thisrun_size;
792 data += thisrun_size;
793 data_size -= thisrun_size;
802 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
807 return ERROR_NAND_DEVICE_NOT_PROBED;
809 block = page / (device->erase_size / device->page_size);
810 if (device->blocks[block].is_erased == 1)
811 device->blocks[block].is_erased = 0;
813 if (device->use_raw || device->controller->write_page == NULL)
814 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
816 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
819 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
822 return ERROR_NAND_DEVICE_NOT_PROBED;
824 if (device->use_raw || device->controller->read_page == NULL)
825 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
827 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
830 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
835 return ERROR_NAND_DEVICE_NOT_PROBED;
837 if (device->page_size <= 512)
839 /* small page device */
841 device->controller->command(device, NAND_CMD_READ0);
843 device->controller->command(device, NAND_CMD_READOOB);
845 /* column (always 0, we start at the beginning of a page/OOB area) */
846 device->controller->address(device, 0x0);
849 device->controller->address(device, page & 0xff);
850 device->controller->address(device, (page >> 8) & 0xff);
852 /* 4th cycle only on devices with more than 32 MiB */
853 if (device->address_cycles >= 4)
854 device->controller->address(device, (page >> 16) & 0xff);
856 /* 5th cycle only on devices with more than 8 GiB */
857 if (device->address_cycles >= 5)
858 device->controller->address(device, (page >> 24) & 0xff);
862 /* large page device */
863 device->controller->command(device, NAND_CMD_READ0);
865 /* column (0 when we start at the beginning of a page,
866 * or 2048 for the beginning of OOB area)
868 device->controller->address(device, 0x0);
870 device->controller->address(device, 0x0);
872 device->controller->address(device, 0x8);
875 device->controller->address(device, page & 0xff);
876 device->controller->address(device, (page >> 8) & 0xff);
878 /* 5th cycle only on devices with more than 128 MiB */
879 if (device->address_cycles >= 5)
880 device->controller->address(device, (page >> 16) & 0xff);
882 /* large page devices need a start command */
883 device->controller->command(device, NAND_CMD_READSTART);
886 if (device->controller->nand_ready) {
887 if (!device->controller->nand_ready(device, 100))
888 return ERROR_NAND_OPERATION_TIMEOUT;
895 if (device->controller->read_block_data != NULL)
896 (device->controller->read_block_data)(device, data, data_size);
899 for (i = 0; i < data_size;)
901 if (device->device->options & NAND_BUSWIDTH_16)
903 device->controller->read_data(device, data);
909 device->controller->read_data(device, data);
919 if (device->controller->read_block_data != NULL)
920 (device->controller->read_block_data)(device, oob, oob_size);
923 for (i = 0; i < oob_size;)
925 if (device->device->options & NAND_BUSWIDTH_16)
927 device->controller->read_data(device, oob);
933 device->controller->read_data(device, oob);
944 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
951 return ERROR_NAND_DEVICE_NOT_PROBED;
953 device->controller->command(device, NAND_CMD_SEQIN);
955 if (device->page_size <= 512)
957 /* column (always 0, we start at the beginning of a page/OOB area) */
958 device->controller->address(device, 0x0);
961 device->controller->address(device, page & 0xff);
962 device->controller->address(device, (page >> 8) & 0xff);
964 /* 4th cycle only on devices with more than 32 MiB */
965 if (device->address_cycles >= 4)
966 device->controller->address(device, (page >> 16) & 0xff);
968 /* 5th cycle only on devices with more than 8 GiB */
969 if (device->address_cycles >= 5)
970 device->controller->address(device, (page >> 24) & 0xff);
974 /* column (0 when we start at the beginning of a page,
975 * or 2048 for the beginning of OOB area)
977 device->controller->address(device, 0x0);
979 device->controller->address(device, 0x0);
981 device->controller->address(device, 0x8);
984 device->controller->address(device, page & 0xff);
985 device->controller->address(device, (page >> 8) & 0xff);
987 /* 5th cycle only on devices with more than 128 MiB */
988 if (device->address_cycles >= 5)
989 device->controller->address(device, (page >> 16) & 0xff);
994 if (device->controller->write_block_data != NULL)
995 (device->controller->write_block_data)(device, data, data_size);
998 for (i = 0; i < data_size;)
1000 if (device->device->options & NAND_BUSWIDTH_16)
1002 u16 data_buf = le_to_h_u16(data);
1003 device->controller->write_data(device, data_buf);
1009 device->controller->write_data(device, *data);
1019 if (device->controller->write_block_data != NULL)
1020 (device->controller->write_block_data)(device, oob, oob_size);
1023 for (i = 0; i < oob_size;)
1025 if (device->device->options & NAND_BUSWIDTH_16)
1027 u16 oob_buf = le_to_h_u16(data);
1028 device->controller->write_data(device, oob_buf);
1034 device->controller->write_data(device, *oob);
1042 device->controller->command(device, NAND_CMD_PAGEPROG);
1044 retval = device->controller->nand_ready ?
1045 device->controller->nand_ready(device, 100) :
1046 nand_poll_ready(device, 100);
1048 return ERROR_NAND_OPERATION_TIMEOUT;
1050 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1052 LOG_ERROR("couldn't read status");
1053 return ERROR_NAND_OPERATION_FAILED;
1056 if (status & NAND_STATUS_FAIL)
1058 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1059 return ERROR_NAND_OPERATION_FAILED;
1065 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1072 command_print(cmd_ctx, "no NAND flash devices configured");
1076 for (p = nand_devices, i = 0; p; p = p->next, i++)
1079 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1080 i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1082 command_print(cmd_ctx, "#%i: not probed", i);
1088 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1096 if ((argc < 1) || (argc > 3))
1098 return ERROR_COMMAND_SYNTAX_ERROR;
1104 first = last = strtoul(args[1], NULL, 0);
1108 first = strtoul(args[1], NULL, 0);
1109 last = strtoul(args[2], NULL, 0);
1112 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1117 if (first >= p->num_blocks)
1118 first = p->num_blocks - 1;
1120 if (last >= p->num_blocks)
1121 last = p->num_blocks - 1;
1123 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1124 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1126 for (j = first; j <= last; j++)
1128 char *erase_state, *bad_state;
1130 if (p->blocks[j].is_erased == 0)
1131 erase_state = "not erased";
1132 else if (p->blocks[j].is_erased == 1)
1133 erase_state = "erased";
1135 erase_state = "erase state unknown";
1137 if (p->blocks[j].is_bad == 0)
1139 else if (p->blocks[j].is_bad == 1)
1140 bad_state = " (marked bad)";
1142 bad_state = " (block condition unknown)";
1144 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1145 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1146 erase_state, bad_state);
1151 command_print(cmd_ctx, "#%s: not probed", args[0]);
1158 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1165 return ERROR_COMMAND_SYNTAX_ERROR;
1168 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1171 if ((retval = nand_probe(p)) == ERROR_OK)
1173 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1175 else if (retval == ERROR_NAND_OPERATION_FAILED)
1177 command_print(cmd_ctx, "probing failed for NAND flash device");
1181 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1186 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1192 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1199 return ERROR_COMMAND_SYNTAX_ERROR;
1203 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1206 int first = strtoul(args[1], NULL, 0);
1207 int last = strtoul(args[2], NULL, 0);
1209 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1211 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1213 else if (retval == ERROR_NAND_OPERATION_FAILED)
1215 command_print(cmd_ctx, "erase failed");
1219 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1224 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1230 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1237 if ((argc < 1) || (argc > 3) || (argc == 2))
1239 return ERROR_COMMAND_SYNTAX_ERROR;
1245 first = strtoul(args[1], NULL, 0);
1246 last = strtoul(args[2], NULL, 0);
1249 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1252 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1254 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks");
1256 else if (retval == ERROR_NAND_OPERATION_FAILED)
1258 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1262 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1267 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1273 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1278 enum oob_formats oob_format = NAND_OOB_NONE;
1282 duration_t duration;
1283 char *duration_text;
1289 return ERROR_COMMAND_SYNTAX_ERROR;
1293 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1300 const int *eccpos = NULL;
1302 offset = strtoul(args[2], NULL, 0);
1307 for (i = 3; i < argc; i++)
1309 if (!strcmp(args[i], "oob_raw"))
1310 oob_format |= NAND_OOB_RAW;
1311 else if (!strcmp(args[i], "oob_only"))
1312 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1313 else if (!strcmp(args[i], "oob_softecc"))
1314 oob_format |= NAND_OOB_SW_ECC;
1315 else if (!strcmp(args[i], "oob_softecc_kw"))
1316 oob_format |= NAND_OOB_SW_ECC_KW;
1319 command_print(cmd_ctx, "unknown option: %s", args[i]);
1320 return ERROR_COMMAND_SYNTAX_ERROR;
1325 duration_start_measure(&duration);
1327 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1332 buf_cnt = binary_size = fileio.size;
1334 if (!(oob_format & NAND_OOB_ONLY))
1336 page_size = p->page_size;
1337 page = malloc(p->page_size);
1340 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1342 if (p->page_size == 512) {
1344 eccpos = nand_oob_16.eccpos;
1345 } else if (p->page_size == 2048) {
1347 eccpos = nand_oob_64.eccpos;
1349 oob = malloc(oob_size);
1352 if (offset % p->page_size)
1354 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1355 fileio_close(&fileio);
1367 fileio_read(&fileio, page_size, page, &size_read);
1368 buf_cnt -= size_read;
1369 if (size_read < page_size)
1371 memset(page + size_read, 0xff, page_size - size_read);
1375 if (oob_format & NAND_OOB_SW_ECC)
1379 memset(oob, 0xff, oob_size);
1380 for (i = 0, j = 0; i < page_size; i += 256) {
1381 nand_calculate_ecc(p, page+i, ecc);
1382 oob[eccpos[j++]] = ecc[0];
1383 oob[eccpos[j++]] = ecc[1];
1384 oob[eccpos[j++]] = ecc[2];
1386 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1389 * In this case eccpos is not used as
1390 * the ECC data is always stored contigously
1391 * at the end of the OOB area. It consists
1392 * of 10 bytes per 512-byte data block.
1395 u8 *ecc = oob + oob_size - page_size/512 * 10;
1396 memset(oob, 0xff, oob_size);
1397 for (i = 0; i < page_size; i += 512) {
1398 nand_calculate_ecc_kw(p, page+i, ecc);
1402 else if (NULL != oob)
1404 fileio_read(&fileio, oob_size, oob, &size_read);
1405 buf_cnt -= size_read;
1406 if (size_read < oob_size)
1408 memset(oob + size_read, 0xff, oob_size - size_read);
1412 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1414 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1415 args[1], args[0], offset);
1417 fileio_close(&fileio);
1423 offset += page_size;
1426 fileio_close(&fileio);
1431 duration_stop_measure(&duration, &duration_text);
1432 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1433 args[1], args[0], offset, duration_text);
1434 free(duration_text);
1435 duration_text = NULL;
1439 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1445 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1451 return ERROR_COMMAND_SYNTAX_ERROR;
1454 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1460 duration_t duration;
1461 char *duration_text;
1468 u32 address = strtoul(args[2], NULL, 0);
1469 u32 size = strtoul(args[3], NULL, 0);
1471 enum oob_formats oob_format = NAND_OOB_NONE;
1476 for (i = 4; i < argc; i++)
1478 if (!strcmp(args[i], "oob_raw"))
1479 oob_format |= NAND_OOB_RAW;
1480 else if (!strcmp(args[i], "oob_only"))
1481 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1483 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1487 if ((address % p->page_size) || (size % p->page_size))
1489 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1493 if (!(oob_format & NAND_OOB_ONLY))
1495 page_size = p->page_size;
1496 page = malloc(p->page_size);
1499 if (oob_format & NAND_OOB_RAW)
1501 if (p->page_size == 512)
1503 else if (p->page_size == 2048)
1505 oob = malloc(oob_size);
1508 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1513 duration_start_measure(&duration);
1518 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1520 command_print(cmd_ctx, "reading NAND flash page failed");
1523 fileio_close(&fileio);
1529 fileio_write(&fileio, page_size, page, &size_written);
1530 bytes_done += page_size;
1535 fileio_write(&fileio, oob_size, oob, &size_written);
1536 bytes_done += oob_size;
1539 size -= p->page_size;
1540 address += p->page_size;
1547 fileio_close(&fileio);
1549 duration_stop_measure(&duration, &duration_text);
1550 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1551 free(duration_text);
1552 duration_text = NULL;
1556 command_print(cmd_ctx, "#%s: not probed", args[0]);
1561 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1567 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1571 if ((argc < 1) || (argc > 2))
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1576 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1583 if (strcmp("enable", args[1]) == 0)
1587 else if (strcmp("disable", args[1]) == 0)
1593 return ERROR_COMMAND_SYNTAX_ERROR;
1597 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1601 command_print(cmd_ctx, "#%s: not probed", args[0]);
1606 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);