1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
38 #include "time_support.h"
42 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
54 //static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
56 static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
58 /* NAND flash controller
60 extern nand_flash_controller_t lpc3180_nand_controller;
61 extern nand_flash_controller_t orion_nand_controller;
62 extern nand_flash_controller_t s3c2410_nand_controller;
63 extern nand_flash_controller_t s3c2412_nand_controller;
64 extern nand_flash_controller_t s3c2440_nand_controller;
65 extern nand_flash_controller_t s3c2443_nand_controller;
67 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
69 static nand_flash_controller_t *nand_flash_controllers[] =
71 &lpc3180_nand_controller,
72 &orion_nand_controller,
73 &s3c2410_nand_controller,
74 &s3c2412_nand_controller,
75 &s3c2440_nand_controller,
76 &s3c2443_nand_controller,
77 /* &boundary_scan_nand_controller, */
81 /* configured NAND devices and NAND Flash command handler */
82 static nand_device_t *nand_devices = NULL;
83 static command_t *nand_cmd;
87 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
90 * Pagesize; 0, 256, 512
91 * 0 get this information from the extended chip ID
92 * 256 256 Byte page size
93 * 512 512 Byte page size
95 static nand_info_t nand_flash_ids[] =
97 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
98 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
99 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
100 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
101 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
102 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
103 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
104 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
105 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
106 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
108 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
109 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
110 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
111 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
113 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
114 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
115 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
119 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
120 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
121 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
123 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
124 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
125 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
129 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
130 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
131 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
132 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
133 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
134 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
136 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
138 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
139 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
140 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
141 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
143 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
144 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
145 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
146 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
148 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
149 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
150 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
151 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
153 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
154 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
155 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
156 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
158 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
159 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
160 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
161 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
163 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
164 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
165 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
166 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
168 {NULL, 0, 0, 0, 0, 0 }
171 /* Manufacturer ID list
173 static nand_manufacturer_t nand_manuf_ids[] =
176 {NAND_MFR_TOSHIBA, "Toshiba"},
177 {NAND_MFR_SAMSUNG, "Samsung"},
178 {NAND_MFR_FUJITSU, "Fujitsu"},
179 {NAND_MFR_NATIONAL, "National"},
180 {NAND_MFR_RENESAS, "Renesas"},
181 {NAND_MFR_STMICRO, "ST Micro"},
182 {NAND_MFR_HYNIX, "Hynix"},
187 * Define default oob placement schemes for large and small page devices
191 static nand_ecclayout_t nand_oob_8 = {
202 static nand_ecclayout_t nand_oob_16 = {
204 .eccpos = {0, 1, 2, 3, 6, 7},
210 static nand_ecclayout_t nand_oob_64 = {
213 40, 41, 42, 43, 44, 45, 46, 47,
214 48, 49, 50, 51, 52, 53, 54, 55,
215 56, 57, 58, 59, 60, 61, 62, 63},
221 /* nand device <nand_controller> [controller options]
223 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
230 LOG_WARNING("incomplete flash device nand configuration");
231 return ERROR_FLASH_BANK_INVALID;
234 for (i = 0; nand_flash_controllers[i]; i++)
236 nand_device_t *p, *c;
238 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
240 /* register flash specific commands */
241 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
243 LOG_ERROR("couldn't register '%s' commands", args[0]);
247 c = malloc(sizeof(nand_device_t));
249 c->controller = nand_flash_controllers[i];
250 c->controller_priv = NULL;
251 c->manufacturer = NULL;
254 c->address_cycles = 0;
259 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
261 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
266 /* put NAND device in linked list */
269 /* find last flash device */
270 for (p = nand_devices; p && p->next; p = p->next);
283 /* no valid NAND controller was found (i.e. the configuration option,
284 * didn't match one of the compiled-in controllers)
286 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
287 LOG_ERROR("compiled-in NAND flash controllers:");
288 for (i = 0; nand_flash_controllers[i]; i++)
290 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
296 int nand_register_commands(struct command_context_s *cmd_ctx)
298 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
300 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
305 int nand_init(struct command_context_s *cmd_ctx)
309 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
310 "list configured NAND flash devices");
311 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
312 "print info about NAND flash device <num>");
313 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
314 "identify NAND flash device <num>");
315 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
316 "check NAND flash device <num> for bad blocks [<first> <last>]");
317 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
318 "erase blocks on NAND flash device <num> <first> <last>");
319 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
320 "copy from NAND flash device <num> <offset> <length> <ram-address>");
321 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
322 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
323 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
324 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc]");
325 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
326 "raw access to NAND flash device <num> ['enable'|'disable']");
332 nand_device_t *get_nand_device_by_num(int num)
337 for (p = nand_devices; p; p = p->next)
348 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
354 if ((first < 0) || (first >= device->num_blocks))
357 if ((last >= device->num_blocks) || (last == -1))
358 last = device->num_blocks - 1;
360 for (i = first; i < last; i++)
362 nand_read_page(device, page, NULL, 0, oob, 6);
364 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
365 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
366 ((device->page_size == 2048) && (oob[0] != 0xff))))
368 LOG_WARNING("invalid block: %i", i);
369 device->blocks[i].is_bad = 1;
373 device->blocks[i].is_bad = 0;
376 page += (device->erase_size / device->page_size);
382 int nand_read_status(struct nand_device_s *device, u8 *status)
385 return ERROR_NAND_DEVICE_NOT_PROBED;
387 /* Send read status command */
388 device->controller->command(device, NAND_CMD_STATUS);
393 if (device->device->options & NAND_BUSWIDTH_16)
396 device->controller->read_data(device, &data);
397 *status = data & 0xff;
401 device->controller->read_data(device, status);
407 static int nand_poll_ready(struct nand_device_s *device, int timeout)
411 device->controller->command(device, NAND_CMD_STATUS);
413 if (device->device->options & NAND_BUSWIDTH_16) {
415 device->controller->read_data(device, &data);
416 status = data & 0xff;
418 device->controller->read_data(device, &status);
420 if (status & NAND_STATUS_READY)
425 return (status & NAND_STATUS_READY) != 0;
428 int nand_probe(struct nand_device_s *device)
430 u8 manufacturer_id, device_id;
435 /* clear device data */
436 device->device = NULL;
437 device->manufacturer = NULL;
439 /* clear device parameters */
440 device->bus_width = 0;
441 device->address_cycles = 0;
442 device->page_size = 0;
443 device->erase_size = 0;
445 /* initialize controller (device parameters are zero, use controller default) */
446 if ((retval = device->controller->init(device) != ERROR_OK))
450 case ERROR_NAND_OPERATION_FAILED:
451 LOG_DEBUG("controller initialization failed");
452 return ERROR_NAND_OPERATION_FAILED;
453 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
454 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
455 return ERROR_NAND_OPERATION_FAILED;
457 LOG_ERROR("BUG: unknown controller initialization failure");
458 return ERROR_NAND_OPERATION_FAILED;
462 device->controller->command(device, NAND_CMD_RESET);
463 device->controller->reset(device);
465 device->controller->command(device, NAND_CMD_READID);
466 device->controller->address(device, 0x0);
468 if (device->bus_width == 8)
470 device->controller->read_data(device, &manufacturer_id);
471 device->controller->read_data(device, &device_id);
476 device->controller->read_data(device, &data_buf);
477 manufacturer_id = data_buf & 0xff;
478 device->controller->read_data(device, &data_buf);
479 device_id = data_buf & 0xff;
482 for (i = 0; nand_flash_ids[i].name; i++)
484 if (nand_flash_ids[i].id == device_id)
486 device->device = &nand_flash_ids[i];
491 for (i = 0; nand_manuf_ids[i].name; i++)
493 if (nand_manuf_ids[i].id == manufacturer_id)
495 device->manufacturer = &nand_manuf_ids[i];
500 if (!device->manufacturer)
502 device->manufacturer = &nand_manuf_ids[0];
503 device->manufacturer->id = manufacturer_id;
508 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
509 manufacturer_id, device_id);
510 return ERROR_NAND_OPERATION_FAILED;
513 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
515 /* initialize device parameters */
518 if (device->device->options & NAND_BUSWIDTH_16)
519 device->bus_width = 16;
521 device->bus_width = 8;
523 /* Do we need extended device probe information? */
524 if (device->device->page_size == 0 ||
525 device->device->erase_size == 0)
527 if (device->bus_width == 8)
529 device->controller->read_data(device, id_buff+3);
530 device->controller->read_data(device, id_buff+4);
531 device->controller->read_data(device, id_buff+5);
537 device->controller->read_data(device, &data_buf);
538 id_buff[3] = data_buf;
540 device->controller->read_data(device, &data_buf);
541 id_buff[4] = data_buf;
543 device->controller->read_data(device, &data_buf);
544 id_buff[5] = data_buf >> 8;
549 if (device->device->page_size == 0)
551 device->page_size = 1 << (10 + (id_buff[4] & 3));
553 else if (device->device->page_size == 256)
555 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
556 return ERROR_NAND_OPERATION_FAILED;
560 device->page_size = device->device->page_size;
563 /* number of address cycles */
564 if (device->page_size <= 512)
566 /* small page devices */
567 if (device->device->chip_size <= 32)
568 device->address_cycles = 3;
569 else if (device->device->chip_size <= 8*1024)
570 device->address_cycles = 4;
573 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
574 device->address_cycles = 5;
579 /* large page devices */
580 if (device->device->chip_size <= 128)
581 device->address_cycles = 4;
582 else if (device->device->chip_size <= 32*1024)
583 device->address_cycles = 5;
586 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
587 device->address_cycles = 6;
592 if (device->device->erase_size == 0)
594 switch ((id_buff[4] >> 4) & 3) {
596 device->erase_size = 64 << 10;
599 device->erase_size = 128 << 10;
602 device->erase_size = 256 << 10;
605 device->erase_size =512 << 10;
611 device->erase_size = device->device->erase_size;
614 /* initialize controller, but leave parameters at the controllers default */
615 if ((retval = device->controller->init(device) != ERROR_OK))
619 case ERROR_NAND_OPERATION_FAILED:
620 LOG_DEBUG("controller initialization failed");
621 return ERROR_NAND_OPERATION_FAILED;
622 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
623 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
624 device->bus_width, device->address_cycles, device->page_size);
625 return ERROR_NAND_OPERATION_FAILED;
627 LOG_ERROR("BUG: unknown controller initialization failure");
628 return ERROR_NAND_OPERATION_FAILED;
632 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
633 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
635 for (i = 0; i < device->num_blocks; i++)
637 device->blocks[i].size = device->erase_size;
638 device->blocks[i].offset = i * device->erase_size;
639 device->blocks[i].is_erased = -1;
640 device->blocks[i].is_bad = -1;
646 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
654 return ERROR_NAND_DEVICE_NOT_PROBED;
656 if ((first_block < 0) || (last_block > device->num_blocks))
657 return ERROR_INVALID_ARGUMENTS;
659 /* make sure we know if a block is bad before erasing it */
660 for (i = first_block; i <= last_block; i++)
662 if (device->blocks[i].is_bad == -1)
664 nand_build_bbt(device, i, last_block);
669 for (i = first_block; i <= last_block; i++)
671 /* Send erase setup command */
672 device->controller->command(device, NAND_CMD_ERASE1);
674 page = i * (device->erase_size / device->page_size);
676 /* Send page address */
677 if (device->page_size <= 512)
680 device->controller->address(device, page & 0xff);
681 device->controller->address(device, (page >> 8) & 0xff);
683 /* 3rd cycle only on devices with more than 32 MiB */
684 if (device->address_cycles >= 4)
685 device->controller->address(device, (page >> 16) & 0xff);
687 /* 4th cycle only on devices with more than 8 GiB */
688 if (device->address_cycles >= 5)
689 device->controller->address(device, (page >> 24) & 0xff);
694 device->controller->address(device, page & 0xff);
695 device->controller->address(device, (page >> 8) & 0xff);
697 /* 3rd cycle only on devices with more than 128 MiB */
698 if (device->address_cycles >= 5)
699 device->controller->address(device, (page >> 16) & 0xff);
702 /* Send erase confirm command */
703 device->controller->command(device, NAND_CMD_ERASE2);
705 retval = device->controller->nand_ready ?
706 device->controller->nand_ready(device, 1000) :
707 nand_poll_ready(device, 1000);
709 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
710 return ERROR_NAND_OPERATION_TIMEOUT;
713 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
715 LOG_ERROR("couldn't read status");
716 return ERROR_NAND_OPERATION_FAILED;
721 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
722 return ERROR_NAND_OPERATION_FAILED;
725 device->blocks[i].is_erased = 1;
732 static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
737 return ERROR_NAND_DEVICE_NOT_PROBED;
739 if (address % device->page_size)
741 LOG_ERROR("reads need to be page aligned");
742 return ERROR_NAND_OPERATION_FAILED;
745 page = malloc(device->page_size);
747 while (data_size > 0 )
749 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
753 page_address = address / device->page_size;
755 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
757 memcpy(data, page, thisrun_size);
759 address += thisrun_size;
760 data += thisrun_size;
761 data_size -= thisrun_size;
769 static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
774 return ERROR_NAND_DEVICE_NOT_PROBED;
776 if (address % device->page_size)
778 LOG_ERROR("writes need to be page aligned");
779 return ERROR_NAND_OPERATION_FAILED;
782 page = malloc(device->page_size);
784 while (data_size > 0 )
786 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
789 memset(page, 0xff, device->page_size);
790 memcpy(page, data, thisrun_size);
792 page_address = address / device->page_size;
794 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
796 address += thisrun_size;
797 data += thisrun_size;
798 data_size -= thisrun_size;
807 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
812 return ERROR_NAND_DEVICE_NOT_PROBED;
814 block = page / (device->erase_size / device->page_size);
815 if (device->blocks[block].is_erased == 1)
816 device->blocks[block].is_erased = 0;
818 if (device->use_raw || device->controller->write_page == NULL)
819 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
821 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
824 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
827 return ERROR_NAND_DEVICE_NOT_PROBED;
829 if (device->use_raw || device->controller->read_page == NULL)
830 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
832 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
835 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
840 return ERROR_NAND_DEVICE_NOT_PROBED;
842 if (device->page_size <= 512)
844 /* small page device */
846 device->controller->command(device, NAND_CMD_READ0);
848 device->controller->command(device, NAND_CMD_READOOB);
850 /* column (always 0, we start at the beginning of a page/OOB area) */
851 device->controller->address(device, 0x0);
854 device->controller->address(device, page & 0xff);
855 device->controller->address(device, (page >> 8) & 0xff);
857 /* 4th cycle only on devices with more than 32 MiB */
858 if (device->address_cycles >= 4)
859 device->controller->address(device, (page >> 16) & 0xff);
861 /* 5th cycle only on devices with more than 8 GiB */
862 if (device->address_cycles >= 5)
863 device->controller->address(device, (page >> 24) & 0xff);
867 /* large page device */
868 device->controller->command(device, NAND_CMD_READ0);
870 /* column (0 when we start at the beginning of a page,
871 * or 2048 for the beginning of OOB area)
873 device->controller->address(device, 0x0);
875 device->controller->address(device, 0x0);
877 device->controller->address(device, 0x8);
880 device->controller->address(device, page & 0xff);
881 device->controller->address(device, (page >> 8) & 0xff);
883 /* 5th cycle only on devices with more than 128 MiB */
884 if (device->address_cycles >= 5)
885 device->controller->address(device, (page >> 16) & 0xff);
887 /* large page devices need a start command */
888 device->controller->command(device, NAND_CMD_READSTART);
891 if (device->controller->nand_ready) {
892 if (!device->controller->nand_ready(device, 100))
893 return ERROR_NAND_OPERATION_TIMEOUT;
900 if (device->controller->read_block_data != NULL)
901 (device->controller->read_block_data)(device, data, data_size);
904 for (i = 0; i < data_size;)
906 if (device->device->options & NAND_BUSWIDTH_16)
908 device->controller->read_data(device, data);
914 device->controller->read_data(device, data);
924 if (device->controller->read_block_data != NULL)
925 (device->controller->read_block_data)(device, oob, oob_size);
928 for (i = 0; i < oob_size;)
930 if (device->device->options & NAND_BUSWIDTH_16)
932 device->controller->read_data(device, oob);
938 device->controller->read_data(device, oob);
949 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
956 return ERROR_NAND_DEVICE_NOT_PROBED;
958 device->controller->command(device, NAND_CMD_SEQIN);
960 if (device->page_size <= 512)
962 /* column (always 0, we start at the beginning of a page/OOB area) */
963 device->controller->address(device, 0x0);
966 device->controller->address(device, page & 0xff);
967 device->controller->address(device, (page >> 8) & 0xff);
969 /* 4th cycle only on devices with more than 32 MiB */
970 if (device->address_cycles >= 4)
971 device->controller->address(device, (page >> 16) & 0xff);
973 /* 5th cycle only on devices with more than 8 GiB */
974 if (device->address_cycles >= 5)
975 device->controller->address(device, (page >> 24) & 0xff);
979 /* column (0 when we start at the beginning of a page,
980 * or 2048 for the beginning of OOB area)
982 device->controller->address(device, 0x0);
984 device->controller->address(device, 0x0);
986 device->controller->address(device, 0x8);
989 device->controller->address(device, page & 0xff);
990 device->controller->address(device, (page >> 8) & 0xff);
992 /* 5th cycle only on devices with more than 128 MiB */
993 if (device->address_cycles >= 5)
994 device->controller->address(device, (page >> 16) & 0xff);
999 if (device->controller->write_block_data != NULL)
1000 (device->controller->write_block_data)(device, data, data_size);
1003 for (i = 0; i < data_size;)
1005 if (device->device->options & NAND_BUSWIDTH_16)
1007 u16 data_buf = le_to_h_u16(data);
1008 device->controller->write_data(device, data_buf);
1014 device->controller->write_data(device, *data);
1024 if (device->controller->write_block_data != NULL)
1025 (device->controller->write_block_data)(device, oob, oob_size);
1028 for (i = 0; i < oob_size;)
1030 if (device->device->options & NAND_BUSWIDTH_16)
1032 u16 oob_buf = le_to_h_u16(data);
1033 device->controller->write_data(device, oob_buf);
1039 device->controller->write_data(device, *oob);
1047 device->controller->command(device, NAND_CMD_PAGEPROG);
1049 retval = device->controller->nand_ready ?
1050 device->controller->nand_ready(device, 100) :
1051 nand_poll_ready(device, 100);
1053 return ERROR_NAND_OPERATION_TIMEOUT;
1055 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1057 LOG_ERROR("couldn't read status");
1058 return ERROR_NAND_OPERATION_FAILED;
1061 if (status & NAND_STATUS_FAIL)
1063 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1064 return ERROR_NAND_OPERATION_FAILED;
1070 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1077 command_print(cmd_ctx, "no NAND flash devices configured");
1081 for (p = nand_devices; p; p = p->next)
1084 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1085 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1087 command_print(cmd_ctx, "#%i: not probed");
1093 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1101 if ((argc < 1) || (argc > 3))
1103 return ERROR_COMMAND_SYNTAX_ERROR;
1109 first = last = strtoul(args[1], NULL, 0);
1113 first = strtoul(args[1], NULL, 0);
1114 last = strtoul(args[2], NULL, 0);
1117 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1122 if (first >= p->num_blocks)
1123 first = p->num_blocks - 1;
1125 if (last >= p->num_blocks)
1126 last = p->num_blocks - 1;
1128 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1129 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1131 for (j = first; j <= last; j++)
1133 char *erase_state, *bad_state;
1135 if (p->blocks[j].is_erased == 0)
1136 erase_state = "not erased";
1137 else if (p->blocks[j].is_erased == 1)
1138 erase_state = "erased";
1140 erase_state = "erase state unknown";
1142 if (p->blocks[j].is_bad == 0)
1144 else if (p->blocks[j].is_bad == 1)
1145 bad_state = " (marked bad)";
1147 bad_state = " (block condition unknown)";
1149 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1150 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1151 erase_state, bad_state);
1156 command_print(cmd_ctx, "#%i: not probed");
1163 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1170 return ERROR_COMMAND_SYNTAX_ERROR;
1173 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1176 if ((retval = nand_probe(p)) == ERROR_OK)
1178 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1180 else if (retval == ERROR_NAND_OPERATION_FAILED)
1182 command_print(cmd_ctx, "probing failed for NAND flash device");
1186 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1191 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1197 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1204 return ERROR_COMMAND_SYNTAX_ERROR;
1208 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1211 int first = strtoul(args[1], NULL, 0);
1212 int last = strtoul(args[2], NULL, 0);
1214 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1216 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1218 else if (retval == ERROR_NAND_OPERATION_FAILED)
1220 command_print(cmd_ctx, "erase failed");
1224 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1229 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1235 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1242 if ((argc < 1) || (argc > 3) || (argc == 2))
1244 return ERROR_COMMAND_SYNTAX_ERROR;
1250 first = strtoul(args[1], NULL, 0);
1251 last = strtoul(args[2], NULL, 0);
1254 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1257 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1259 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1261 else if (retval == ERROR_NAND_OPERATION_FAILED)
1263 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1267 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1272 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1278 static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1284 return ERROR_COMMAND_SYNTAX_ERROR;
1288 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1295 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1301 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1306 enum oob_formats oob_format = NAND_OOB_NONE;
1310 duration_t duration;
1311 char *duration_text;
1317 return ERROR_COMMAND_SYNTAX_ERROR;
1321 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1328 const int *eccpos = NULL;
1330 offset = strtoul(args[2], NULL, 0);
1335 for (i = 3; i < argc; i++)
1337 if (!strcmp(args[i], "oob_raw"))
1338 oob_format |= NAND_OOB_RAW;
1339 else if (!strcmp(args[i], "oob_only"))
1340 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1341 else if (!strcmp(args[i], "oob_softecc"))
1342 oob_format |= NAND_OOB_SW_ECC;
1345 command_print(cmd_ctx, "unknown option: %s", args[i]);
1346 return ERROR_COMMAND_SYNTAX_ERROR;
1351 duration_start_measure(&duration);
1353 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1358 buf_cnt = binary_size = fileio.size;
1360 if (!(oob_format & NAND_OOB_ONLY))
1362 page_size = p->page_size;
1363 page = malloc(p->page_size);
1366 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC))
1368 if (p->page_size == 512) {
1370 eccpos = nand_oob_16.eccpos;
1371 } else if (p->page_size == 2048) {
1373 eccpos = nand_oob_64.eccpos;
1375 oob = malloc(oob_size);
1378 if (offset % p->page_size)
1380 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1381 fileio_close(&fileio);
1393 fileio_read(&fileio, page_size, page, &size_read);
1394 buf_cnt -= size_read;
1395 if (size_read < page_size)
1397 memset(page + size_read, 0xff, page_size - size_read);
1401 if (oob_format & NAND_OOB_SW_ECC)
1405 memset(oob, 0xff, oob_size);
1406 for (i = 0, j = 0; i < page_size; i += 256) {
1407 nand_calculate_ecc(p, page+i, ecc);
1408 oob[eccpos[j++]] = ecc[0];
1409 oob[eccpos[j++]] = ecc[1];
1410 oob[eccpos[j++]] = ecc[2];
1413 else if (NULL != oob)
1415 fileio_read(&fileio, oob_size, oob, &size_read);
1416 buf_cnt -= size_read;
1417 if (size_read < oob_size)
1419 memset(oob + size_read, 0xff, oob_size - size_read);
1423 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1425 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1426 args[1], args[0], offset);
1428 fileio_close(&fileio);
1434 offset += page_size;
1437 fileio_close(&fileio);
1442 duration_stop_measure(&duration, &duration_text);
1443 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1444 args[1], args[0], offset, duration_text);
1445 free(duration_text);
1446 duration_text = NULL;
1450 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1456 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1462 return ERROR_COMMAND_SYNTAX_ERROR;
1465 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1471 duration_t duration;
1472 char *duration_text;
1479 u32 address = strtoul(args[2], NULL, 0);
1480 u32 size = strtoul(args[3], NULL, 0);
1482 enum oob_formats oob_format = NAND_OOB_NONE;
1487 for (i = 4; i < argc; i++)
1489 if (!strcmp(args[i], "oob_raw"))
1490 oob_format |= NAND_OOB_RAW;
1491 else if (!strcmp(args[i], "oob_only"))
1492 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1494 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1498 if ((address % p->page_size) || (size % p->page_size))
1500 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1504 if (!(oob_format & NAND_OOB_ONLY))
1506 page_size = p->page_size;
1507 page = malloc(p->page_size);
1510 if (oob_format & NAND_OOB_RAW)
1512 if (p->page_size == 512)
1514 else if (p->page_size == 2048)
1516 oob = malloc(oob_size);
1519 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1524 duration_start_measure(&duration);
1529 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1531 command_print(cmd_ctx, "reading NAND flash page failed");
1534 fileio_close(&fileio);
1540 fileio_write(&fileio, page_size, page, &size_written);
1541 bytes_done += page_size;
1546 fileio_write(&fileio, oob_size, oob, &size_written);
1547 bytes_done += oob_size;
1550 size -= p->page_size;
1551 address += p->page_size;
1558 fileio_close(&fileio);
1560 duration_stop_measure(&duration, &duration_text);
1561 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1562 free(duration_text);
1563 duration_text = NULL;
1567 command_print(cmd_ctx, "#%i: not probed");
1572 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1578 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1582 if ((argc < 1) || (argc > 2))
1584 return ERROR_COMMAND_SYNTAX_ERROR;
1587 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1594 if (strcmp("enable", args[1]) == 0)
1598 else if (strcmp("disable", args[1]) == 0)
1604 return ERROR_COMMAND_SYNTAX_ERROR;
1608 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1612 command_print(cmd_ctx, "#%i: not probed");
1617 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);