git.sur5r.net Git - openocd/blob - src/flash/nand.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Partially based on drivers/mtd/nand_ids.c from Linux.                 *
   6  *   Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de>               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "nand.h"
  28 #include "time_support.h"
  29 #include "fileio.h"
  30
  31 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  32 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  33 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  34 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  36 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38
  39 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40
  41 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  42 //static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size);
  43
  44 static int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  45
  46 /* NAND flash controller
  47  */
  48 extern nand_flash_controller_t davinci_nand_controller;
  49 extern nand_flash_controller_t lpc3180_nand_controller;
  50 extern nand_flash_controller_t orion_nand_controller;
  51 extern nand_flash_controller_t s3c2410_nand_controller;
  52 extern nand_flash_controller_t s3c2412_nand_controller;
  53 extern nand_flash_controller_t s3c2440_nand_controller;
  54 extern nand_flash_controller_t s3c2443_nand_controller;
  55 extern nand_flash_controller_t imx31_nand_flash_controller;
  56
  57 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
  58
  59 static nand_flash_controller_t *nand_flash_controllers[] =
  60 {
  61         &davinci_nand_controller,
  62         &lpc3180_nand_controller,
  63         &orion_nand_controller,
  64         &s3c2410_nand_controller,
  65         &s3c2412_nand_controller,
  66         &s3c2440_nand_controller,
  67         &s3c2443_nand_controller,
  68         &imx31_nand_flash_controller,
  69 /*      &boundary_scan_nand_controller, */
  70         NULL
  71 };
  72
  73 /* configured NAND devices and NAND Flash command handler */
  74 static nand_device_t *nand_devices = NULL;
  75 static command_t *nand_cmd;
  76
  77 /*      Chip ID list
  78  *
  79  *      Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
  80  *      options
  81  *
  82  *      Pagesize; 0, 256, 512
  83  *      0       get this information from the extended chip ID
  84  *      256     256 Byte page size
  85  *      512     512 Byte page size
  86  */
  87 static nand_info_t nand_flash_ids[] =
  88 {
  89         /* start "museum" IDs */
  90         {"NAND 1MiB 5V 8-bit",          0x6e, 256, 1, 0x1000, 0},
  91         {"NAND 2MiB 5V 8-bit",          0x64, 256, 2, 0x1000, 0},
  92         {"NAND 4MiB 5V 8-bit",          0x6b, 512, 4, 0x2000, 0},
  93         {"NAND 1MiB 3,3V 8-bit",        0xe8, 256, 1, 0x1000, 0},
  94         {"NAND 1MiB 3,3V 8-bit",        0xec, 256, 1, 0x1000, 0},
  95         {"NAND 2MiB 3,3V 8-bit",        0xea, 256, 2, 0x1000, 0},
  96         {"NAND 4MiB 3,3V 8-bit",        0xd5, 512, 4, 0x2000, 0},
  97         {"NAND 4MiB 3,3V 8-bit",        0xe3, 512, 4, 0x2000, 0},
  98         {"NAND 4MiB 3,3V 8-bit",        0xe5, 512, 4, 0x2000, 0},
  99         {"NAND 8MiB 3,3V 8-bit",        0xd6, 512, 8, 0x2000, 0},
 100
 101         {"NAND 8MiB 1,8V 8-bit",        0x39, 512, 8, 0x2000, 0},
 102         {"NAND 8MiB 3,3V 8-bit",        0xe6, 512, 8, 0x2000, 0},
 103         {"NAND 8MiB 1,8V 16-bit",       0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
 104         {"NAND 8MiB 3,3V 16-bit",       0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
 105         /* end "museum" IDs */
 106
 107         {"NAND 16MiB 1,8V 8-bit",       0x33, 512, 16, 0x4000, 0},
 108         {"NAND 16MiB 3,3V 8-bit",       0x73, 512, 16, 0x4000, 0},
 109         {"NAND 16MiB 1,8V 16-bit",      0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
 110         {"NAND 16MiB 3,3V 16-bit",      0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
 111
 112         {"NAND 32MiB 1,8V 8-bit",       0x35, 512, 32, 0x4000, 0},
 113         {"NAND 32MiB 3,3V 8-bit",       0x75, 512, 32, 0x4000, 0},
 114         {"NAND 32MiB 1,8V 16-bit",      0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
 115         {"NAND 32MiB 3,3V 16-bit",      0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
 116
 117         {"NAND 64MiB 1,8V 8-bit",       0x36, 512, 64, 0x4000, 0},
 118         {"NAND 64MiB 3,3V 8-bit",       0x76, 512, 64, 0x4000, 0},
 119         {"NAND 64MiB 1,8V 16-bit",      0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
 120         {"NAND 64MiB 3,3V 16-bit",      0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
 121
 122         {"NAND 128MiB 1,8V 8-bit",      0x78, 512, 128, 0x4000, 0},
 123         {"NAND 128MiB 1,8V 8-bit",      0x39, 512, 128, 0x4000, 0},
 124         {"NAND 128MiB 3,3V 8-bit",      0x79, 512, 128, 0x4000, 0},
 125         {"NAND 128MiB 1,8V 16-bit",     0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 126         {"NAND 128MiB 1,8V 16-bit",     0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 127         {"NAND 128MiB 3,3V 16-bit",     0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 128         {"NAND 128MiB 3,3V 16-bit",     0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 129
 130         {"NAND 256MiB 3,3V 8-bit",      0x71, 512, 256, 0x4000, 0},
 131
 132         {"NAND 64MiB 1,8V 8-bit",       0xA2, 0,  64, 0, LP_OPTIONS},
 133         {"NAND 64MiB 3,3V 8-bit",       0xF2, 0,  64, 0, LP_OPTIONS},
 134         {"NAND 64MiB 1,8V 16-bit",      0xB2, 0,  64, 0, LP_OPTIONS16},
 135         {"NAND 64MiB 3,3V 16-bit",      0xC2, 0,  64, 0, LP_OPTIONS16},
 136
 137         {"NAND 128MiB 1,8V 8-bit",      0xA1, 0, 128, 0, LP_OPTIONS},
 138         {"NAND 128MiB 3,3V 8-bit",      0xF1, 0, 128, 0, LP_OPTIONS},
 139         {"NAND 128MiB 1,8V 16-bit",     0xB1, 0, 128, 0, LP_OPTIONS16},
 140         {"NAND 128MiB 3,3V 16-bit",     0xC1, 0, 128, 0, LP_OPTIONS16},
 141
 142         {"NAND 256MiB 1,8V 8-bit",      0xAA, 0, 256, 0, LP_OPTIONS},
 143         {"NAND 256MiB 3,3V 8-bit",      0xDA, 0, 256, 0, LP_OPTIONS},
 144         {"NAND 256MiB 1,8V 16-bit",     0xBA, 0, 256, 0, LP_OPTIONS16},
 145         {"NAND 256MiB 3,3V 16-bit",     0xCA, 0, 256, 0, LP_OPTIONS16},
 146
 147         {"NAND 512MiB 1,8V 8-bit",      0xAC, 0, 512, 0, LP_OPTIONS},
 148         {"NAND 512MiB 3,3V 8-bit",      0xDC, 0, 512, 0, LP_OPTIONS},
 149         {"NAND 512MiB 1,8V 16-bit",     0xBC, 0, 512, 0, LP_OPTIONS16},
 150         {"NAND 512MiB 3,3V 16-bit",     0xCC, 0, 512, 0, LP_OPTIONS16},
 151
 152         {"NAND 1GiB 1,8V 8-bit",        0xA3, 0, 1024, 0, LP_OPTIONS},
 153         {"NAND 1GiB 3,3V 8-bit",        0xD3, 0, 1024, 0, LP_OPTIONS},
 154         {"NAND 1GiB 1,8V 16-bit",       0xB3, 0, 1024, 0, LP_OPTIONS16},
 155         {"NAND 1GiB 3,3V 16-bit",       0xC3, 0, 1024, 0, LP_OPTIONS16},
 156
 157         {"NAND 2GiB 1,8V 8-bit",        0xA5, 0, 2048, 0, LP_OPTIONS},
 158         {"NAND 2GiB 3,3V 8-bit",        0xD5, 0, 2048, 0, LP_OPTIONS},
 159         {"NAND 2GiB 1,8V 16-bit",       0xB5, 0, 2048, 0, LP_OPTIONS16},
 160         {"NAND 2GiB 3,3V 16-bit",       0xC5, 0, 2048, 0, LP_OPTIONS16},
 161
 162         {NULL, 0, 0, 0, 0, 0 }
 163 };
 164
 165 /* Manufacturer ID list
 166  */
 167 static nand_manufacturer_t nand_manuf_ids[] =
 168 {
 169         {0x0, "unknown"},
 170         {NAND_MFR_TOSHIBA, "Toshiba"},
 171         {NAND_MFR_SAMSUNG, "Samsung"},
 172         {NAND_MFR_FUJITSU, "Fujitsu"},
 173         {NAND_MFR_NATIONAL, "National"},
 174         {NAND_MFR_RENESAS, "Renesas"},
 175         {NAND_MFR_STMICRO, "ST Micro"},
 176         {NAND_MFR_HYNIX, "Hynix"},
 177         {NAND_MFR_MICRON, "Micron"},
 178         {0x0, NULL},
 179 };
 180
 181 /*
 182  * Define default oob placement schemes for large and small page devices
 183  */
 184
 185 #if 0
 186 static nand_ecclayout_t nand_oob_8 = {
 187         .eccbytes = 3,
 188         .eccpos = {0, 1, 2},
 189         .oobfree = {
 190                 {.offset = 3,
 191                  .length = 2},
 192                 {.offset = 6,
 193                  .length = 2}}
 194 };
 195 #endif
 196
 197 static nand_ecclayout_t nand_oob_16 = {
 198         .eccbytes = 6,
 199         .eccpos = {0, 1, 2, 3, 6, 7},
 200         .oobfree = {
 201                 {.offset = 8,
 202                  . length = 8}}
 203 };
 204
 205 static nand_ecclayout_t nand_oob_64 = {
 206         .eccbytes = 24,
 207         .eccpos = {
 208                    40, 41, 42, 43, 44, 45, 46, 47,
 209                    48, 49, 50, 51, 52, 53, 54, 55,
 210                    56, 57, 58, 59, 60, 61, 62, 63},
 211         .oobfree = {
 212                 {.offset = 2,
 213                  .length = 38}}
 214 };
 215
 216 /* nand device <nand_controller> [controller options]
 217  */
 218 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 219 {
 220         int i;
 221         int retval;
 222
 223         if (argc < 1)
 224         {
 225                 LOG_WARNING("incomplete flash device nand configuration");
 226                 return ERROR_FLASH_BANK_INVALID;
 227         }
 228
 229         for (i = 0; nand_flash_controllers[i]; i++)
 230         {
 231                 nand_device_t *p, *c;
 232
 233                 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
 234                 {
 235                         /* register flash specific commands */
 236                         if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
 237                         {
 238                                 LOG_ERROR("couldn't register '%s' commands", args[0]);
 239                                 return retval;
 240                         }
 241
 242                         c = malloc(sizeof(nand_device_t));
 243
 244                         c->controller = nand_flash_controllers[i];
 245                         c->controller_priv = NULL;
 246                         c->manufacturer = NULL;
 247                         c->device = NULL;
 248                         c->bus_width = 0;
 249                         c->address_cycles = 0;
 250                         c->page_size = 0;
 251                         c->use_raw = 0;
 252                         c->next = NULL;
 253
 254                         if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
 255                         {
 256                                 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
 257                                 free(c);
 258                                 return ERROR_OK;
 259                         }
 260
 261                         /* put NAND device in linked list */
 262                         if (nand_devices)
 263                         {
 264                                 /* find last flash device */
 265                                 for (p = nand_devices; p && p->next; p = p->next);
 266                                 if (p)
 267                                         p->next = c;
 268                         }
 269                         else
 270                         {
 271                                 nand_devices = c;
 272                         }
 273
 274                         return ERROR_OK;
 275                 }
 276         }
 277
 278         /* no valid NAND controller was found (i.e. the configuration option,
 279          * didn't match one of the compiled-in controllers)
 280          */
 281         LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
 282         LOG_ERROR("compiled-in NAND flash controllers:");
 283         for (i = 0; nand_flash_controllers[i]; i++)
 284         {
 285                 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
 286         }
 287
 288         return ERROR_OK;
 289 }
 290
 291 int nand_register_commands(struct command_context_s *cmd_ctx)
 292 {
 293         nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
 294
 295         register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
 296
 297         return ERROR_OK;
 298 }
 299
 300 int nand_init(struct command_context_s *cmd_ctx)
 301 {
 302         if (nand_devices)
 303         {
 304                 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
 305                                                  "list configured NAND flash devices");
 306                 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
 307                                                  "print info about NAND flash device <num>");
 308                 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
 309                                                  "identify NAND flash device <num>");
 310                 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
 311                                                  "check NAND flash device <num> for bad blocks [<offset> <length>]");
 312                 register_command(cmd_ctx, nand_cmd, "erase",
 313                                 handle_nand_erase_command, COMMAND_EXEC,
 314                                 "erase blocks on NAND flash device <num> [<offset> <length>]");
 315                 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
 316                                                  "dump from NAND flash device <num> <filename> "
 317                                                  "<offset> <length> [oob_raw | oob_only]");
 318                 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
 319                                                  "write to NAND flash device <num> <filename> <offset> [oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
 320                 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
 321                                                  "raw access to NAND flash device <num> ['enable'|'disable']");
 322         }
 323
 324         return ERROR_OK;
 325 }
 326
 327 nand_device_t *get_nand_device_by_num(int num)
 328 {
 329         nand_device_t *p;
 330         int i = 0;
 331
 332         for (p = nand_devices; p; p = p->next)
 333         {
 334                 if (i++ == num)
 335                 {
 336                         return p;
 337                 }
 338         }
 339
 340         return NULL;
 341 }
 342
 343 int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
 344                 char *str, nand_device_t **device)
 345 {
 346         unsigned num;
 347         COMMAND_PARSE_NUMBER(uint, str, num);
 348         *device = get_nand_device_by_num(num);
 349         if (!*device) {
 350                 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", str);
 351                 return ERROR_INVALID_ARGUMENTS;
 352         }
 353         return ERROR_OK;
 354 }
 355
 356 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
 357 {
 358         uint32_t page = 0x0;
 359         int i;
 360         uint8_t oob[6];
 361
 362         if ((first < 0) || (first >= device->num_blocks))
 363                 first = 0;
 364
 365         if ((last >= device->num_blocks) || (last == -1))
 366                 last = device->num_blocks - 1;
 367
 368         for (i = first; i < last; i++)
 369         {
 370                 nand_read_page(device, page, NULL, 0, oob, 6);
 371
 372                 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
 373                         || (((device->page_size == 512) && (oob[5] != 0xff)) ||
 374                                 ((device->page_size == 2048) && (oob[0] != 0xff))))
 375                 {
 376                         LOG_WARNING("bad block: %i", i);
 377                         device->blocks[i].is_bad = 1;
 378                 }
 379                 else
 380                 {
 381                         device->blocks[i].is_bad = 0;
 382                 }
 383
 384                 page += (device->erase_size / device->page_size);
 385         }
 386
 387         return ERROR_OK;
 388 }
 389
 390 int nand_read_status(struct nand_device_s *device, uint8_t *status)
 391 {
 392         if (!device->device)
 393                 return ERROR_NAND_DEVICE_NOT_PROBED;
 394
 395         /* Send read status command */
 396         device->controller->command(device, NAND_CMD_STATUS);
 397
 398         alive_sleep(1);
 399
 400         /* read status */
 401         if (device->device->options & NAND_BUSWIDTH_16)
 402         {
 403                 uint16_t data;
 404                 device->controller->read_data(device, &data);
 405                 *status = data & 0xff;
 406         }
 407         else
 408         {
 409                 device->controller->read_data(device, status);
 410         }
 411
 412         return ERROR_OK;
 413 }
 414
 415 static int nand_poll_ready(struct nand_device_s *device, int timeout)
 416 {
 417         uint8_t status;
 418
 419         device->controller->command(device, NAND_CMD_STATUS);
 420         do {
 421                 if (device->device->options & NAND_BUSWIDTH_16) {
 422                         uint16_t data;
 423                         device->controller->read_data(device, &data);
 424                         status = data & 0xff;
 425                 } else {
 426                         device->controller->read_data(device, &status);
 427                 }
 428                 if (status & NAND_STATUS_READY)
 429                         break;
 430                 alive_sleep(1);
 431         } while (timeout--);
 432
 433         return (status & NAND_STATUS_READY) != 0;
 434 }
 435
 436 int nand_probe(struct nand_device_s *device)
 437 {
 438         uint8_t manufacturer_id, device_id;
 439         uint8_t id_buff[6];
 440         int retval;
 441         int i;
 442
 443         /* clear device data */
 444         device->device = NULL;
 445         device->manufacturer = NULL;
 446
 447         /* clear device parameters */
 448         device->bus_width = 0;
 449         device->address_cycles = 0;
 450         device->page_size = 0;
 451         device->erase_size = 0;
 452
 453         /* initialize controller (device parameters are zero, use controller default) */
 454         if ((retval = device->controller->init(device) != ERROR_OK))
 455         {
 456                 switch (retval)
 457                 {
 458                         case ERROR_NAND_OPERATION_FAILED:
 459                                 LOG_DEBUG("controller initialization failed");
 460                                 return ERROR_NAND_OPERATION_FAILED;
 461                         case ERROR_NAND_OPERATION_NOT_SUPPORTED:
 462                                 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
 463                                 return ERROR_NAND_OPERATION_FAILED;
 464                         default:
 465                                 LOG_ERROR("BUG: unknown controller initialization failure");
 466                                 return ERROR_NAND_OPERATION_FAILED;
 467                 }
 468         }
 469
 470         device->controller->command(device, NAND_CMD_RESET);
 471         device->controller->reset(device);
 472
 473         device->controller->command(device, NAND_CMD_READID);
 474         device->controller->address(device, 0x0);
 475
 476         if (device->bus_width == 8)
 477         {
 478                 device->controller->read_data(device, &manufacturer_id);
 479                 device->controller->read_data(device, &device_id);
 480         }
 481         else
 482         {
 483                 uint16_t data_buf;
 484                 device->controller->read_data(device, &data_buf);
 485                 manufacturer_id = data_buf & 0xff;
 486                 device->controller->read_data(device, &data_buf);
 487                 device_id = data_buf & 0xff;
 488         }
 489
 490         for (i = 0; nand_flash_ids[i].name; i++)
 491         {
 492                 if (nand_flash_ids[i].id == device_id)
 493                 {
 494                         device->device = &nand_flash_ids[i];
 495                         break;
 496                 }
 497         }
 498
 499         for (i = 0; nand_manuf_ids[i].name; i++)
 500         {
 501                 if (nand_manuf_ids[i].id == manufacturer_id)
 502                 {
 503                         device->manufacturer = &nand_manuf_ids[i];
 504                         break;
 505                 }
 506         }
 507
 508         if (!device->manufacturer)
 509         {
 510                 device->manufacturer = &nand_manuf_ids[0];
 511                 device->manufacturer->id = manufacturer_id;
 512         }
 513
 514         if (!device->device)
 515         {
 516                 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
 517                         manufacturer_id, device_id);
 518                 return ERROR_NAND_OPERATION_FAILED;
 519         }
 520
 521         LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
 522
 523         /* initialize device parameters */
 524
 525         /* bus width */
 526         if (device->device->options & NAND_BUSWIDTH_16)
 527                 device->bus_width = 16;
 528         else
 529                 device->bus_width = 8;
 530
 531         /* Do we need extended device probe information? */
 532         if (device->device->page_size == 0 ||
 533             device->device->erase_size == 0)
 534         {
 535                 if (device->bus_width == 8)
 536                 {
 537                         device->controller->read_data(device, id_buff + 3);
 538                         device->controller->read_data(device, id_buff + 4);
 539                         device->controller->read_data(device, id_buff + 5);
 540                 }
 541                 else
 542                 {
 543                         uint16_t data_buf;
 544
 545                         device->controller->read_data(device, &data_buf);
 546                         id_buff[3] = data_buf;
 547
 548                         device->controller->read_data(device, &data_buf);
 549                         id_buff[4] = data_buf;
 550
 551                         device->controller->read_data(device, &data_buf);
 552                         id_buff[5] = data_buf >> 8;
 553                 }
 554         }
 555
 556         /* page size */
 557         if (device->device->page_size == 0)
 558         {
 559                 device->page_size = 1 << (10 + (id_buff[4] & 3));
 560         }
 561         else if (device->device->page_size == 256)
 562         {
 563                 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
 564                 return ERROR_NAND_OPERATION_FAILED;
 565         }
 566         else
 567         {
 568                 device->page_size = device->device->page_size;
 569         }
 570
 571         /* number of address cycles */
 572         if (device->page_size <= 512)
 573         {
 574                 /* small page devices */
 575                 if (device->device->chip_size <= 32)
 576                         device->address_cycles = 3;
 577                 else if (device->device->chip_size <= 8*1024)
 578                         device->address_cycles = 4;
 579                 else
 580                 {
 581                         LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
 582                         device->address_cycles = 5;
 583                 }
 584         }
 585         else
 586         {
 587                 /* large page devices */
 588                 if (device->device->chip_size <= 128)
 589                         device->address_cycles = 4;
 590                 else if (device->device->chip_size <= 32*1024)
 591                         device->address_cycles = 5;
 592                 else
 593                 {
 594                         LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
 595                         device->address_cycles = 6;
 596                 }
 597         }
 598
 599         /* erase size */
 600         if (device->device->erase_size == 0)
 601         {
 602                 switch ((id_buff[4] >> 4) & 3) {
 603                 case 0:
 604                         device->erase_size = 64 << 10;
 605                         break;
 606                 case 1:
 607                         device->erase_size = 128 << 10;
 608                         break;
 609                 case 2:
 610                         device->erase_size = 256 << 10;
 611                         break;
 612                 case 3:
 613                         device->erase_size =512 << 10;
 614                         break;
 615                 }
 616         }
 617         else
 618         {
 619                 device->erase_size = device->device->erase_size;
 620         }
 621
 622         /* initialize controller, but leave parameters at the controllers default */
 623         if ((retval = device->controller->init(device) != ERROR_OK))
 624         {
 625                 switch (retval)
 626                 {
 627                         case ERROR_NAND_OPERATION_FAILED:
 628                                 LOG_DEBUG("controller initialization failed");
 629                                 return ERROR_NAND_OPERATION_FAILED;
 630                         case ERROR_NAND_OPERATION_NOT_SUPPORTED:
 631                                 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
 632                                         device->bus_width, device->address_cycles, device->page_size);
 633                                 return ERROR_NAND_OPERATION_FAILED;
 634                         default:
 635                                 LOG_ERROR("BUG: unknown controller initialization failure");
 636                                 return ERROR_NAND_OPERATION_FAILED;
 637                 }
 638         }
 639
 640         device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
 641         device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
 642
 643         for (i = 0; i < device->num_blocks; i++)
 644         {
 645                 device->blocks[i].size = device->erase_size;
 646                 device->blocks[i].offset = i * device->erase_size;
 647                 device->blocks[i].is_erased = -1;
 648                 device->blocks[i].is_bad = -1;
 649         }
 650
 651         return ERROR_OK;
 652 }
 653
 654 static int nand_erase(struct nand_device_s *device, int first_block, int last_block)
 655 {
 656         int i;
 657         uint32_t page;
 658         uint8_t status;
 659         int retval;
 660
 661         if (!device->device)
 662                 return ERROR_NAND_DEVICE_NOT_PROBED;
 663
 664         if ((first_block < 0) || (last_block > device->num_blocks))
 665                 return ERROR_INVALID_ARGUMENTS;
 666
 667         /* make sure we know if a block is bad before erasing it */
 668         for (i = first_block; i <= last_block; i++)
 669         {
 670                 if (device->blocks[i].is_bad == -1)
 671                 {
 672                         nand_build_bbt(device, i, last_block);
 673                         break;
 674                 }
 675         }
 676
 677         for (i = first_block; i <= last_block; i++)
 678         {
 679                 /* Send erase setup command */
 680                 device->controller->command(device, NAND_CMD_ERASE1);
 681
 682                 page = i * (device->erase_size / device->page_size);
 683
 684                 /* Send page address */
 685                 if (device->page_size <= 512)
 686                 {
 687                         /* row */
 688                         device->controller->address(device, page & 0xff);
 689                         device->controller->address(device, (page >> 8) & 0xff);
 690
 691                         /* 3rd cycle only on devices with more than 32 MiB */
 692                         if (device->address_cycles >= 4)
 693                                 device->controller->address(device, (page >> 16) & 0xff);
 694
 695                         /* 4th cycle only on devices with more than 8 GiB */
 696                         if (device->address_cycles >= 5)
 697                                 device->controller->address(device, (page >> 24) & 0xff);
 698                 }
 699                 else
 700                 {
 701                         /* row */
 702                         device->controller->address(device, page & 0xff);
 703                         device->controller->address(device, (page >> 8) & 0xff);
 704
 705                         /* 3rd cycle only on devices with more than 128 MiB */
 706                         if (device->address_cycles >= 5)
 707                                 device->controller->address(device, (page >> 16) & 0xff);
 708                 }
 709
 710                 /* Send erase confirm command */
 711                 device->controller->command(device, NAND_CMD_ERASE2);
 712
 713                 retval = device->controller->nand_ready ?
 714                                 device->controller->nand_ready(device, 1000) :
 715                                 nand_poll_ready(device, 1000);
 716                 if (!retval) {
 717                         LOG_ERROR("timeout waiting for NAND flash block erase to complete");
 718                         return ERROR_NAND_OPERATION_TIMEOUT;
 719                 }
 720
 721                 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
 722                 {
 723                         LOG_ERROR("couldn't read status");
 724                         return ERROR_NAND_OPERATION_FAILED;
 725                 }
 726
 727                 if (status & 0x1)
 728                 {
 729                         LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
 730                                         (device->blocks[i].is_bad == 1)
 731                                                 ? "bad " : "",
 732                                         i, status);
 733                         /* continue; other blocks might still be erasable */
 734                 }
 735
 736                 device->blocks[i].is_erased = 1;
 737         }
 738
 739         return ERROR_OK;
 740 }
 741
 742 #if 0
 743 static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
 744 {
 745         uint8_t *page;
 746
 747         if (!device->device)
 748                 return ERROR_NAND_DEVICE_NOT_PROBED;
 749
 750         if (address % device->page_size)
 751         {
 752                 LOG_ERROR("reads need to be page aligned");
 753                 return ERROR_NAND_OPERATION_FAILED;
 754         }
 755
 756         page = malloc(device->page_size);
 757
 758         while (data_size > 0)
 759         {
 760                 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
 761                 uint32_t page_address;
 762
 763
 764                 page_address = address / device->page_size;
 765
 766                 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
 767
 768                 memcpy(data, page, thisrun_size);
 769
 770                 address += thisrun_size;
 771                 data += thisrun_size;
 772                 data_size -= thisrun_size;
 773         }
 774
 775         free(page);
 776
 777         return ERROR_OK;
 778 }
 779
 780 static int nand_write_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
 781 {
 782         uint8_t *page;
 783
 784         if (!device->device)
 785                 return ERROR_NAND_DEVICE_NOT_PROBED;
 786
 787         if (address % device->page_size)
 788         {
 789                 LOG_ERROR("writes need to be page aligned");
 790                 return ERROR_NAND_OPERATION_FAILED;
 791         }
 792
 793         page = malloc(device->page_size);
 794
 795         while (data_size > 0)
 796         {
 797                 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
 798                 uint32_t page_address;
 799
 800                 memset(page, 0xff, device->page_size);
 801                 memcpy(page, data, thisrun_size);
 802
 803                 page_address = address / device->page_size;
 804
 805                 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
 806
 807                 address += thisrun_size;
 808                 data += thisrun_size;
 809                 data_size -= thisrun_size;
 810         }
 811
 812         free(page);
 813
 814         return ERROR_OK;
 815 }
 816 #endif
 817
 818 int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 819 {
 820         uint32_t block;
 821
 822         if (!device->device)
 823                 return ERROR_NAND_DEVICE_NOT_PROBED;
 824
 825         block = page / (device->erase_size / device->page_size);
 826         if (device->blocks[block].is_erased == 1)
 827                 device->blocks[block].is_erased = 0;
 828
 829         if (device->use_raw || device->controller->write_page == NULL)
 830                 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
 831         else
 832                 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
 833 }
 834
 835 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 836 {
 837         if (!device->device)
 838                 return ERROR_NAND_DEVICE_NOT_PROBED;
 839
 840         if (device->use_raw || device->controller->read_page == NULL)
 841                 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
 842         else
 843                 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
 844 }
 845
 846 int nand_read_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 847 {
 848         uint32_t i;
 849
 850         if (!device->device)
 851                 return ERROR_NAND_DEVICE_NOT_PROBED;
 852
 853         if (device->page_size <= 512)
 854         {
 855                 /* small page device */
 856                 if (data)
 857                         device->controller->command(device, NAND_CMD_READ0);
 858                 else
 859                         device->controller->command(device, NAND_CMD_READOOB);
 860
 861                 /* column (always 0, we start at the beginning of a page/OOB area) */
 862                 device->controller->address(device, 0x0);
 863
 864                 /* row */
 865                 device->controller->address(device, page & 0xff);
 866                 device->controller->address(device, (page >> 8) & 0xff);
 867
 868                 /* 4th cycle only on devices with more than 32 MiB */
 869                 if (device->address_cycles >= 4)
 870                         device->controller->address(device, (page >> 16) & 0xff);
 871
 872                 /* 5th cycle only on devices with more than 8 GiB */
 873                 if (device->address_cycles >= 5)
 874                         device->controller->address(device, (page >> 24) & 0xff);
 875         }
 876         else
 877         {
 878                 /* large page device */
 879                 device->controller->command(device, NAND_CMD_READ0);
 880
 881                 /* column (0 when we start at the beginning of a page,
 882                  * or 2048 for the beginning of OOB area)
 883                  */
 884                 device->controller->address(device, 0x0);
 885                 if (data)
 886                         device->controller->address(device, 0x0);
 887                 else
 888                         device->controller->address(device, 0x8);
 889
 890                 /* row */
 891                 device->controller->address(device, page & 0xff);
 892                 device->controller->address(device, (page >> 8) & 0xff);
 893
 894                 /* 5th cycle only on devices with more than 128 MiB */
 895                 if (device->address_cycles >= 5)
 896                         device->controller->address(device, (page >> 16) & 0xff);
 897
 898                 /* large page devices need a start command */
 899                 device->controller->command(device, NAND_CMD_READSTART);
 900         }
 901
 902         if (device->controller->nand_ready) {
 903                 if (!device->controller->nand_ready(device, 100))
 904                         return ERROR_NAND_OPERATION_TIMEOUT;
 905         } else {
 906                 alive_sleep(1);
 907         }
 908
 909         if (data)
 910         {
 911                 if (device->controller->read_block_data != NULL)
 912                         (device->controller->read_block_data)(device, data, data_size);
 913                 else
 914                 {
 915                         for (i = 0; i < data_size;)
 916                         {
 917                                 if (device->device->options & NAND_BUSWIDTH_16)
 918                                 {
 919                                         device->controller->read_data(device, data);
 920                                         data += 2;
 921                                         i += 2;
 922                                 }
 923                                 else
 924                                 {
 925                                         device->controller->read_data(device, data);
 926                                         data += 1;
 927                                         i += 1;
 928                                 }
 929                         }
 930                 }
 931         }
 932
 933         if (oob)
 934         {
 935                 if (device->controller->read_block_data != NULL)
 936                         (device->controller->read_block_data)(device, oob, oob_size);
 937                 else
 938                 {
 939                         for (i = 0; i < oob_size;)
 940                         {
 941                                 if (device->device->options & NAND_BUSWIDTH_16)
 942                                 {
 943                                         device->controller->read_data(device, oob);
 944                                         oob += 2;
 945                                         i += 2;
 946                                 }
 947                                 else
 948                                 {
 949                                         device->controller->read_data(device, oob);
 950                                         oob += 1;
 951                                         i += 1;
 952                                 }
 953                         }
 954                 }
 955         }
 956
 957         return ERROR_OK;
 958 }
 959
 960 int nand_write_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 961 {
 962         uint32_t i;
 963         int retval;
 964         uint8_t status;
 965
 966         if (!device->device)
 967                 return ERROR_NAND_DEVICE_NOT_PROBED;
 968
 969         device->controller->command(device, NAND_CMD_SEQIN);
 970
 971         if (device->page_size <= 512)
 972         {
 973                 /* column (always 0, we start at the beginning of a page/OOB area) */
 974                 device->controller->address(device, 0x0);
 975
 976                 /* row */
 977                 device->controller->address(device, page & 0xff);
 978                 device->controller->address(device, (page >> 8) & 0xff);
 979
 980                 /* 4th cycle only on devices with more than 32 MiB */
 981                 if (device->address_cycles >= 4)
 982                         device->controller->address(device, (page >> 16) & 0xff);
 983
 984                 /* 5th cycle only on devices with more than 8 GiB */
 985                 if (device->address_cycles >= 5)
 986                         device->controller->address(device, (page >> 24) & 0xff);
 987         }
 988         else
 989         {
 990                 /* column (0 when we start at the beginning of a page,
 991                  * or 2048 for the beginning of OOB area)
 992                  */
 993                 device->controller->address(device, 0x0);
 994                 if (data)
 995                         device->controller->address(device, 0x0);
 996                 else
 997                         device->controller->address(device, 0x8);
 998
 999                 /* row */
1000                 device->controller->address(device, page & 0xff);
1001                 device->controller->address(device, (page >> 8) & 0xff);
1002
1003                 /* 5th cycle only on devices with more than 128 MiB */
1004                 if (device->address_cycles >= 5)
1005                         device->controller->address(device, (page >> 16) & 0xff);
1006         }
1007
1008         if (data)
1009         {
1010                 if (device->controller->write_block_data != NULL)
1011                         (device->controller->write_block_data)(device, data, data_size);
1012                 else
1013                 {
1014                         for (i = 0; i < data_size;)
1015                         {
1016                                 if (device->device->options & NAND_BUSWIDTH_16)
1017                                 {
1018                                         uint16_t data_buf = le_to_h_u16(data);
1019                                         device->controller->write_data(device, data_buf);
1020                                         data += 2;
1021                                         i += 2;
1022                                 }
1023                                 else
1024                                 {
1025                                         device->controller->write_data(device, *data);
1026                                         data += 1;
1027                                         i += 1;
1028                                 }
1029                         }
1030                 }
1031         }
1032
1033         if (oob)
1034         {
1035                 if (device->controller->write_block_data != NULL)
1036                         (device->controller->write_block_data)(device, oob, oob_size);
1037                 else
1038                 {
1039                         for (i = 0; i < oob_size;)
1040                         {
1041                                 if (device->device->options & NAND_BUSWIDTH_16)
1042                                 {
1043                                         uint16_t oob_buf = le_to_h_u16(data);
1044                                         device->controller->write_data(device, oob_buf);
1045                                         oob += 2;
1046                                         i += 2;
1047                                 }
1048                                 else
1049                                 {
1050                                         device->controller->write_data(device, *oob);
1051                                         oob += 1;
1052                                         i += 1;
1053                                 }
1054                         }
1055                 }
1056         }
1057
1058         device->controller->command(device, NAND_CMD_PAGEPROG);
1059
1060         retval = device->controller->nand_ready ?
1061                         device->controller->nand_ready(device, 100) :
1062                         nand_poll_ready(device, 100);
1063         if (!retval)
1064                 return ERROR_NAND_OPERATION_TIMEOUT;
1065
1066         if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1067         {
1068                 LOG_ERROR("couldn't read status");
1069                 return ERROR_NAND_OPERATION_FAILED;
1070         }
1071
1072         if (status & NAND_STATUS_FAIL)
1073         {
1074                 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1075                 return ERROR_NAND_OPERATION_FAILED;
1076         }
1077
1078         return ERROR_OK;
1079 }
1080
1081 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1082 {
1083         nand_device_t *p;
1084         int i;
1085
1086         if (!nand_devices)
1087         {
1088                 command_print(cmd_ctx, "no NAND flash devices configured");
1089                 return ERROR_OK;
1090         }
1091
1092         for (p = nand_devices, i = 0; p; p = p->next, i++)
1093         {
1094                 if (p->device)
1095                         command_print(cmd_ctx, "#%i: %s (%s) "
1096                                 "pagesize: %i, buswidth: %i,\n\t"
1097                                 "blocksize: %i, blocks: %i",
1098                                 i, p->device->name, p->manufacturer->name,
1099                                 p->page_size, p->bus_width,
1100                                 p->erase_size, p->num_blocks);
1101                 else
1102                         command_print(cmd_ctx, "#%i: not probed", i);
1103         }
1104
1105         return ERROR_OK;
1106 }
1107
1108 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1109 {
1110         int i = 0;
1111         int j = 0;
1112         int first = -1;
1113         int last = -1;
1114
1115         nand_device_t *p;
1116         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1117         if (ERROR_OK != retval)
1118                 return retval;
1119
1120         switch (argc) {
1121         default:
1122                 return ERROR_COMMAND_SYNTAX_ERROR;
1123         case 1:
1124                 first = 0;
1125                 last = INT32_MAX;
1126                 break;
1127         case 2:
1128                 COMMAND_PARSE_NUMBER(int, args[1], i);
1129                 first = last = i;
1130                 i = 0;
1131                 break;
1132         case 3:
1133                 COMMAND_PARSE_NUMBER(int, args[1], first);
1134                 COMMAND_PARSE_NUMBER(int, args[2], last);
1135                 break;
1136         }
1137
1138         if (p)
1139         {
1140                 if (p->device)
1141                 {
1142                         if (first >= p->num_blocks)
1143                                 first = p->num_blocks - 1;
1144
1145                         if (last >= p->num_blocks)
1146                                 last = p->num_blocks - 1;
1147
1148                         command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1149                                 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1150
1151                         for (j = first; j <= last; j++)
1152                         {
1153                                 char *erase_state, *bad_state;
1154
1155                                 if (p->blocks[j].is_erased == 0)
1156                                         erase_state = "not erased";
1157                                 else if (p->blocks[j].is_erased == 1)
1158                                         erase_state = "erased";
1159                                 else
1160                                         erase_state = "erase state unknown";
1161
1162                                 if (p->blocks[j].is_bad == 0)
1163                                         bad_state = "";
1164                                 else if (p->blocks[j].is_bad == 1)
1165                                         bad_state = " (marked bad)";
1166                                 else
1167                                         bad_state = " (block condition unknown)";
1168
1169                                 command_print(cmd_ctx,
1170                                               "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1171                                               j,
1172                                               p->blocks[j].offset,
1173                                               p->blocks[j].size / 1024,
1174                                               erase_state,
1175                                               bad_state);
1176                         }
1177                 }
1178                 else
1179                 {
1180                         command_print(cmd_ctx, "#%s: not probed", args[0]);
1181                 }
1182         }
1183
1184         return ERROR_OK;
1185 }
1186
1187 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1188 {
1189         if (argc != 1)
1190         {
1191                 return ERROR_COMMAND_SYNTAX_ERROR;
1192         }
1193
1194         nand_device_t *p;
1195         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1196         if (ERROR_OK != retval)
1197                 return retval;
1198
1199         if (p)
1200         {
1201                 if ((retval = nand_probe(p)) == ERROR_OK)
1202                 {
1203                         command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1204                 }
1205                 else if (retval == ERROR_NAND_OPERATION_FAILED)
1206                 {
1207                         command_print(cmd_ctx, "probing failed for NAND flash device");
1208                 }
1209                 else
1210                 {
1211                         command_print(cmd_ctx, "unknown error when probing NAND flash device");
1212                 }
1213         }
1214
1215         return ERROR_OK;
1216 }
1217
1218 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1219 {
1220         if (argc != 1 && argc != 3)
1221         {
1222                 return ERROR_COMMAND_SYNTAX_ERROR;
1223
1224         }
1225
1226         nand_device_t *p;
1227         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1228         if (ERROR_OK != retval)
1229                 return retval;
1230
1231         if (p)
1232         {
1233                 unsigned long offset;
1234                 unsigned long length;
1235
1236                 /* erase specified part of the chip; or else everything */
1237                 if (argc == 3) {
1238                         unsigned long size = p->erase_size * p->num_blocks;
1239
1240                         COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1241                         if ((offset % p->erase_size) != 0 || offset >= size)
1242                                 return ERROR_INVALID_ARGUMENTS;
1243
1244                         COMMAND_PARSE_NUMBER(ulong, args[2], length);
1245                         if ((length == 0) || (length % p->erase_size) != 0
1246                                         || (length + offset) > size)
1247                                 return ERROR_INVALID_ARGUMENTS;
1248
1249                         offset /= p->erase_size;
1250                         length /= p->erase_size;
1251                 } else {
1252                         offset = 0;
1253                         length = p->num_blocks;
1254                 }
1255
1256                 retval = nand_erase(p, offset, offset + length - 1);
1257                 if (retval == ERROR_OK)
1258                 {
1259                         command_print(cmd_ctx, "erased blocks %lu to %lu "
1260                                         "on NAND flash device #%s '%s'",
1261                                         offset, offset + length,
1262                                         args[0], p->device->name);
1263                 }
1264                 else if (retval == ERROR_NAND_OPERATION_FAILED)
1265                 {
1266                         command_print(cmd_ctx, "erase failed");
1267                 }
1268                 else
1269                 {
1270                         command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1271                 }
1272         }
1273
1274         return ERROR_OK;
1275 }
1276
1277 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1278 {
1279         int first = -1;
1280         int last = -1;
1281
1282         if ((argc < 1) || (argc > 3) || (argc == 2))
1283         {
1284                 return ERROR_COMMAND_SYNTAX_ERROR;
1285
1286         }
1287
1288         nand_device_t *p;
1289         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1290         if (ERROR_OK != retval)
1291                 return retval;
1292
1293         if (argc == 3)
1294         {
1295                 unsigned long offset;
1296                 unsigned long length;
1297
1298                 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1299                 if (offset % p->erase_size)
1300                         return ERROR_INVALID_ARGUMENTS;
1301                 offset /= p->erase_size;
1302
1303                 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1304                 if (length % p->erase_size)
1305                         return ERROR_INVALID_ARGUMENTS;
1306
1307                 length -= 1;
1308                 length /= p->erase_size;
1309
1310                 first = offset;
1311                 last = offset + length;
1312         }
1313
1314         retval = nand_build_bbt(p, first, last);
1315         if (retval == ERROR_OK)
1316         {
1317                 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1318                                 "use \"nand info\" command to list blocks");
1319         }
1320         else if (retval == ERROR_NAND_OPERATION_FAILED)
1321         {
1322                 command_print(cmd_ctx, "error when checking for bad blocks on "
1323                                 "NAND flash device");
1324         }
1325         else
1326         {
1327                 command_print(cmd_ctx, "unknown error when checking for bad "
1328                                 "blocks on NAND flash device");
1329         }
1330
1331         return ERROR_OK;
1332 }
1333
1334 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1335 {
1336         uint32_t offset;
1337         uint32_t binary_size;
1338         uint32_t buf_cnt;
1339         enum oob_formats oob_format = NAND_OOB_NONE;
1340
1341         fileio_t fileio;
1342
1343         duration_t duration;
1344         char *duration_text;
1345
1346         if (argc < 3)
1347         {
1348                 return ERROR_COMMAND_SYNTAX_ERROR;
1349         }
1350
1351         nand_device_t *p;
1352         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1353         if (ERROR_OK != retval)
1354                 return retval;
1355
1356         if (p)
1357         {
1358                 uint8_t *page = NULL;
1359                 uint32_t page_size = 0;
1360                 uint8_t *oob = NULL;
1361                 uint32_t oob_size = 0;
1362                 const int *eccpos = NULL;
1363
1364                 COMMAND_PARSE_NUMBER(u32, args[2], offset);
1365
1366                 if (argc > 3)
1367                 {
1368                         int i;
1369                         for (i = 3; i < argc; i++)
1370                         {
1371                                 if (!strcmp(args[i], "oob_raw"))
1372                                         oob_format |= NAND_OOB_RAW;
1373                                 else if (!strcmp(args[i], "oob_only"))
1374                                         oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1375                                 else if (!strcmp(args[i], "oob_softecc"))
1376                                         oob_format |= NAND_OOB_SW_ECC;
1377                                 else if (!strcmp(args[i], "oob_softecc_kw"))
1378                                         oob_format |= NAND_OOB_SW_ECC_KW;
1379                                 else
1380                                 {
1381                                         command_print(cmd_ctx, "unknown option: %s", args[i]);
1382                                         return ERROR_COMMAND_SYNTAX_ERROR;
1383                                 }
1384                         }
1385                 }
1386
1387                 duration_start_measure(&duration);
1388
1389                 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1390                 {
1391                         return ERROR_OK;
1392                 }
1393
1394                 buf_cnt = binary_size = fileio.size;
1395
1396                 if (!(oob_format & NAND_OOB_ONLY))
1397                 {
1398                         page_size = p->page_size;
1399                         page = malloc(p->page_size);
1400                 }
1401
1402                 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1403                 {
1404                         if (p->page_size == 512) {
1405                                 oob_size = 16;
1406                                 eccpos = nand_oob_16.eccpos;
1407                         } else if (p->page_size == 2048) {
1408                                 oob_size = 64;
1409                                 eccpos = nand_oob_64.eccpos;
1410                         }
1411                         oob = malloc(oob_size);
1412                 }
1413
1414                 if (offset % p->page_size)
1415                 {
1416                         command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1417                         fileio_close(&fileio);
1418                         free(oob);
1419                         free(page);
1420                         return ERROR_OK;
1421                 }
1422
1423                 while (buf_cnt > 0)
1424                 {
1425                         uint32_t size_read;
1426
1427                         if (NULL != page)
1428                         {
1429                                 fileio_read(&fileio, page_size, page, &size_read);
1430                                 buf_cnt -= size_read;
1431                                 if (size_read < page_size)
1432                                 {
1433                                         memset(page + size_read, 0xff, page_size - size_read);
1434                                 }
1435                         }
1436
1437                         if (oob_format & NAND_OOB_SW_ECC)
1438                         {
1439                                 uint32_t i, j;
1440                                 uint8_t ecc[3];
1441                                 memset(oob, 0xff, oob_size);
1442                                 for (i = 0, j = 0; i < page_size; i += 256) {
1443                                         nand_calculate_ecc(p, page + i, ecc);
1444                                         oob[eccpos[j++]] = ecc[0];
1445                                         oob[eccpos[j++]] = ecc[1];
1446                                         oob[eccpos[j++]] = ecc[2];
1447                                 }
1448                         } else if (oob_format & NAND_OOB_SW_ECC_KW)
1449                         {
1450                                 /*
1451                                  * In this case eccpos is not used as
1452                                  * the ECC data is always stored contigously
1453                                  * at the end of the OOB area.  It consists
1454                                  * of 10 bytes per 512-byte data block.
1455                                  */
1456                                 uint32_t i;
1457                                 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1458                                 memset(oob, 0xff, oob_size);
1459                                 for (i = 0; i < page_size; i += 512) {
1460                                         nand_calculate_ecc_kw(p, page + i, ecc);
1461                                         ecc += 10;
1462                                 }
1463                         }
1464                         else if (NULL != oob)
1465                         {
1466                                 fileio_read(&fileio, oob_size, oob, &size_read);
1467                                 buf_cnt -= size_read;
1468                                 if (size_read < oob_size)
1469                                 {
1470                                         memset(oob + size_read, 0xff, oob_size - size_read);
1471                                 }
1472                         }
1473
1474                         if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1475                         {
1476                                 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1477                                         args[1], args[0], offset);
1478
1479                                 fileio_close(&fileio);
1480                                 free(oob);
1481                                 free(page);
1482
1483                                 return ERROR_OK;
1484                         }
1485                         offset += page_size;
1486                 }
1487
1488                 fileio_close(&fileio);
1489                 free(oob);
1490                 free(page);
1491                 oob = NULL;
1492                 page = NULL;
1493                 duration_stop_measure(&duration, &duration_text);
1494                 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8" PRIx32 " in %s",
1495                         args[1], args[0], offset, duration_text);
1496                 free(duration_text);
1497                 duration_text = NULL;
1498         }
1499
1500         return ERROR_OK;
1501 }
1502
1503 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1504 {
1505         if (argc < 4)
1506         {
1507                 return ERROR_COMMAND_SYNTAX_ERROR;
1508         }
1509
1510         nand_device_t *p;
1511         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1512         if (ERROR_OK != retval)
1513                 return retval;
1514
1515         if (p)
1516         {
1517                 if (p->device)
1518                 {
1519                         fileio_t fileio;
1520                         duration_t duration;
1521                         char *duration_text;
1522                         int retval;
1523
1524                         uint8_t *page = NULL;
1525                         uint32_t page_size = 0;
1526                         uint8_t *oob = NULL;
1527                         uint32_t oob_size = 0;
1528                         uint32_t address;
1529                         COMMAND_PARSE_NUMBER(u32, args[2], address);
1530                         uint32_t size;
1531                         COMMAND_PARSE_NUMBER(u32, args[3], size);
1532                         uint32_t bytes_done = 0;
1533                         enum oob_formats oob_format = NAND_OOB_NONE;
1534
1535                         if (argc > 4)
1536                         {
1537                                 int i;
1538                                 for (i = 4; i < argc; i++)
1539                                 {
1540                                         if (!strcmp(args[i], "oob_raw"))
1541                                                 oob_format |= NAND_OOB_RAW;
1542                                         else if (!strcmp(args[i], "oob_only"))
1543                                                 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1544                                         else
1545                                                 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1546                                 }
1547                         }
1548
1549                         if ((address % p->page_size) || (size % p->page_size))
1550                         {
1551                                 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1552                                 return ERROR_OK;
1553                         }
1554
1555                         if (!(oob_format & NAND_OOB_ONLY))
1556                         {
1557                                 page_size = p->page_size;
1558                                 page = malloc(p->page_size);
1559                         }
1560
1561                         if (oob_format & NAND_OOB_RAW)
1562                         {
1563                                 if (p->page_size == 512)
1564                                         oob_size = 16;
1565                                 else if (p->page_size == 2048)
1566                                         oob_size = 64;
1567                                 oob = malloc(oob_size);
1568                         }
1569
1570                         if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1571                         {
1572                                 return ERROR_OK;
1573                         }
1574
1575                         duration_start_measure(&duration);
1576
1577                         while (size > 0)
1578                         {
1579                                 uint32_t size_written;
1580                                 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1581                                 {
1582                                         command_print(cmd_ctx, "reading NAND flash page failed");
1583                                         free(page);
1584                                         free(oob);
1585                                         fileio_close(&fileio);
1586                                         return ERROR_OK;
1587                                 }
1588
1589                                 if (NULL != page)
1590                                 {
1591                                         fileio_write(&fileio, page_size, page, &size_written);
1592                                         bytes_done += page_size;
1593                                 }
1594
1595                                 if (NULL != oob)
1596                                 {
1597                                         fileio_write(&fileio, oob_size, oob, &size_written);
1598                                         bytes_done += oob_size;
1599                                 }
1600
1601                                 size -= p->page_size;
1602                                 address += p->page_size;
1603                         }
1604
1605                         free(page);
1606                         page = NULL;
1607                         free(oob);
1608                         oob = NULL;
1609                         fileio_close(&fileio);
1610
1611                         duration_stop_measure(&duration, &duration_text);
1612                         command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1613                         free(duration_text);
1614                         duration_text = NULL;
1615                 }
1616                 else
1617                 {
1618                         command_print(cmd_ctx, "#%s: not probed", args[0]);
1619                 }
1620         }
1621
1622         return ERROR_OK;
1623 }
1624
1625 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1626 {
1627         if ((argc < 1) || (argc > 2))
1628         {
1629                 return ERROR_COMMAND_SYNTAX_ERROR;
1630         }
1631
1632         nand_device_t *p;
1633         int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1634         if (ERROR_OK != retval)
1635                 return retval;
1636
1637         if (p)
1638         {
1639                 if (p->device)
1640                 {
1641                         if (argc == 2)
1642                         {
1643                                 if (strcmp("enable", args[1]) == 0)
1644                                 {
1645                                         p->use_raw = 1;
1646                                 }
1647                                 else if (strcmp("disable", args[1]) == 0)
1648                                 {
1649                                         p->use_raw = 0;
1650                                 }
1651                                 else
1652                                 {
1653                                         return ERROR_COMMAND_SYNTAX_ERROR;
1654                                 }
1655                         }
1656
1657                         command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1658                 }
1659                 else
1660                 {
1661                         command_print(cmd_ctx, "#%s: not probed", args[0]);
1662                 }
1663         }
1664
1665         return ERROR_OK;
1666 }