1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
31 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
32 //static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34 static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36 /* NAND flash controller
38 extern struct nand_flash_controller davinci_nand_controller;
39 extern struct nand_flash_controller lpc3180_nand_controller;
40 extern struct nand_flash_controller orion_nand_controller;
41 extern struct nand_flash_controller s3c2410_nand_controller;
42 extern struct nand_flash_controller s3c2412_nand_controller;
43 extern struct nand_flash_controller s3c2440_nand_controller;
44 extern struct nand_flash_controller s3c2443_nand_controller;
45 extern struct nand_flash_controller imx31_nand_flash_controller;
47 /* extern struct nand_flash_controller boundary_scan_nand_controller; */
49 static struct nand_flash_controller *nand_flash_controllers[] =
51 &davinci_nand_controller,
52 &lpc3180_nand_controller,
53 &orion_nand_controller,
54 &s3c2410_nand_controller,
55 &s3c2412_nand_controller,
56 &s3c2440_nand_controller,
57 &s3c2443_nand_controller,
58 &imx31_nand_flash_controller,
59 /* &boundary_scan_nand_controller, */
63 /* configured NAND devices and NAND Flash command handler */
64 static struct nand_device *nand_devices = NULL;
65 static struct command *nand_cmd;
69 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
72 * Pagesize; 0, 256, 512
73 * 0 get this information from the extended chip ID
74 * 256 256 Byte page size
75 * 512 512 Byte page size
77 static struct nand_info nand_flash_ids[] =
79 /* start "museum" IDs */
80 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
81 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
82 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
83 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
84 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
85 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
86 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
87 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
88 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
89 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
91 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
92 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
93 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
94 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
95 /* end "museum" IDs */
97 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
98 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
99 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
100 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
102 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
103 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
104 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
105 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
107 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
108 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
109 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
113 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
114 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
115 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
122 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
123 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
124 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
125 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
127 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
128 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
129 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
130 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
132 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
133 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
134 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
135 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
137 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
138 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
139 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
140 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
142 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
143 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
144 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
145 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
147 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
148 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
149 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
150 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
152 {NULL, 0, 0, 0, 0, 0 }
155 /* Manufacturer ID list
157 static struct nand_manufacturer nand_manuf_ids[] =
160 {NAND_MFR_TOSHIBA, "Toshiba"},
161 {NAND_MFR_SAMSUNG, "Samsung"},
162 {NAND_MFR_FUJITSU, "Fujitsu"},
163 {NAND_MFR_NATIONAL, "National"},
164 {NAND_MFR_RENESAS, "Renesas"},
165 {NAND_MFR_STMICRO, "ST Micro"},
166 {NAND_MFR_HYNIX, "Hynix"},
167 {NAND_MFR_MICRON, "Micron"},
172 * Define default oob placement schemes for large and small page devices
176 static struct nand_ecclayout nand_oob_8 = {
187 static struct nand_ecclayout nand_oob_16 = {
189 .eccpos = {0, 1, 2, 3, 6, 7},
195 static struct nand_ecclayout nand_oob_64 = {
198 40, 41, 42, 43, 44, 45, 46, 47,
199 48, 49, 50, 51, 52, 53, 54, 55,
200 56, 57, 58, 59, 60, 61, 62, 63},
206 /* nand device <nand_controller> [controller options]
208 COMMAND_HANDLER(handle_nand_device_command)
215 LOG_WARNING("incomplete flash device nand configuration");
216 return ERROR_FLASH_BANK_INVALID;
219 for (i = 0; nand_flash_controllers[i]; i++)
221 struct nand_device *p, *c;
223 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
225 /* register flash specific commands */
226 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
228 LOG_ERROR("couldn't register '%s' commands", args[0]);
232 c = malloc(sizeof(struct nand_device));
234 c->controller = nand_flash_controllers[i];
235 c->controller_priv = NULL;
236 c->manufacturer = NULL;
239 c->address_cycles = 0;
244 retval = CALL_COMMAND_HANDLER(nand_flash_controllers[i]->nand_device_command, c);
245 if (ERROR_OK != retval)
247 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
252 /* put NAND device in linked list */
255 /* find last flash device */
256 for (p = nand_devices; p && p->next; p = p->next);
269 /* no valid NAND controller was found (i.e. the configuration option,
270 * didn't match one of the compiled-in controllers)
272 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
273 LOG_ERROR("compiled-in NAND flash controllers:");
274 for (i = 0; nand_flash_controllers[i]; i++)
276 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
282 int nand_register_commands(struct command_context *cmd_ctx)
284 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
286 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
291 struct nand_device *get_nand_device_by_num(int num)
293 struct nand_device *p;
296 for (p = nand_devices; p; p = p->next)
307 int nand_command_get_device_by_num(struct command_context *cmd_ctx,
308 const char *str, struct nand_device **nand)
311 COMMAND_PARSE_NUMBER(uint, str, num);
312 *nand = get_nand_device_by_num(num);
314 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", str);
315 return ERROR_INVALID_ARGUMENTS;
320 static int nand_build_bbt(struct nand_device *nand, int first, int last)
326 if ((first < 0) || (first >= nand->num_blocks))
329 if ((last >= nand->num_blocks) || (last == -1))
330 last = nand->num_blocks - 1;
332 for (i = first; i < last; i++)
334 nand_read_page(nand, page, NULL, 0, oob, 6);
336 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
337 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
338 ((nand->page_size == 2048) && (oob[0] != 0xff))))
340 LOG_WARNING("bad block: %i", i);
341 nand->blocks[i].is_bad = 1;
345 nand->blocks[i].is_bad = 0;
348 page += (nand->erase_size / nand->page_size);
354 int nand_read_status(struct nand_device *nand, uint8_t *status)
357 return ERROR_NAND_DEVICE_NOT_PROBED;
359 /* Send read status command */
360 nand->controller->command(nand, NAND_CMD_STATUS);
365 if (nand->device->options & NAND_BUSWIDTH_16)
368 nand->controller->read_data(nand, &data);
369 *status = data & 0xff;
373 nand->controller->read_data(nand, status);
379 static int nand_poll_ready(struct nand_device *nand, int timeout)
383 nand->controller->command(nand, NAND_CMD_STATUS);
385 if (nand->device->options & NAND_BUSWIDTH_16) {
387 nand->controller->read_data(nand, &data);
388 status = data & 0xff;
390 nand->controller->read_data(nand, &status);
392 if (status & NAND_STATUS_READY)
397 return (status & NAND_STATUS_READY) != 0;
400 int nand_probe(struct nand_device *nand)
402 uint8_t manufacturer_id, device_id;
407 /* clear device data */
409 nand->manufacturer = NULL;
411 /* clear device parameters */
413 nand->address_cycles = 0;
415 nand->erase_size = 0;
417 /* initialize controller (device parameters are zero, use controller default) */
418 if ((retval = nand->controller->init(nand) != ERROR_OK))
422 case ERROR_NAND_OPERATION_FAILED:
423 LOG_DEBUG("controller initialization failed");
424 return ERROR_NAND_OPERATION_FAILED;
425 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
426 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
427 return ERROR_NAND_OPERATION_FAILED;
429 LOG_ERROR("BUG: unknown controller initialization failure");
430 return ERROR_NAND_OPERATION_FAILED;
434 nand->controller->command(nand, NAND_CMD_RESET);
435 nand->controller->reset(nand);
437 nand->controller->command(nand, NAND_CMD_READID);
438 nand->controller->address(nand, 0x0);
440 if (nand->bus_width == 8)
442 nand->controller->read_data(nand, &manufacturer_id);
443 nand->controller->read_data(nand, &device_id);
448 nand->controller->read_data(nand, &data_buf);
449 manufacturer_id = data_buf & 0xff;
450 nand->controller->read_data(nand, &data_buf);
451 device_id = data_buf & 0xff;
454 for (i = 0; nand_flash_ids[i].name; i++)
456 if (nand_flash_ids[i].id == device_id)
458 nand->device = &nand_flash_ids[i];
463 for (i = 0; nand_manuf_ids[i].name; i++)
465 if (nand_manuf_ids[i].id == manufacturer_id)
467 nand->manufacturer = &nand_manuf_ids[i];
472 if (!nand->manufacturer)
474 nand->manufacturer = &nand_manuf_ids[0];
475 nand->manufacturer->id = manufacturer_id;
480 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
481 manufacturer_id, device_id);
482 return ERROR_NAND_OPERATION_FAILED;
485 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
487 /* initialize device parameters */
490 if (nand->device->options & NAND_BUSWIDTH_16)
491 nand->bus_width = 16;
495 /* Do we need extended device probe information? */
496 if (nand->device->page_size == 0 ||
497 nand->device->erase_size == 0)
499 if (nand->bus_width == 8)
501 nand->controller->read_data(nand, id_buff + 3);
502 nand->controller->read_data(nand, id_buff + 4);
503 nand->controller->read_data(nand, id_buff + 5);
509 nand->controller->read_data(nand, &data_buf);
510 id_buff[3] = data_buf;
512 nand->controller->read_data(nand, &data_buf);
513 id_buff[4] = data_buf;
515 nand->controller->read_data(nand, &data_buf);
516 id_buff[5] = data_buf >> 8;
521 if (nand->device->page_size == 0)
523 nand->page_size = 1 << (10 + (id_buff[4] & 3));
525 else if (nand->device->page_size == 256)
527 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
528 return ERROR_NAND_OPERATION_FAILED;
532 nand->page_size = nand->device->page_size;
535 /* number of address cycles */
536 if (nand->page_size <= 512)
538 /* small page devices */
539 if (nand->device->chip_size <= 32)
540 nand->address_cycles = 3;
541 else if (nand->device->chip_size <= 8*1024)
542 nand->address_cycles = 4;
545 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
546 nand->address_cycles = 5;
551 /* large page devices */
552 if (nand->device->chip_size <= 128)
553 nand->address_cycles = 4;
554 else if (nand->device->chip_size <= 32*1024)
555 nand->address_cycles = 5;
558 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
559 nand->address_cycles = 6;
564 if (nand->device->erase_size == 0)
566 switch ((id_buff[4] >> 4) & 3) {
568 nand->erase_size = 64 << 10;
571 nand->erase_size = 128 << 10;
574 nand->erase_size = 256 << 10;
577 nand->erase_size =512 << 10;
583 nand->erase_size = nand->device->erase_size;
586 /* initialize controller, but leave parameters at the controllers default */
587 if ((retval = nand->controller->init(nand) != ERROR_OK))
591 case ERROR_NAND_OPERATION_FAILED:
592 LOG_DEBUG("controller initialization failed");
593 return ERROR_NAND_OPERATION_FAILED;
594 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
595 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
596 nand->bus_width, nand->address_cycles, nand->page_size);
597 return ERROR_NAND_OPERATION_FAILED;
599 LOG_ERROR("BUG: unknown controller initialization failure");
600 return ERROR_NAND_OPERATION_FAILED;
604 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
605 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
607 for (i = 0; i < nand->num_blocks; i++)
609 nand->blocks[i].size = nand->erase_size;
610 nand->blocks[i].offset = i * nand->erase_size;
611 nand->blocks[i].is_erased = -1;
612 nand->blocks[i].is_bad = -1;
618 static int nand_erase(struct nand_device *nand, int first_block, int last_block)
626 return ERROR_NAND_DEVICE_NOT_PROBED;
628 if ((first_block < 0) || (last_block > nand->num_blocks))
629 return ERROR_INVALID_ARGUMENTS;
631 /* make sure we know if a block is bad before erasing it */
632 for (i = first_block; i <= last_block; i++)
634 if (nand->blocks[i].is_bad == -1)
636 nand_build_bbt(nand, i, last_block);
641 for (i = first_block; i <= last_block; i++)
643 /* Send erase setup command */
644 nand->controller->command(nand, NAND_CMD_ERASE1);
646 page = i * (nand->erase_size / nand->page_size);
648 /* Send page address */
649 if (nand->page_size <= 512)
652 nand->controller->address(nand, page & 0xff);
653 nand->controller->address(nand, (page >> 8) & 0xff);
655 /* 3rd cycle only on devices with more than 32 MiB */
656 if (nand->address_cycles >= 4)
657 nand->controller->address(nand, (page >> 16) & 0xff);
659 /* 4th cycle only on devices with more than 8 GiB */
660 if (nand->address_cycles >= 5)
661 nand->controller->address(nand, (page >> 24) & 0xff);
666 nand->controller->address(nand, page & 0xff);
667 nand->controller->address(nand, (page >> 8) & 0xff);
669 /* 3rd cycle only on devices with more than 128 MiB */
670 if (nand->address_cycles >= 5)
671 nand->controller->address(nand, (page >> 16) & 0xff);
674 /* Send erase confirm command */
675 nand->controller->command(nand, NAND_CMD_ERASE2);
677 retval = nand->controller->nand_ready ?
678 nand->controller->nand_ready(nand, 1000) :
679 nand_poll_ready(nand, 1000);
681 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
682 return ERROR_NAND_OPERATION_TIMEOUT;
685 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
687 LOG_ERROR("couldn't read status");
688 return ERROR_NAND_OPERATION_FAILED;
693 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
694 (nand->blocks[i].is_bad == 1)
697 /* continue; other blocks might still be erasable */
700 nand->blocks[i].is_erased = 1;
707 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
712 return ERROR_NAND_DEVICE_NOT_PROBED;
714 if (address % nand->page_size)
716 LOG_ERROR("reads need to be page aligned");
717 return ERROR_NAND_OPERATION_FAILED;
720 page = malloc(nand->page_size);
722 while (data_size > 0)
724 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
725 uint32_t page_address;
728 page_address = address / nand->page_size;
730 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
732 memcpy(data, page, thisrun_size);
734 address += thisrun_size;
735 data += thisrun_size;
736 data_size -= thisrun_size;
744 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
749 return ERROR_NAND_DEVICE_NOT_PROBED;
751 if (address % nand->page_size)
753 LOG_ERROR("writes need to be page aligned");
754 return ERROR_NAND_OPERATION_FAILED;
757 page = malloc(nand->page_size);
759 while (data_size > 0)
761 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
762 uint32_t page_address;
764 memset(page, 0xff, nand->page_size);
765 memcpy(page, data, thisrun_size);
767 page_address = address / nand->page_size;
769 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
771 address += thisrun_size;
772 data += thisrun_size;
773 data_size -= thisrun_size;
782 int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
787 return ERROR_NAND_DEVICE_NOT_PROBED;
789 block = page / (nand->erase_size / nand->page_size);
790 if (nand->blocks[block].is_erased == 1)
791 nand->blocks[block].is_erased = 0;
793 if (nand->use_raw || nand->controller->write_page == NULL)
794 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
796 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
799 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
802 return ERROR_NAND_DEVICE_NOT_PROBED;
804 if (nand->use_raw || nand->controller->read_page == NULL)
805 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
807 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
810 int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
815 return ERROR_NAND_DEVICE_NOT_PROBED;
817 if (nand->page_size <= 512)
819 /* small page device */
821 nand->controller->command(nand, NAND_CMD_READ0);
823 nand->controller->command(nand, NAND_CMD_READOOB);
825 /* column (always 0, we start at the beginning of a page/OOB area) */
826 nand->controller->address(nand, 0x0);
829 nand->controller->address(nand, page & 0xff);
830 nand->controller->address(nand, (page >> 8) & 0xff);
832 /* 4th cycle only on devices with more than 32 MiB */
833 if (nand->address_cycles >= 4)
834 nand->controller->address(nand, (page >> 16) & 0xff);
836 /* 5th cycle only on devices with more than 8 GiB */
837 if (nand->address_cycles >= 5)
838 nand->controller->address(nand, (page >> 24) & 0xff);
842 /* large page device */
843 nand->controller->command(nand, NAND_CMD_READ0);
845 /* column (0 when we start at the beginning of a page,
846 * or 2048 for the beginning of OOB area)
848 nand->controller->address(nand, 0x0);
850 nand->controller->address(nand, 0x0);
852 nand->controller->address(nand, 0x8);
855 nand->controller->address(nand, page & 0xff);
856 nand->controller->address(nand, (page >> 8) & 0xff);
858 /* 5th cycle only on devices with more than 128 MiB */
859 if (nand->address_cycles >= 5)
860 nand->controller->address(nand, (page >> 16) & 0xff);
862 /* large page devices need a start command */
863 nand->controller->command(nand, NAND_CMD_READSTART);
866 if (nand->controller->nand_ready) {
867 if (!nand->controller->nand_ready(nand, 100))
868 return ERROR_NAND_OPERATION_TIMEOUT;
875 if (nand->controller->read_block_data != NULL)
876 (nand->controller->read_block_data)(nand, data, data_size);
879 for (i = 0; i < data_size;)
881 if (nand->device->options & NAND_BUSWIDTH_16)
883 nand->controller->read_data(nand, data);
889 nand->controller->read_data(nand, data);
899 if (nand->controller->read_block_data != NULL)
900 (nand->controller->read_block_data)(nand, oob, oob_size);
903 for (i = 0; i < oob_size;)
905 if (nand->device->options & NAND_BUSWIDTH_16)
907 nand->controller->read_data(nand, oob);
913 nand->controller->read_data(nand, oob);
924 int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
931 return ERROR_NAND_DEVICE_NOT_PROBED;
933 nand->controller->command(nand, NAND_CMD_SEQIN);
935 if (nand->page_size <= 512)
937 /* column (always 0, we start at the beginning of a page/OOB area) */
938 nand->controller->address(nand, 0x0);
941 nand->controller->address(nand, page & 0xff);
942 nand->controller->address(nand, (page >> 8) & 0xff);
944 /* 4th cycle only on devices with more than 32 MiB */
945 if (nand->address_cycles >= 4)
946 nand->controller->address(nand, (page >> 16) & 0xff);
948 /* 5th cycle only on devices with more than 8 GiB */
949 if (nand->address_cycles >= 5)
950 nand->controller->address(nand, (page >> 24) & 0xff);
954 /* column (0 when we start at the beginning of a page,
955 * or 2048 for the beginning of OOB area)
957 nand->controller->address(nand, 0x0);
959 nand->controller->address(nand, 0x0);
961 nand->controller->address(nand, 0x8);
964 nand->controller->address(nand, page & 0xff);
965 nand->controller->address(nand, (page >> 8) & 0xff);
967 /* 5th cycle only on devices with more than 128 MiB */
968 if (nand->address_cycles >= 5)
969 nand->controller->address(nand, (page >> 16) & 0xff);
974 if (nand->controller->write_block_data != NULL)
975 (nand->controller->write_block_data)(nand, data, data_size);
978 for (i = 0; i < data_size;)
980 if (nand->device->options & NAND_BUSWIDTH_16)
982 uint16_t data_buf = le_to_h_u16(data);
983 nand->controller->write_data(nand, data_buf);
989 nand->controller->write_data(nand, *data);
999 if (nand->controller->write_block_data != NULL)
1000 (nand->controller->write_block_data)(nand, oob, oob_size);
1003 for (i = 0; i < oob_size;)
1005 if (nand->device->options & NAND_BUSWIDTH_16)
1007 uint16_t oob_buf = le_to_h_u16(data);
1008 nand->controller->write_data(nand, oob_buf);
1014 nand->controller->write_data(nand, *oob);
1022 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1024 retval = nand->controller->nand_ready ?
1025 nand->controller->nand_ready(nand, 100) :
1026 nand_poll_ready(nand, 100);
1028 return ERROR_NAND_OPERATION_TIMEOUT;
1030 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1032 LOG_ERROR("couldn't read status");
1033 return ERROR_NAND_OPERATION_FAILED;
1036 if (status & NAND_STATUS_FAIL)
1038 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1039 return ERROR_NAND_OPERATION_FAILED;
1045 COMMAND_HANDLER(handle_nand_list_command)
1047 struct nand_device *p;
1052 command_print(cmd_ctx, "no NAND flash devices configured");
1056 for (p = nand_devices, i = 0; p; p = p->next, i++)
1059 command_print(cmd_ctx, "#%i: %s (%s) "
1060 "pagesize: %i, buswidth: %i,\n\t"
1061 "blocksize: %i, blocks: %i",
1062 i, p->device->name, p->manufacturer->name,
1063 p->page_size, p->bus_width,
1064 p->erase_size, p->num_blocks);
1066 command_print(cmd_ctx, "#%i: not probed", i);
1072 COMMAND_HANDLER(handle_nand_info_command)
1079 struct nand_device *p;
1080 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1081 if (ERROR_OK != retval)
1086 return ERROR_COMMAND_SYNTAX_ERROR;
1092 COMMAND_PARSE_NUMBER(int, args[1], i);
1097 COMMAND_PARSE_NUMBER(int, args[1], first);
1098 COMMAND_PARSE_NUMBER(int, args[2], last);
1102 if (NULL == p->device)
1104 command_print(cmd_ctx, "#%s: not probed", args[0]);
1108 if (first >= p->num_blocks)
1109 first = p->num_blocks - 1;
1111 if (last >= p->num_blocks)
1112 last = p->num_blocks - 1;
1114 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1115 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1117 for (j = first; j <= last; j++)
1119 char *erase_state, *bad_state;
1121 if (p->blocks[j].is_erased == 0)
1122 erase_state = "not erased";
1123 else if (p->blocks[j].is_erased == 1)
1124 erase_state = "erased";
1126 erase_state = "erase state unknown";
1128 if (p->blocks[j].is_bad == 0)
1130 else if (p->blocks[j].is_bad == 1)
1131 bad_state = " (marked bad)";
1133 bad_state = " (block condition unknown)";
1135 command_print(cmd_ctx,
1136 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1138 p->blocks[j].offset,
1139 p->blocks[j].size / 1024,
1147 COMMAND_HANDLER(handle_nand_probe_command)
1151 return ERROR_COMMAND_SYNTAX_ERROR;
1154 struct nand_device *p;
1155 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1156 if (ERROR_OK != retval)
1159 if ((retval = nand_probe(p)) == ERROR_OK)
1161 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1163 else if (retval == ERROR_NAND_OPERATION_FAILED)
1165 command_print(cmd_ctx, "probing failed for NAND flash device");
1169 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1175 COMMAND_HANDLER(handle_nand_erase_command)
1177 if (argc != 1 && argc != 3)
1179 return ERROR_COMMAND_SYNTAX_ERROR;
1183 struct nand_device *p;
1184 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1185 if (ERROR_OK != retval)
1188 unsigned long offset;
1189 unsigned long length;
1191 /* erase specified part of the chip; or else everything */
1193 unsigned long size = p->erase_size * p->num_blocks;
1195 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1196 if ((offset % p->erase_size) != 0 || offset >= size)
1197 return ERROR_INVALID_ARGUMENTS;
1199 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1200 if ((length == 0) || (length % p->erase_size) != 0
1201 || (length + offset) > size)
1202 return ERROR_INVALID_ARGUMENTS;
1204 offset /= p->erase_size;
1205 length /= p->erase_size;
1208 length = p->num_blocks;
1211 retval = nand_erase(p, offset, offset + length - 1);
1212 if (retval == ERROR_OK)
1214 command_print(cmd_ctx, "erased blocks %lu to %lu "
1215 "on NAND flash device #%s '%s'",
1216 offset, offset + length,
1217 args[0], p->device->name);
1219 else if (retval == ERROR_NAND_OPERATION_FAILED)
1221 command_print(cmd_ctx, "erase failed");
1225 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1231 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1236 if ((argc < 1) || (argc > 3) || (argc == 2))
1238 return ERROR_COMMAND_SYNTAX_ERROR;
1242 struct nand_device *p;
1243 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1244 if (ERROR_OK != retval)
1249 unsigned long offset;
1250 unsigned long length;
1252 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1253 if (offset % p->erase_size)
1254 return ERROR_INVALID_ARGUMENTS;
1255 offset /= p->erase_size;
1257 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1258 if (length % p->erase_size)
1259 return ERROR_INVALID_ARGUMENTS;
1262 length /= p->erase_size;
1265 last = offset + length;
1268 retval = nand_build_bbt(p, first, last);
1269 if (retval == ERROR_OK)
1271 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1272 "use \"nand info\" command to list blocks");
1274 else if (retval == ERROR_NAND_OPERATION_FAILED)
1276 command_print(cmd_ctx, "error when checking for bad blocks on "
1277 "NAND flash device");
1281 command_print(cmd_ctx, "unknown error when checking for bad "
1282 "blocks on NAND flash device");
1288 COMMAND_HANDLER(handle_nand_write_command)
1291 uint32_t binary_size;
1293 enum oob_formats oob_format = NAND_OOB_NONE;
1295 struct fileio fileio;
1300 return ERROR_COMMAND_SYNTAX_ERROR;
1303 struct nand_device *p;
1304 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1305 if (ERROR_OK != retval)
1308 uint8_t *page = NULL;
1309 uint32_t page_size = 0;
1310 uint8_t *oob = NULL;
1311 uint32_t oob_size = 0;
1312 const int *eccpos = NULL;
1314 COMMAND_PARSE_NUMBER(u32, args[2], offset);
1318 for (unsigned i = 3; i < argc; i++)
1320 if (!strcmp(args[i], "oob_raw"))
1321 oob_format |= NAND_OOB_RAW;
1322 else if (!strcmp(args[i], "oob_only"))
1323 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1324 else if (!strcmp(args[i], "oob_softecc"))
1325 oob_format |= NAND_OOB_SW_ECC;
1326 else if (!strcmp(args[i], "oob_softecc_kw"))
1327 oob_format |= NAND_OOB_SW_ECC_KW;
1330 command_print(cmd_ctx, "unknown option: %s", args[i]);
1331 return ERROR_COMMAND_SYNTAX_ERROR;
1336 struct duration bench;
1337 duration_start(&bench);
1339 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1344 buf_cnt = binary_size = fileio.size;
1346 if (!(oob_format & NAND_OOB_ONLY))
1348 page_size = p->page_size;
1349 page = malloc(p->page_size);
1352 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1354 if (p->page_size == 512) {
1356 eccpos = nand_oob_16.eccpos;
1357 } else if (p->page_size == 2048) {
1359 eccpos = nand_oob_64.eccpos;
1361 oob = malloc(oob_size);
1364 if (offset % p->page_size)
1366 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1367 fileio_close(&fileio);
1379 fileio_read(&fileio, page_size, page, &size_read);
1380 buf_cnt -= size_read;
1381 if (size_read < page_size)
1383 memset(page + size_read, 0xff, page_size - size_read);
1387 if (oob_format & NAND_OOB_SW_ECC)
1391 memset(oob, 0xff, oob_size);
1392 for (i = 0, j = 0; i < page_size; i += 256) {
1393 nand_calculate_ecc(p, page + i, ecc);
1394 oob[eccpos[j++]] = ecc[0];
1395 oob[eccpos[j++]] = ecc[1];
1396 oob[eccpos[j++]] = ecc[2];
1398 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1401 * In this case eccpos is not used as
1402 * the ECC data is always stored contigously
1403 * at the end of the OOB area. It consists
1404 * of 10 bytes per 512-byte data block.
1407 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1408 memset(oob, 0xff, oob_size);
1409 for (i = 0; i < page_size; i += 512) {
1410 nand_calculate_ecc_kw(p, page + i, ecc);
1414 else if (NULL != oob)
1416 fileio_read(&fileio, oob_size, oob, &size_read);
1417 buf_cnt -= size_read;
1418 if (size_read < oob_size)
1420 memset(oob + size_read, 0xff, oob_size - size_read);
1424 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1426 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1427 args[1], args[0], offset);
1429 fileio_close(&fileio);
1435 offset += page_size;
1438 fileio_close(&fileio);
1443 if (duration_measure(&bench) == ERROR_OK)
1445 command_print(cmd_ctx, "wrote file %s to NAND flash %s "
1446 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1447 args[1], args[0], offset, duration_elapsed(&bench),
1448 duration_kbps(&bench, fileio.size));
1454 COMMAND_HANDLER(handle_nand_dump_command)
1458 return ERROR_COMMAND_SYNTAX_ERROR;
1461 struct nand_device *p;
1462 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1463 if (ERROR_OK != retval)
1466 if (NULL == p->device)
1468 command_print(cmd_ctx, "#%s: not probed", args[0]);
1472 struct fileio fileio;
1474 uint8_t *page = NULL;
1475 uint32_t page_size = 0;
1476 uint8_t *oob = NULL;
1477 uint32_t oob_size = 0;
1479 COMMAND_PARSE_NUMBER(u32, args[2], address);
1481 COMMAND_PARSE_NUMBER(u32, args[3], size);
1482 uint32_t bytes_done = 0;
1483 enum oob_formats oob_format = NAND_OOB_NONE;
1487 for (unsigned i = 4; i < argc; i++)
1489 if (!strcmp(args[i], "oob_raw"))
1490 oob_format |= NAND_OOB_RAW;
1491 else if (!strcmp(args[i], "oob_only"))
1492 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1494 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1498 if ((address % p->page_size) || (size % p->page_size))
1500 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1504 if (!(oob_format & NAND_OOB_ONLY))
1506 page_size = p->page_size;
1507 page = malloc(p->page_size);
1510 if (oob_format & NAND_OOB_RAW)
1512 if (p->page_size == 512)
1514 else if (p->page_size == 2048)
1516 oob = malloc(oob_size);
1519 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1524 struct duration bench;
1525 duration_start(&bench);
1529 uint32_t size_written;
1530 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1532 command_print(cmd_ctx, "reading NAND flash page failed");
1535 fileio_close(&fileio);
1541 fileio_write(&fileio, page_size, page, &size_written);
1542 bytes_done += page_size;
1547 fileio_write(&fileio, oob_size, oob, &size_written);
1548 bytes_done += oob_size;
1551 size -= p->page_size;
1552 address += p->page_size;
1559 fileio_close(&fileio);
1561 if (duration_measure(&bench) == ERROR_OK)
1563 command_print(cmd_ctx, "dumped %lld byte in %fs (%0.3f kb/s)",
1564 fileio.size, duration_elapsed(&bench),
1565 duration_kbps(&bench, fileio.size));
1571 COMMAND_HANDLER(handle_nand_raw_access_command)
1573 if ((argc < 1) || (argc > 2))
1575 return ERROR_COMMAND_SYNTAX_ERROR;
1578 struct nand_device *p;
1579 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1580 if (ERROR_OK != retval)
1583 if (NULL == p->device)
1585 command_print(cmd_ctx, "#%s: not probed", args[0]);
1591 if (strcmp("enable", args[1]) == 0)
1593 else if (strcmp("disable", args[1]) == 0)
1596 return ERROR_COMMAND_SYNTAX_ERROR;
1599 const char *msg = p->use_raw ? "enabled" : "disabled";
1600 command_print(cmd_ctx, "raw access is %s", msg);
1605 int nand_init(struct command_context *cmd_ctx)
1610 register_command(cmd_ctx, nand_cmd, "list",
1611 handle_nand_list_command, COMMAND_EXEC,
1612 "list configured NAND flash devices");
1613 register_command(cmd_ctx, nand_cmd, "info",
1614 handle_nand_info_command, COMMAND_EXEC,
1615 "print info about NAND flash device <num>");
1616 register_command(cmd_ctx, nand_cmd, "probe",
1617 handle_nand_probe_command, COMMAND_EXEC,
1618 "identify NAND flash device <num>");
1620 register_command(cmd_ctx, nand_cmd, "check_bad_blocks",
1621 handle_nand_check_bad_blocks_command, COMMAND_EXEC,
1622 "check NAND flash device <num> for bad blocks [<offset> <length>]");
1623 register_command(cmd_ctx, nand_cmd, "erase",
1624 handle_nand_erase_command, COMMAND_EXEC,
1625 "erase blocks on NAND flash device <num> [<offset> <length>]");
1626 register_command(cmd_ctx, nand_cmd, "dump",
1627 handle_nand_dump_command, COMMAND_EXEC,
1628 "dump from NAND flash device <num> <filename> "
1629 "<offset> <length> [oob_raw | oob_only]");
1630 register_command(cmd_ctx, nand_cmd, "write",
1631 handle_nand_write_command, COMMAND_EXEC,
1632 "write to NAND flash device <num> <filename> <offset> "
1633 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
1635 register_command(cmd_ctx, nand_cmd, "raw_access",
1636 handle_nand_raw_access_command, COMMAND_EXEC,
1637 "raw access to NAND flash device <num> ['enable'|'disable']");