1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
31 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
32 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
33 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
34 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
42 //static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size);
44 static int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
46 /* NAND flash controller
48 extern nand_flash_controller_t davinci_nand_controller;
49 extern nand_flash_controller_t lpc3180_nand_controller;
50 extern nand_flash_controller_t orion_nand_controller;
51 extern nand_flash_controller_t s3c2410_nand_controller;
52 extern nand_flash_controller_t s3c2412_nand_controller;
53 extern nand_flash_controller_t s3c2440_nand_controller;
54 extern nand_flash_controller_t s3c2443_nand_controller;
55 extern nand_flash_controller_t imx31_nand_flash_controller;
57 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
59 static nand_flash_controller_t *nand_flash_controllers[] =
61 &davinci_nand_controller,
62 &lpc3180_nand_controller,
63 &orion_nand_controller,
64 &s3c2410_nand_controller,
65 &s3c2412_nand_controller,
66 &s3c2440_nand_controller,
67 &s3c2443_nand_controller,
68 &imx31_nand_flash_controller,
69 /* &boundary_scan_nand_controller, */
73 /* configured NAND devices and NAND Flash command handler */
74 static nand_device_t *nand_devices = NULL;
75 static command_t *nand_cmd;
79 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
82 * Pagesize; 0, 256, 512
83 * 0 get this information from the extended chip ID
84 * 256 256 Byte page size
85 * 512 512 Byte page size
87 static nand_info_t nand_flash_ids[] =
89 /* start "museum" IDs */
90 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
91 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
92 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
93 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
95 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
99 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
101 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
104 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 /* end "museum" IDs */
107 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
108 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
113 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
115 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
118 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
122 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
130 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
132 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
133 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
135 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
137 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
138 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
140 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
142 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
143 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
145 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
147 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
148 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
150 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
152 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
153 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
155 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
157 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
158 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
160 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
162 {NULL, 0, 0, 0, 0, 0 }
165 /* Manufacturer ID list
167 static nand_manufacturer_t nand_manuf_ids[] =
170 {NAND_MFR_TOSHIBA, "Toshiba"},
171 {NAND_MFR_SAMSUNG, "Samsung"},
172 {NAND_MFR_FUJITSU, "Fujitsu"},
173 {NAND_MFR_NATIONAL, "National"},
174 {NAND_MFR_RENESAS, "Renesas"},
175 {NAND_MFR_STMICRO, "ST Micro"},
176 {NAND_MFR_HYNIX, "Hynix"},
177 {NAND_MFR_MICRON, "Micron"},
182 * Define default oob placement schemes for large and small page devices
186 static nand_ecclayout_t nand_oob_8 = {
197 static nand_ecclayout_t nand_oob_16 = {
199 .eccpos = {0, 1, 2, 3, 6, 7},
205 static nand_ecclayout_t nand_oob_64 = {
208 40, 41, 42, 43, 44, 45, 46, 47,
209 48, 49, 50, 51, 52, 53, 54, 55,
210 56, 57, 58, 59, 60, 61, 62, 63},
216 /* nand device <nand_controller> [controller options]
218 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
225 LOG_WARNING("incomplete flash device nand configuration");
226 return ERROR_FLASH_BANK_INVALID;
229 for (i = 0; nand_flash_controllers[i]; i++)
231 nand_device_t *p, *c;
233 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
235 /* register flash specific commands */
236 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
238 LOG_ERROR("couldn't register '%s' commands", args[0]);
242 c = malloc(sizeof(nand_device_t));
244 c->controller = nand_flash_controllers[i];
245 c->controller_priv = NULL;
246 c->manufacturer = NULL;
249 c->address_cycles = 0;
254 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
256 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
261 /* put NAND device in linked list */
264 /* find last flash device */
265 for (p = nand_devices; p && p->next; p = p->next);
278 /* no valid NAND controller was found (i.e. the configuration option,
279 * didn't match one of the compiled-in controllers)
281 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
282 LOG_ERROR("compiled-in NAND flash controllers:");
283 for (i = 0; nand_flash_controllers[i]; i++)
285 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
291 int nand_register_commands(struct command_context_s *cmd_ctx)
293 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
295 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
300 int nand_init(struct command_context_s *cmd_ctx)
304 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
305 "list configured NAND flash devices");
306 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
307 "print info about NAND flash device <num>");
308 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
309 "identify NAND flash device <num>");
310 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
311 "check NAND flash device <num> for bad blocks [<offset> <length>]");
312 register_command(cmd_ctx, nand_cmd, "erase",
313 handle_nand_erase_command, COMMAND_EXEC,
314 "erase blocks on NAND flash device <num> [<offset> <length>]");
315 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
316 "dump from NAND flash device <num> <filename> "
317 "<offset> <length> [oob_raw | oob_only]");
318 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
319 "write to NAND flash device <num> <filename> <offset> [oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
320 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
321 "raw access to NAND flash device <num> ['enable'|'disable']");
327 nand_device_t *get_nand_device_by_num(int num)
332 for (p = nand_devices; p; p = p->next)
343 int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
344 char *str, nand_device_t **device)
347 COMMAND_PARSE_NUMBER(uint, str, num);
348 *device = get_nand_device_by_num(num);
350 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", str);
351 return ERROR_INVALID_ARGUMENTS;
356 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
362 if ((first < 0) || (first >= device->num_blocks))
365 if ((last >= device->num_blocks) || (last == -1))
366 last = device->num_blocks - 1;
368 for (i = first; i < last; i++)
370 nand_read_page(device, page, NULL, 0, oob, 6);
372 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
373 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
374 ((device->page_size == 2048) && (oob[0] != 0xff))))
376 LOG_WARNING("bad block: %i", i);
377 device->blocks[i].is_bad = 1;
381 device->blocks[i].is_bad = 0;
384 page += (device->erase_size / device->page_size);
390 int nand_read_status(struct nand_device_s *device, uint8_t *status)
393 return ERROR_NAND_DEVICE_NOT_PROBED;
395 /* Send read status command */
396 device->controller->command(device, NAND_CMD_STATUS);
401 if (device->device->options & NAND_BUSWIDTH_16)
404 device->controller->read_data(device, &data);
405 *status = data & 0xff;
409 device->controller->read_data(device, status);
415 static int nand_poll_ready(struct nand_device_s *device, int timeout)
419 device->controller->command(device, NAND_CMD_STATUS);
421 if (device->device->options & NAND_BUSWIDTH_16) {
423 device->controller->read_data(device, &data);
424 status = data & 0xff;
426 device->controller->read_data(device, &status);
428 if (status & NAND_STATUS_READY)
433 return (status & NAND_STATUS_READY) != 0;
436 int nand_probe(struct nand_device_s *device)
438 uint8_t manufacturer_id, device_id;
443 /* clear device data */
444 device->device = NULL;
445 device->manufacturer = NULL;
447 /* clear device parameters */
448 device->bus_width = 0;
449 device->address_cycles = 0;
450 device->page_size = 0;
451 device->erase_size = 0;
453 /* initialize controller (device parameters are zero, use controller default) */
454 if ((retval = device->controller->init(device) != ERROR_OK))
458 case ERROR_NAND_OPERATION_FAILED:
459 LOG_DEBUG("controller initialization failed");
460 return ERROR_NAND_OPERATION_FAILED;
461 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
462 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
463 return ERROR_NAND_OPERATION_FAILED;
465 LOG_ERROR("BUG: unknown controller initialization failure");
466 return ERROR_NAND_OPERATION_FAILED;
470 device->controller->command(device, NAND_CMD_RESET);
471 device->controller->reset(device);
473 device->controller->command(device, NAND_CMD_READID);
474 device->controller->address(device, 0x0);
476 if (device->bus_width == 8)
478 device->controller->read_data(device, &manufacturer_id);
479 device->controller->read_data(device, &device_id);
484 device->controller->read_data(device, &data_buf);
485 manufacturer_id = data_buf & 0xff;
486 device->controller->read_data(device, &data_buf);
487 device_id = data_buf & 0xff;
490 for (i = 0; nand_flash_ids[i].name; i++)
492 if (nand_flash_ids[i].id == device_id)
494 device->device = &nand_flash_ids[i];
499 for (i = 0; nand_manuf_ids[i].name; i++)
501 if (nand_manuf_ids[i].id == manufacturer_id)
503 device->manufacturer = &nand_manuf_ids[i];
508 if (!device->manufacturer)
510 device->manufacturer = &nand_manuf_ids[0];
511 device->manufacturer->id = manufacturer_id;
516 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
517 manufacturer_id, device_id);
518 return ERROR_NAND_OPERATION_FAILED;
521 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
523 /* initialize device parameters */
526 if (device->device->options & NAND_BUSWIDTH_16)
527 device->bus_width = 16;
529 device->bus_width = 8;
531 /* Do we need extended device probe information? */
532 if (device->device->page_size == 0 ||
533 device->device->erase_size == 0)
535 if (device->bus_width == 8)
537 device->controller->read_data(device, id_buff + 3);
538 device->controller->read_data(device, id_buff + 4);
539 device->controller->read_data(device, id_buff + 5);
545 device->controller->read_data(device, &data_buf);
546 id_buff[3] = data_buf;
548 device->controller->read_data(device, &data_buf);
549 id_buff[4] = data_buf;
551 device->controller->read_data(device, &data_buf);
552 id_buff[5] = data_buf >> 8;
557 if (device->device->page_size == 0)
559 device->page_size = 1 << (10 + (id_buff[4] & 3));
561 else if (device->device->page_size == 256)
563 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
564 return ERROR_NAND_OPERATION_FAILED;
568 device->page_size = device->device->page_size;
571 /* number of address cycles */
572 if (device->page_size <= 512)
574 /* small page devices */
575 if (device->device->chip_size <= 32)
576 device->address_cycles = 3;
577 else if (device->device->chip_size <= 8*1024)
578 device->address_cycles = 4;
581 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
582 device->address_cycles = 5;
587 /* large page devices */
588 if (device->device->chip_size <= 128)
589 device->address_cycles = 4;
590 else if (device->device->chip_size <= 32*1024)
591 device->address_cycles = 5;
594 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
595 device->address_cycles = 6;
600 if (device->device->erase_size == 0)
602 switch ((id_buff[4] >> 4) & 3) {
604 device->erase_size = 64 << 10;
607 device->erase_size = 128 << 10;
610 device->erase_size = 256 << 10;
613 device->erase_size =512 << 10;
619 device->erase_size = device->device->erase_size;
622 /* initialize controller, but leave parameters at the controllers default */
623 if ((retval = device->controller->init(device) != ERROR_OK))
627 case ERROR_NAND_OPERATION_FAILED:
628 LOG_DEBUG("controller initialization failed");
629 return ERROR_NAND_OPERATION_FAILED;
630 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
631 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
632 device->bus_width, device->address_cycles, device->page_size);
633 return ERROR_NAND_OPERATION_FAILED;
635 LOG_ERROR("BUG: unknown controller initialization failure");
636 return ERROR_NAND_OPERATION_FAILED;
640 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
641 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
643 for (i = 0; i < device->num_blocks; i++)
645 device->blocks[i].size = device->erase_size;
646 device->blocks[i].offset = i * device->erase_size;
647 device->blocks[i].is_erased = -1;
648 device->blocks[i].is_bad = -1;
654 static int nand_erase(struct nand_device_s *device, int first_block, int last_block)
662 return ERROR_NAND_DEVICE_NOT_PROBED;
664 if ((first_block < 0) || (last_block > device->num_blocks))
665 return ERROR_INVALID_ARGUMENTS;
667 /* make sure we know if a block is bad before erasing it */
668 for (i = first_block; i <= last_block; i++)
670 if (device->blocks[i].is_bad == -1)
672 nand_build_bbt(device, i, last_block);
677 for (i = first_block; i <= last_block; i++)
679 /* Send erase setup command */
680 device->controller->command(device, NAND_CMD_ERASE1);
682 page = i * (device->erase_size / device->page_size);
684 /* Send page address */
685 if (device->page_size <= 512)
688 device->controller->address(device, page & 0xff);
689 device->controller->address(device, (page >> 8) & 0xff);
691 /* 3rd cycle only on devices with more than 32 MiB */
692 if (device->address_cycles >= 4)
693 device->controller->address(device, (page >> 16) & 0xff);
695 /* 4th cycle only on devices with more than 8 GiB */
696 if (device->address_cycles >= 5)
697 device->controller->address(device, (page >> 24) & 0xff);
702 device->controller->address(device, page & 0xff);
703 device->controller->address(device, (page >> 8) & 0xff);
705 /* 3rd cycle only on devices with more than 128 MiB */
706 if (device->address_cycles >= 5)
707 device->controller->address(device, (page >> 16) & 0xff);
710 /* Send erase confirm command */
711 device->controller->command(device, NAND_CMD_ERASE2);
713 retval = device->controller->nand_ready ?
714 device->controller->nand_ready(device, 1000) :
715 nand_poll_ready(device, 1000);
717 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
718 return ERROR_NAND_OPERATION_TIMEOUT;
721 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
723 LOG_ERROR("couldn't read status");
724 return ERROR_NAND_OPERATION_FAILED;
729 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
730 (device->blocks[i].is_bad == 1)
733 /* continue; other blocks might still be erasable */
736 device->blocks[i].is_erased = 1;
743 static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
748 return ERROR_NAND_DEVICE_NOT_PROBED;
750 if (address % device->page_size)
752 LOG_ERROR("reads need to be page aligned");
753 return ERROR_NAND_OPERATION_FAILED;
756 page = malloc(device->page_size);
758 while (data_size > 0)
760 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
761 uint32_t page_address;
764 page_address = address / device->page_size;
766 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
768 memcpy(data, page, thisrun_size);
770 address += thisrun_size;
771 data += thisrun_size;
772 data_size -= thisrun_size;
780 static int nand_write_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
785 return ERROR_NAND_DEVICE_NOT_PROBED;
787 if (address % device->page_size)
789 LOG_ERROR("writes need to be page aligned");
790 return ERROR_NAND_OPERATION_FAILED;
793 page = malloc(device->page_size);
795 while (data_size > 0)
797 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
798 uint32_t page_address;
800 memset(page, 0xff, device->page_size);
801 memcpy(page, data, thisrun_size);
803 page_address = address / device->page_size;
805 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
807 address += thisrun_size;
808 data += thisrun_size;
809 data_size -= thisrun_size;
818 int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
823 return ERROR_NAND_DEVICE_NOT_PROBED;
825 block = page / (device->erase_size / device->page_size);
826 if (device->blocks[block].is_erased == 1)
827 device->blocks[block].is_erased = 0;
829 if (device->use_raw || device->controller->write_page == NULL)
830 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
832 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
835 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
838 return ERROR_NAND_DEVICE_NOT_PROBED;
840 if (device->use_raw || device->controller->read_page == NULL)
841 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
843 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
846 int nand_read_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
851 return ERROR_NAND_DEVICE_NOT_PROBED;
853 if (device->page_size <= 512)
855 /* small page device */
857 device->controller->command(device, NAND_CMD_READ0);
859 device->controller->command(device, NAND_CMD_READOOB);
861 /* column (always 0, we start at the beginning of a page/OOB area) */
862 device->controller->address(device, 0x0);
865 device->controller->address(device, page & 0xff);
866 device->controller->address(device, (page >> 8) & 0xff);
868 /* 4th cycle only on devices with more than 32 MiB */
869 if (device->address_cycles >= 4)
870 device->controller->address(device, (page >> 16) & 0xff);
872 /* 5th cycle only on devices with more than 8 GiB */
873 if (device->address_cycles >= 5)
874 device->controller->address(device, (page >> 24) & 0xff);
878 /* large page device */
879 device->controller->command(device, NAND_CMD_READ0);
881 /* column (0 when we start at the beginning of a page,
882 * or 2048 for the beginning of OOB area)
884 device->controller->address(device, 0x0);
886 device->controller->address(device, 0x0);
888 device->controller->address(device, 0x8);
891 device->controller->address(device, page & 0xff);
892 device->controller->address(device, (page >> 8) & 0xff);
894 /* 5th cycle only on devices with more than 128 MiB */
895 if (device->address_cycles >= 5)
896 device->controller->address(device, (page >> 16) & 0xff);
898 /* large page devices need a start command */
899 device->controller->command(device, NAND_CMD_READSTART);
902 if (device->controller->nand_ready) {
903 if (!device->controller->nand_ready(device, 100))
904 return ERROR_NAND_OPERATION_TIMEOUT;
911 if (device->controller->read_block_data != NULL)
912 (device->controller->read_block_data)(device, data, data_size);
915 for (i = 0; i < data_size;)
917 if (device->device->options & NAND_BUSWIDTH_16)
919 device->controller->read_data(device, data);
925 device->controller->read_data(device, data);
935 if (device->controller->read_block_data != NULL)
936 (device->controller->read_block_data)(device, oob, oob_size);
939 for (i = 0; i < oob_size;)
941 if (device->device->options & NAND_BUSWIDTH_16)
943 device->controller->read_data(device, oob);
949 device->controller->read_data(device, oob);
960 int nand_write_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
967 return ERROR_NAND_DEVICE_NOT_PROBED;
969 device->controller->command(device, NAND_CMD_SEQIN);
971 if (device->page_size <= 512)
973 /* column (always 0, we start at the beginning of a page/OOB area) */
974 device->controller->address(device, 0x0);
977 device->controller->address(device, page & 0xff);
978 device->controller->address(device, (page >> 8) & 0xff);
980 /* 4th cycle only on devices with more than 32 MiB */
981 if (device->address_cycles >= 4)
982 device->controller->address(device, (page >> 16) & 0xff);
984 /* 5th cycle only on devices with more than 8 GiB */
985 if (device->address_cycles >= 5)
986 device->controller->address(device, (page >> 24) & 0xff);
990 /* column (0 when we start at the beginning of a page,
991 * or 2048 for the beginning of OOB area)
993 device->controller->address(device, 0x0);
995 device->controller->address(device, 0x0);
997 device->controller->address(device, 0x8);
1000 device->controller->address(device, page & 0xff);
1001 device->controller->address(device, (page >> 8) & 0xff);
1003 /* 5th cycle only on devices with more than 128 MiB */
1004 if (device->address_cycles >= 5)
1005 device->controller->address(device, (page >> 16) & 0xff);
1010 if (device->controller->write_block_data != NULL)
1011 (device->controller->write_block_data)(device, data, data_size);
1014 for (i = 0; i < data_size;)
1016 if (device->device->options & NAND_BUSWIDTH_16)
1018 uint16_t data_buf = le_to_h_u16(data);
1019 device->controller->write_data(device, data_buf);
1025 device->controller->write_data(device, *data);
1035 if (device->controller->write_block_data != NULL)
1036 (device->controller->write_block_data)(device, oob, oob_size);
1039 for (i = 0; i < oob_size;)
1041 if (device->device->options & NAND_BUSWIDTH_16)
1043 uint16_t oob_buf = le_to_h_u16(data);
1044 device->controller->write_data(device, oob_buf);
1050 device->controller->write_data(device, *oob);
1058 device->controller->command(device, NAND_CMD_PAGEPROG);
1060 retval = device->controller->nand_ready ?
1061 device->controller->nand_ready(device, 100) :
1062 nand_poll_ready(device, 100);
1064 return ERROR_NAND_OPERATION_TIMEOUT;
1066 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1068 LOG_ERROR("couldn't read status");
1069 return ERROR_NAND_OPERATION_FAILED;
1072 if (status & NAND_STATUS_FAIL)
1074 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1075 return ERROR_NAND_OPERATION_FAILED;
1081 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1088 command_print(cmd_ctx, "no NAND flash devices configured");
1092 for (p = nand_devices, i = 0; p; p = p->next, i++)
1095 command_print(cmd_ctx, "#%i: %s (%s) "
1096 "pagesize: %i, buswidth: %i,\n\t"
1097 "blocksize: %i, blocks: %i",
1098 i, p->device->name, p->manufacturer->name,
1099 p->page_size, p->bus_width,
1100 p->erase_size, p->num_blocks);
1102 command_print(cmd_ctx, "#%i: not probed", i);
1108 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1118 return ERROR_COMMAND_SYNTAX_ERROR;
1124 first = last = strtoul(args[1], NULL, 0);
1127 first = strtoul(args[1], NULL, 0);
1128 last = strtoul(args[2], NULL, 0);
1132 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1137 if (first >= p->num_blocks)
1138 first = p->num_blocks - 1;
1140 if (last >= p->num_blocks)
1141 last = p->num_blocks - 1;
1143 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1144 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1146 for (j = first; j <= last; j++)
1148 char *erase_state, *bad_state;
1150 if (p->blocks[j].is_erased == 0)
1151 erase_state = "not erased";
1152 else if (p->blocks[j].is_erased == 1)
1153 erase_state = "erased";
1155 erase_state = "erase state unknown";
1157 if (p->blocks[j].is_bad == 0)
1159 else if (p->blocks[j].is_bad == 1)
1160 bad_state = " (marked bad)";
1162 bad_state = " (block condition unknown)";
1164 command_print(cmd_ctx,
1165 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1167 p->blocks[j].offset,
1168 p->blocks[j].size / 1024,
1175 command_print(cmd_ctx, "#%s: not probed", args[0]);
1182 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1189 return ERROR_COMMAND_SYNTAX_ERROR;
1192 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1195 if ((retval = nand_probe(p)) == ERROR_OK)
1197 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1199 else if (retval == ERROR_NAND_OPERATION_FAILED)
1201 command_print(cmd_ctx, "probing failed for NAND flash device");
1205 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1210 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1216 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1221 if (argc != 1 && argc != 3)
1223 return ERROR_COMMAND_SYNTAX_ERROR;
1227 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1231 unsigned long offset;
1232 unsigned long length;
1234 /* erase specified part of the chip; or else everything */
1236 unsigned long size = p->erase_size * p->num_blocks;
1238 offset = strtoul(args[1], &cp, 0);
1239 if (*cp || (offset == ULONG_MAX)
1240 || (offset % p->erase_size) != 0
1242 return ERROR_INVALID_ARGUMENTS;
1244 length = strtoul(args[2], &cp, 0);
1245 if (*cp || (length == ULONG_MAX)
1247 || (length % p->erase_size) != 0
1248 || (length + offset) > size)
1249 return ERROR_INVALID_ARGUMENTS;
1251 offset /= p->erase_size;
1252 length /= p->erase_size;
1255 length = p->num_blocks;
1258 retval = nand_erase(p, offset, offset + length - 1);
1259 if (retval == ERROR_OK)
1261 command_print(cmd_ctx, "erased blocks %lu to %lu "
1262 "on NAND flash device #%s '%s'",
1263 offset, offset + length,
1264 args[0], p->device->name);
1266 else if (retval == ERROR_NAND_OPERATION_FAILED)
1268 command_print(cmd_ctx, "erase failed");
1272 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1277 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1283 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1290 if ((argc < 1) || (argc > 3) || (argc == 2))
1292 return ERROR_COMMAND_SYNTAX_ERROR;
1296 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1298 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds",
1300 return ERROR_INVALID_ARGUMENTS;
1306 unsigned long offset;
1307 unsigned long length;
1309 offset = strtoul(args[1], &cp, 0);
1310 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1312 return ERROR_INVALID_ARGUMENTS;
1314 offset /= p->erase_size;
1316 length = strtoul(args[2], &cp, 0);
1317 if (*cp || length == ULONG_MAX || length % p->erase_size)
1319 return ERROR_INVALID_ARGUMENTS;
1322 length /= p->erase_size;
1325 last = offset + length;
1328 retval = nand_build_bbt(p, first, last);
1329 if (retval == ERROR_OK)
1331 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1332 "use \"nand info\" command to list blocks");
1334 else if (retval == ERROR_NAND_OPERATION_FAILED)
1336 command_print(cmd_ctx, "error when checking for bad blocks on "
1337 "NAND flash device");
1341 command_print(cmd_ctx, "unknown error when checking for bad "
1342 "blocks on NAND flash device");
1348 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1351 uint32_t binary_size;
1353 enum oob_formats oob_format = NAND_OOB_NONE;
1357 duration_t duration;
1358 char *duration_text;
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1368 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1371 uint8_t *page = NULL;
1372 uint32_t page_size = 0;
1373 uint8_t *oob = NULL;
1374 uint32_t oob_size = 0;
1375 const int *eccpos = NULL;
1377 offset = strtoul(args[2], NULL, 0);
1382 for (i = 3; i < argc; i++)
1384 if (!strcmp(args[i], "oob_raw"))
1385 oob_format |= NAND_OOB_RAW;
1386 else if (!strcmp(args[i], "oob_only"))
1387 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1388 else if (!strcmp(args[i], "oob_softecc"))
1389 oob_format |= NAND_OOB_SW_ECC;
1390 else if (!strcmp(args[i], "oob_softecc_kw"))
1391 oob_format |= NAND_OOB_SW_ECC_KW;
1394 command_print(cmd_ctx, "unknown option: %s", args[i]);
1395 return ERROR_COMMAND_SYNTAX_ERROR;
1400 duration_start_measure(&duration);
1402 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1407 buf_cnt = binary_size = fileio.size;
1409 if (!(oob_format & NAND_OOB_ONLY))
1411 page_size = p->page_size;
1412 page = malloc(p->page_size);
1415 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1417 if (p->page_size == 512) {
1419 eccpos = nand_oob_16.eccpos;
1420 } else if (p->page_size == 2048) {
1422 eccpos = nand_oob_64.eccpos;
1424 oob = malloc(oob_size);
1427 if (offset % p->page_size)
1429 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1430 fileio_close(&fileio);
1442 fileio_read(&fileio, page_size, page, &size_read);
1443 buf_cnt -= size_read;
1444 if (size_read < page_size)
1446 memset(page + size_read, 0xff, page_size - size_read);
1450 if (oob_format & NAND_OOB_SW_ECC)
1454 memset(oob, 0xff, oob_size);
1455 for (i = 0, j = 0; i < page_size; i += 256) {
1456 nand_calculate_ecc(p, page + i, ecc);
1457 oob[eccpos[j++]] = ecc[0];
1458 oob[eccpos[j++]] = ecc[1];
1459 oob[eccpos[j++]] = ecc[2];
1461 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1464 * In this case eccpos is not used as
1465 * the ECC data is always stored contigously
1466 * at the end of the OOB area. It consists
1467 * of 10 bytes per 512-byte data block.
1470 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1471 memset(oob, 0xff, oob_size);
1472 for (i = 0; i < page_size; i += 512) {
1473 nand_calculate_ecc_kw(p, page + i, ecc);
1477 else if (NULL != oob)
1479 fileio_read(&fileio, oob_size, oob, &size_read);
1480 buf_cnt -= size_read;
1481 if (size_read < oob_size)
1483 memset(oob + size_read, 0xff, oob_size - size_read);
1487 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1489 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1490 args[1], args[0], offset);
1492 fileio_close(&fileio);
1498 offset += page_size;
1501 fileio_close(&fileio);
1506 duration_stop_measure(&duration, &duration_text);
1507 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8" PRIx32 " in %s",
1508 args[1], args[0], offset, duration_text);
1509 free(duration_text);
1510 duration_text = NULL;
1514 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1520 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1526 return ERROR_COMMAND_SYNTAX_ERROR;
1529 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1535 duration_t duration;
1536 char *duration_text;
1539 uint8_t *page = NULL;
1540 uint32_t page_size = 0;
1541 uint8_t *oob = NULL;
1542 uint32_t oob_size = 0;
1543 uint32_t address = strtoul(args[2], NULL, 0);
1544 uint32_t size = strtoul(args[3], NULL, 0);
1545 uint32_t bytes_done = 0;
1546 enum oob_formats oob_format = NAND_OOB_NONE;
1551 for (i = 4; i < argc; i++)
1553 if (!strcmp(args[i], "oob_raw"))
1554 oob_format |= NAND_OOB_RAW;
1555 else if (!strcmp(args[i], "oob_only"))
1556 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1558 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1562 if ((address % p->page_size) || (size % p->page_size))
1564 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1568 if (!(oob_format & NAND_OOB_ONLY))
1570 page_size = p->page_size;
1571 page = malloc(p->page_size);
1574 if (oob_format & NAND_OOB_RAW)
1576 if (p->page_size == 512)
1578 else if (p->page_size == 2048)
1580 oob = malloc(oob_size);
1583 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1588 duration_start_measure(&duration);
1592 uint32_t size_written;
1593 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1595 command_print(cmd_ctx, "reading NAND flash page failed");
1598 fileio_close(&fileio);
1604 fileio_write(&fileio, page_size, page, &size_written);
1605 bytes_done += page_size;
1610 fileio_write(&fileio, oob_size, oob, &size_written);
1611 bytes_done += oob_size;
1614 size -= p->page_size;
1615 address += p->page_size;
1622 fileio_close(&fileio);
1624 duration_stop_measure(&duration, &duration_text);
1625 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1626 free(duration_text);
1627 duration_text = NULL;
1631 command_print(cmd_ctx, "#%s: not probed", args[0]);
1636 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1642 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1646 if ((argc < 1) || (argc > 2))
1648 return ERROR_COMMAND_SYNTAX_ERROR;
1651 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1658 if (strcmp("enable", args[1]) == 0)
1662 else if (strcmp("disable", args[1]) == 0)
1668 return ERROR_COMMAND_SYNTAX_ERROR;
1672 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1676 command_print(cmd_ctx, "#%s: not probed", args[0]);
1681 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);