1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
31 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
32 //static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34 static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36 /* NAND flash controller
38 extern struct nand_flash_controller davinci_nand_controller;
39 extern struct nand_flash_controller lpc3180_nand_controller;
40 extern struct nand_flash_controller orion_nand_controller;
41 extern struct nand_flash_controller s3c2410_nand_controller;
42 extern struct nand_flash_controller s3c2412_nand_controller;
43 extern struct nand_flash_controller s3c2440_nand_controller;
44 extern struct nand_flash_controller s3c2443_nand_controller;
45 extern struct nand_flash_controller imx31_nand_flash_controller;
47 /* extern struct nand_flash_controller boundary_scan_nand_controller; */
49 static struct nand_flash_controller *nand_flash_controllers[] =
51 &davinci_nand_controller,
52 &lpc3180_nand_controller,
53 &orion_nand_controller,
54 &s3c2410_nand_controller,
55 &s3c2412_nand_controller,
56 &s3c2440_nand_controller,
57 &s3c2443_nand_controller,
58 &imx31_nand_flash_controller,
59 /* &boundary_scan_nand_controller, */
63 /* configured NAND devices and NAND Flash command handler */
64 static struct nand_device *nand_devices = NULL;
65 static struct command *nand_cmd;
69 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
72 * Pagesize; 0, 256, 512
73 * 0 get this information from the extended chip ID
74 * 256 256 Byte page size
75 * 512 512 Byte page size
77 static struct nand_info nand_flash_ids[] =
79 /* start "museum" IDs */
80 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
81 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
82 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
83 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
84 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
85 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
86 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
87 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
88 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
89 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
91 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
92 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
93 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
94 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
95 /* end "museum" IDs */
97 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
98 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
99 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
100 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
102 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
103 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
104 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
105 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
107 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
108 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
109 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
113 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
114 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
115 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
122 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
123 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
124 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
125 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
127 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
128 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
129 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
130 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
132 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
133 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
134 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
135 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
137 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
138 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
139 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
140 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
142 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
143 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
144 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
145 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
147 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
148 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
149 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
150 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
152 {NULL, 0, 0, 0, 0, 0 }
155 /* Manufacturer ID list
157 static struct nand_manufacturer nand_manuf_ids[] =
160 {NAND_MFR_TOSHIBA, "Toshiba"},
161 {NAND_MFR_SAMSUNG, "Samsung"},
162 {NAND_MFR_FUJITSU, "Fujitsu"},
163 {NAND_MFR_NATIONAL, "National"},
164 {NAND_MFR_RENESAS, "Renesas"},
165 {NAND_MFR_STMICRO, "ST Micro"},
166 {NAND_MFR_HYNIX, "Hynix"},
167 {NAND_MFR_MICRON, "Micron"},
172 * Define default oob placement schemes for large and small page devices
176 static struct nand_ecclayout nand_oob_8 = {
187 static struct nand_ecclayout nand_oob_16 = {
189 .eccpos = {0, 1, 2, 3, 6, 7},
195 static struct nand_ecclayout nand_oob_64 = {
198 40, 41, 42, 43, 44, 45, 46, 47,
199 48, 49, 50, 51, 52, 53, 54, 55,
200 56, 57, 58, 59, 60, 61, 62, 63},
206 /* nand device <nand_controller> [controller options]
208 COMMAND_HANDLER(handle_nand_device_command)
215 LOG_WARNING("incomplete flash device nand configuration");
216 return ERROR_FLASH_BANK_INVALID;
219 for (i = 0; nand_flash_controllers[i]; i++)
221 struct nand_device *p, *c;
223 if (strcmp(CMD_ARGV[0], nand_flash_controllers[i]->name) == 0)
225 /* register flash specific commands */
226 if ((retval = nand_flash_controllers[i]->register_commands(CMD_CTX)) != ERROR_OK)
228 LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[0]);
232 c = malloc(sizeof(struct nand_device));
234 c->controller = nand_flash_controllers[i];
235 c->controller_priv = NULL;
236 c->manufacturer = NULL;
239 c->address_cycles = 0;
244 retval = CALL_COMMAND_HANDLER(nand_flash_controllers[i]->nand_device_command, c);
245 if (ERROR_OK != retval)
247 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
252 /* put NAND device in linked list */
255 /* find last flash device */
256 for (p = nand_devices; p && p->next; p = p->next);
269 /* no valid NAND controller was found (i.e. the configuration option,
270 * didn't match one of the compiled-in controllers)
272 LOG_ERROR("No valid NAND flash controller found (%s)", CMD_ARGV[0]);
273 LOG_ERROR("compiled-in NAND flash controllers:");
274 for (i = 0; nand_flash_controllers[i]; i++)
276 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
282 int nand_register_commands(struct command_context *cmd_ctx)
284 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
286 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
291 struct nand_device *get_nand_device_by_num(int num)
293 struct nand_device *p;
296 for (p = nand_devices; p; p = p->next)
307 COMMAND_HELPER(nand_command_get_device_by_num, unsigned name_index,
308 struct nand_device **nand)
310 const char *str = CMD_ARGV[name_index];
312 COMMAND_PARSE_NUMBER(uint, str, num);
313 *nand = get_nand_device_by_num(num);
315 command_print(CMD_CTX, "NAND flash device '#%s' is out of bounds", str);
316 return ERROR_INVALID_ARGUMENTS;
321 static int nand_build_bbt(struct nand_device *nand, int first, int last)
327 if ((first < 0) || (first >= nand->num_blocks))
330 if ((last >= nand->num_blocks) || (last == -1))
331 last = nand->num_blocks - 1;
333 for (i = first; i < last; i++)
335 nand_read_page(nand, page, NULL, 0, oob, 6);
337 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
338 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
339 ((nand->page_size == 2048) && (oob[0] != 0xff))))
341 LOG_WARNING("bad block: %i", i);
342 nand->blocks[i].is_bad = 1;
346 nand->blocks[i].is_bad = 0;
349 page += (nand->erase_size / nand->page_size);
355 int nand_read_status(struct nand_device *nand, uint8_t *status)
358 return ERROR_NAND_DEVICE_NOT_PROBED;
360 /* Send read status command */
361 nand->controller->command(nand, NAND_CMD_STATUS);
366 if (nand->device->options & NAND_BUSWIDTH_16)
369 nand->controller->read_data(nand, &data);
370 *status = data & 0xff;
374 nand->controller->read_data(nand, status);
380 static int nand_poll_ready(struct nand_device *nand, int timeout)
384 nand->controller->command(nand, NAND_CMD_STATUS);
386 if (nand->device->options & NAND_BUSWIDTH_16) {
388 nand->controller->read_data(nand, &data);
389 status = data & 0xff;
391 nand->controller->read_data(nand, &status);
393 if (status & NAND_STATUS_READY)
398 return (status & NAND_STATUS_READY) != 0;
401 int nand_probe(struct nand_device *nand)
403 uint8_t manufacturer_id, device_id;
408 /* clear device data */
410 nand->manufacturer = NULL;
412 /* clear device parameters */
414 nand->address_cycles = 0;
416 nand->erase_size = 0;
418 /* initialize controller (device parameters are zero, use controller default) */
419 if ((retval = nand->controller->init(nand) != ERROR_OK))
423 case ERROR_NAND_OPERATION_FAILED:
424 LOG_DEBUG("controller initialization failed");
425 return ERROR_NAND_OPERATION_FAILED;
426 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
427 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
428 return ERROR_NAND_OPERATION_FAILED;
430 LOG_ERROR("BUG: unknown controller initialization failure");
431 return ERROR_NAND_OPERATION_FAILED;
435 nand->controller->command(nand, NAND_CMD_RESET);
436 nand->controller->reset(nand);
438 nand->controller->command(nand, NAND_CMD_READID);
439 nand->controller->address(nand, 0x0);
441 if (nand->bus_width == 8)
443 nand->controller->read_data(nand, &manufacturer_id);
444 nand->controller->read_data(nand, &device_id);
449 nand->controller->read_data(nand, &data_buf);
450 manufacturer_id = data_buf & 0xff;
451 nand->controller->read_data(nand, &data_buf);
452 device_id = data_buf & 0xff;
455 for (i = 0; nand_flash_ids[i].name; i++)
457 if (nand_flash_ids[i].id == device_id)
459 nand->device = &nand_flash_ids[i];
464 for (i = 0; nand_manuf_ids[i].name; i++)
466 if (nand_manuf_ids[i].id == manufacturer_id)
468 nand->manufacturer = &nand_manuf_ids[i];
473 if (!nand->manufacturer)
475 nand->manufacturer = &nand_manuf_ids[0];
476 nand->manufacturer->id = manufacturer_id;
481 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
482 manufacturer_id, device_id);
483 return ERROR_NAND_OPERATION_FAILED;
486 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
488 /* initialize device parameters */
491 if (nand->device->options & NAND_BUSWIDTH_16)
492 nand->bus_width = 16;
496 /* Do we need extended device probe information? */
497 if (nand->device->page_size == 0 ||
498 nand->device->erase_size == 0)
500 if (nand->bus_width == 8)
502 nand->controller->read_data(nand, id_buff + 3);
503 nand->controller->read_data(nand, id_buff + 4);
504 nand->controller->read_data(nand, id_buff + 5);
510 nand->controller->read_data(nand, &data_buf);
511 id_buff[3] = data_buf;
513 nand->controller->read_data(nand, &data_buf);
514 id_buff[4] = data_buf;
516 nand->controller->read_data(nand, &data_buf);
517 id_buff[5] = data_buf >> 8;
522 if (nand->device->page_size == 0)
524 nand->page_size = 1 << (10 + (id_buff[4] & 3));
526 else if (nand->device->page_size == 256)
528 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
529 return ERROR_NAND_OPERATION_FAILED;
533 nand->page_size = nand->device->page_size;
536 /* number of address cycles */
537 if (nand->page_size <= 512)
539 /* small page devices */
540 if (nand->device->chip_size <= 32)
541 nand->address_cycles = 3;
542 else if (nand->device->chip_size <= 8*1024)
543 nand->address_cycles = 4;
546 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
547 nand->address_cycles = 5;
552 /* large page devices */
553 if (nand->device->chip_size <= 128)
554 nand->address_cycles = 4;
555 else if (nand->device->chip_size <= 32*1024)
556 nand->address_cycles = 5;
559 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
560 nand->address_cycles = 6;
565 if (nand->device->erase_size == 0)
567 switch ((id_buff[4] >> 4) & 3) {
569 nand->erase_size = 64 << 10;
572 nand->erase_size = 128 << 10;
575 nand->erase_size = 256 << 10;
578 nand->erase_size =512 << 10;
584 nand->erase_size = nand->device->erase_size;
587 /* initialize controller, but leave parameters at the controllers default */
588 if ((retval = nand->controller->init(nand) != ERROR_OK))
592 case ERROR_NAND_OPERATION_FAILED:
593 LOG_DEBUG("controller initialization failed");
594 return ERROR_NAND_OPERATION_FAILED;
595 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
596 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
597 nand->bus_width, nand->address_cycles, nand->page_size);
598 return ERROR_NAND_OPERATION_FAILED;
600 LOG_ERROR("BUG: unknown controller initialization failure");
601 return ERROR_NAND_OPERATION_FAILED;
605 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
606 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
608 for (i = 0; i < nand->num_blocks; i++)
610 nand->blocks[i].size = nand->erase_size;
611 nand->blocks[i].offset = i * nand->erase_size;
612 nand->blocks[i].is_erased = -1;
613 nand->blocks[i].is_bad = -1;
619 static int nand_erase(struct nand_device *nand, int first_block, int last_block)
627 return ERROR_NAND_DEVICE_NOT_PROBED;
629 if ((first_block < 0) || (last_block > nand->num_blocks))
630 return ERROR_INVALID_ARGUMENTS;
632 /* make sure we know if a block is bad before erasing it */
633 for (i = first_block; i <= last_block; i++)
635 if (nand->blocks[i].is_bad == -1)
637 nand_build_bbt(nand, i, last_block);
642 for (i = first_block; i <= last_block; i++)
644 /* Send erase setup command */
645 nand->controller->command(nand, NAND_CMD_ERASE1);
647 page = i * (nand->erase_size / nand->page_size);
649 /* Send page address */
650 if (nand->page_size <= 512)
653 nand->controller->address(nand, page & 0xff);
654 nand->controller->address(nand, (page >> 8) & 0xff);
656 /* 3rd cycle only on devices with more than 32 MiB */
657 if (nand->address_cycles >= 4)
658 nand->controller->address(nand, (page >> 16) & 0xff);
660 /* 4th cycle only on devices with more than 8 GiB */
661 if (nand->address_cycles >= 5)
662 nand->controller->address(nand, (page >> 24) & 0xff);
667 nand->controller->address(nand, page & 0xff);
668 nand->controller->address(nand, (page >> 8) & 0xff);
670 /* 3rd cycle only on devices with more than 128 MiB */
671 if (nand->address_cycles >= 5)
672 nand->controller->address(nand, (page >> 16) & 0xff);
675 /* Send erase confirm command */
676 nand->controller->command(nand, NAND_CMD_ERASE2);
678 retval = nand->controller->nand_ready ?
679 nand->controller->nand_ready(nand, 1000) :
680 nand_poll_ready(nand, 1000);
682 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
683 return ERROR_NAND_OPERATION_TIMEOUT;
686 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
688 LOG_ERROR("couldn't read status");
689 return ERROR_NAND_OPERATION_FAILED;
694 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
695 (nand->blocks[i].is_bad == 1)
698 /* continue; other blocks might still be erasable */
701 nand->blocks[i].is_erased = 1;
708 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
713 return ERROR_NAND_DEVICE_NOT_PROBED;
715 if (address % nand->page_size)
717 LOG_ERROR("reads need to be page aligned");
718 return ERROR_NAND_OPERATION_FAILED;
721 page = malloc(nand->page_size);
723 while (data_size > 0)
725 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
726 uint32_t page_address;
729 page_address = address / nand->page_size;
731 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
733 memcpy(data, page, thisrun_size);
735 address += thisrun_size;
736 data += thisrun_size;
737 data_size -= thisrun_size;
745 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
750 return ERROR_NAND_DEVICE_NOT_PROBED;
752 if (address % nand->page_size)
754 LOG_ERROR("writes need to be page aligned");
755 return ERROR_NAND_OPERATION_FAILED;
758 page = malloc(nand->page_size);
760 while (data_size > 0)
762 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
763 uint32_t page_address;
765 memset(page, 0xff, nand->page_size);
766 memcpy(page, data, thisrun_size);
768 page_address = address / nand->page_size;
770 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
772 address += thisrun_size;
773 data += thisrun_size;
774 data_size -= thisrun_size;
783 int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
788 return ERROR_NAND_DEVICE_NOT_PROBED;
790 block = page / (nand->erase_size / nand->page_size);
791 if (nand->blocks[block].is_erased == 1)
792 nand->blocks[block].is_erased = 0;
794 if (nand->use_raw || nand->controller->write_page == NULL)
795 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
797 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
800 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
803 return ERROR_NAND_DEVICE_NOT_PROBED;
805 if (nand->use_raw || nand->controller->read_page == NULL)
806 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
808 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
811 int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
816 return ERROR_NAND_DEVICE_NOT_PROBED;
818 if (nand->page_size <= 512)
820 /* small page device */
822 nand->controller->command(nand, NAND_CMD_READ0);
824 nand->controller->command(nand, NAND_CMD_READOOB);
826 /* column (always 0, we start at the beginning of a page/OOB area) */
827 nand->controller->address(nand, 0x0);
830 nand->controller->address(nand, page & 0xff);
831 nand->controller->address(nand, (page >> 8) & 0xff);
833 /* 4th cycle only on devices with more than 32 MiB */
834 if (nand->address_cycles >= 4)
835 nand->controller->address(nand, (page >> 16) & 0xff);
837 /* 5th cycle only on devices with more than 8 GiB */
838 if (nand->address_cycles >= 5)
839 nand->controller->address(nand, (page >> 24) & 0xff);
843 /* large page device */
844 nand->controller->command(nand, NAND_CMD_READ0);
846 /* column (0 when we start at the beginning of a page,
847 * or 2048 for the beginning of OOB area)
849 nand->controller->address(nand, 0x0);
851 nand->controller->address(nand, 0x0);
853 nand->controller->address(nand, 0x8);
856 nand->controller->address(nand, page & 0xff);
857 nand->controller->address(nand, (page >> 8) & 0xff);
859 /* 5th cycle only on devices with more than 128 MiB */
860 if (nand->address_cycles >= 5)
861 nand->controller->address(nand, (page >> 16) & 0xff);
863 /* large page devices need a start command */
864 nand->controller->command(nand, NAND_CMD_READSTART);
867 if (nand->controller->nand_ready) {
868 if (!nand->controller->nand_ready(nand, 100))
869 return ERROR_NAND_OPERATION_TIMEOUT;
876 if (nand->controller->read_block_data != NULL)
877 (nand->controller->read_block_data)(nand, data, data_size);
880 for (i = 0; i < data_size;)
882 if (nand->device->options & NAND_BUSWIDTH_16)
884 nand->controller->read_data(nand, data);
890 nand->controller->read_data(nand, data);
900 if (nand->controller->read_block_data != NULL)
901 (nand->controller->read_block_data)(nand, oob, oob_size);
904 for (i = 0; i < oob_size;)
906 if (nand->device->options & NAND_BUSWIDTH_16)
908 nand->controller->read_data(nand, oob);
914 nand->controller->read_data(nand, oob);
925 int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
932 return ERROR_NAND_DEVICE_NOT_PROBED;
934 nand->controller->command(nand, NAND_CMD_SEQIN);
936 if (nand->page_size <= 512)
938 /* column (always 0, we start at the beginning of a page/OOB area) */
939 nand->controller->address(nand, 0x0);
942 nand->controller->address(nand, page & 0xff);
943 nand->controller->address(nand, (page >> 8) & 0xff);
945 /* 4th cycle only on devices with more than 32 MiB */
946 if (nand->address_cycles >= 4)
947 nand->controller->address(nand, (page >> 16) & 0xff);
949 /* 5th cycle only on devices with more than 8 GiB */
950 if (nand->address_cycles >= 5)
951 nand->controller->address(nand, (page >> 24) & 0xff);
955 /* column (0 when we start at the beginning of a page,
956 * or 2048 for the beginning of OOB area)
958 nand->controller->address(nand, 0x0);
960 nand->controller->address(nand, 0x0);
962 nand->controller->address(nand, 0x8);
965 nand->controller->address(nand, page & 0xff);
966 nand->controller->address(nand, (page >> 8) & 0xff);
968 /* 5th cycle only on devices with more than 128 MiB */
969 if (nand->address_cycles >= 5)
970 nand->controller->address(nand, (page >> 16) & 0xff);
975 if (nand->controller->write_block_data != NULL)
976 (nand->controller->write_block_data)(nand, data, data_size);
979 for (i = 0; i < data_size;)
981 if (nand->device->options & NAND_BUSWIDTH_16)
983 uint16_t data_buf = le_to_h_u16(data);
984 nand->controller->write_data(nand, data_buf);
990 nand->controller->write_data(nand, *data);
1000 if (nand->controller->write_block_data != NULL)
1001 (nand->controller->write_block_data)(nand, oob, oob_size);
1004 for (i = 0; i < oob_size;)
1006 if (nand->device->options & NAND_BUSWIDTH_16)
1008 uint16_t oob_buf = le_to_h_u16(data);
1009 nand->controller->write_data(nand, oob_buf);
1015 nand->controller->write_data(nand, *oob);
1023 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1025 retval = nand->controller->nand_ready ?
1026 nand->controller->nand_ready(nand, 100) :
1027 nand_poll_ready(nand, 100);
1029 return ERROR_NAND_OPERATION_TIMEOUT;
1031 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1033 LOG_ERROR("couldn't read status");
1034 return ERROR_NAND_OPERATION_FAILED;
1037 if (status & NAND_STATUS_FAIL)
1039 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1040 return ERROR_NAND_OPERATION_FAILED;
1046 COMMAND_HANDLER(handle_nand_list_command)
1048 struct nand_device *p;
1053 command_print(CMD_CTX, "no NAND flash devices configured");
1057 for (p = nand_devices, i = 0; p; p = p->next, i++)
1060 command_print(CMD_CTX, "#%i: %s (%s) "
1061 "pagesize: %i, buswidth: %i,\n\t"
1062 "blocksize: %i, blocks: %i",
1063 i, p->device->name, p->manufacturer->name,
1064 p->page_size, p->bus_width,
1065 p->erase_size, p->num_blocks);
1067 command_print(CMD_CTX, "#%i: not probed", i);
1073 COMMAND_HANDLER(handle_nand_info_command)
1080 struct nand_device *p;
1081 int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
1082 if (ERROR_OK != retval)
1087 return ERROR_COMMAND_SYNTAX_ERROR;
1093 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
1098 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
1099 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
1103 if (NULL == p->device)
1105 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1109 if (first >= p->num_blocks)
1110 first = p->num_blocks - 1;
1112 if (last >= p->num_blocks)
1113 last = p->num_blocks - 1;
1115 command_print(CMD_CTX, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1116 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1118 for (j = first; j <= last; j++)
1120 char *erase_state, *bad_state;
1122 if (p->blocks[j].is_erased == 0)
1123 erase_state = "not erased";
1124 else if (p->blocks[j].is_erased == 1)
1125 erase_state = "erased";
1127 erase_state = "erase state unknown";
1129 if (p->blocks[j].is_bad == 0)
1131 else if (p->blocks[j].is_bad == 1)
1132 bad_state = " (marked bad)";
1134 bad_state = " (block condition unknown)";
1136 command_print(CMD_CTX,
1137 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1139 p->blocks[j].offset,
1140 p->blocks[j].size / 1024,
1148 COMMAND_HANDLER(handle_nand_probe_command)
1152 return ERROR_COMMAND_SYNTAX_ERROR;
1155 struct nand_device *p;
1156 int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
1157 if (ERROR_OK != retval)
1160 if ((retval = nand_probe(p)) == ERROR_OK)
1162 command_print(CMD_CTX, "NAND flash device '%s' found", p->device->name);
1164 else if (retval == ERROR_NAND_OPERATION_FAILED)
1166 command_print(CMD_CTX, "probing failed for NAND flash device");
1170 command_print(CMD_CTX, "unknown error when probing NAND flash device");
1176 COMMAND_HANDLER(handle_nand_erase_command)
1178 if (CMD_ARGC != 1 && CMD_ARGC != 3)
1180 return ERROR_COMMAND_SYNTAX_ERROR;
1184 struct nand_device *p;
1185 int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
1186 if (ERROR_OK != retval)
1189 unsigned long offset;
1190 unsigned long length;
1192 /* erase specified part of the chip; or else everything */
1193 if (CMD_ARGC == 3) {
1194 unsigned long size = p->erase_size * p->num_blocks;
1196 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1197 if ((offset % p->erase_size) != 0 || offset >= size)
1198 return ERROR_INVALID_ARGUMENTS;
1200 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1201 if ((length == 0) || (length % p->erase_size) != 0
1202 || (length + offset) > size)
1203 return ERROR_INVALID_ARGUMENTS;
1205 offset /= p->erase_size;
1206 length /= p->erase_size;
1209 length = p->num_blocks;
1212 retval = nand_erase(p, offset, offset + length - 1);
1213 if (retval == ERROR_OK)
1215 command_print(CMD_CTX, "erased blocks %lu to %lu "
1216 "on NAND flash device #%s '%s'",
1217 offset, offset + length,
1218 CMD_ARGV[0], p->device->name);
1220 else if (retval == ERROR_NAND_OPERATION_FAILED)
1222 command_print(CMD_CTX, "erase failed");
1226 command_print(CMD_CTX, "unknown error when erasing NAND flash device");
1232 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1237 if ((CMD_ARGC < 1) || (CMD_ARGC > 3) || (CMD_ARGC == 2))
1239 return ERROR_COMMAND_SYNTAX_ERROR;
1243 struct nand_device *p;
1244 int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
1245 if (ERROR_OK != retval)
1250 unsigned long offset;
1251 unsigned long length;
1253 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1254 if (offset % p->erase_size)
1255 return ERROR_INVALID_ARGUMENTS;
1256 offset /= p->erase_size;
1258 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1259 if (length % p->erase_size)
1260 return ERROR_INVALID_ARGUMENTS;
1263 length /= p->erase_size;
1266 last = offset + length;
1269 retval = nand_build_bbt(p, first, last);
1270 if (retval == ERROR_OK)
1272 command_print(CMD_CTX, "checked NAND flash device for bad blocks, "
1273 "use \"nand info\" command to list blocks");
1275 else if (retval == ERROR_NAND_OPERATION_FAILED)
1277 command_print(CMD_CTX, "error when checking for bad blocks on "
1278 "NAND flash device");
1282 command_print(CMD_CTX, "unknown error when checking for bad "
1283 "blocks on NAND flash device");
1289 struct nand_fileio_state {
1296 enum oob_formats oob_format;
1303 struct fileio fileio;
1305 struct duration bench;
1308 static void nand_fileio_init(struct nand_fileio_state *state)
1310 memset(state, 0, sizeof(*state));
1311 state->oob_format = NAND_OOB_NONE;
1314 static int nand_fileio_start(struct command_context *cmd_ctx,
1315 struct nand_device *nand, const char *filename, int filemode,
1316 struct nand_fileio_state *state)
1318 if (state->address % nand->page_size)
1320 command_print(cmd_ctx, "only page-aligned addresses are supported");
1321 return ERROR_COMMAND_SYNTAX_ERROR;
1324 duration_start(&state->bench);
1326 if (NULL != filename)
1328 int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
1329 if (ERROR_OK != retval)
1331 const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
1332 command_print(cmd_ctx, "failed to open '%s' for %s access",
1336 state->file_opened = true;
1339 if (!(state->oob_format & NAND_OOB_ONLY))
1341 state->page_size = nand->page_size;
1342 state->page = malloc(nand->page_size);
1345 if (state->oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1347 if (nand->page_size == 512)
1349 state->oob_size = 16;
1350 state->eccpos = nand_oob_16.eccpos;
1352 else if (nand->page_size == 2048)
1354 state->oob_size = 64;
1355 state->eccpos = nand_oob_64.eccpos;
1357 state->oob = malloc(state->oob_size);
1362 static int nand_fileio_cleanup(struct nand_fileio_state *state)
1364 if (state->file_opened)
1365 fileio_close(&state->fileio);
1379 static int nand_fileio_finish(struct nand_fileio_state *state)
1381 nand_fileio_cleanup(state);
1382 return duration_measure(&state->bench);
1385 static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
1386 struct nand_device **dev, enum fileio_access filemode,
1387 bool need_size, bool sw_ecc)
1389 nand_fileio_init(state);
1391 unsigned minargs = need_size ? 4 : 3;
1392 if (CMD_ARGC < minargs)
1393 return ERROR_COMMAND_SYNTAX_ERROR;
1395 struct nand_device *nand;
1396 int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &nand);
1397 if (ERROR_OK != retval)
1400 if (NULL == nand->device)
1402 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1406 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
1409 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->size);
1410 if (state->size % nand->page_size)
1412 command_print(CMD_CTX, "only page-aligned sizes are supported");
1413 return ERROR_COMMAND_SYNTAX_ERROR;
1417 if (CMD_ARGC > minargs)
1419 for (unsigned i = minargs; i < CMD_ARGC; i++)
1421 if (!strcmp(CMD_ARGV[i], "oob_raw"))
1422 state->oob_format |= NAND_OOB_RAW;
1423 else if (!strcmp(CMD_ARGV[i], "oob_only"))
1424 state->oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1425 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc"))
1426 state->oob_format |= NAND_OOB_SW_ECC;
1427 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc_kw"))
1428 state->oob_format |= NAND_OOB_SW_ECC_KW;
1431 command_print(CMD_CTX, "unknown option: %s", CMD_ARGV[i]);
1432 return ERROR_COMMAND_SYNTAX_ERROR;
1437 retval = nand_fileio_start(CMD_CTX, nand, CMD_ARGV[1], filemode, state);
1438 if (ERROR_OK != retval)
1442 state->size = state->fileio.size;
1450 * @returns If no error occurred, returns number of bytes consumed;
1451 * otherwise, returns a negative error code.)
1453 static int nand_fileio_read(struct nand_device *nand,
1454 struct nand_fileio_state *s)
1456 size_t total_read = 0;
1459 if (NULL != s->page)
1461 fileio_read(&s->fileio, s->page_size, s->page, &one_read);
1462 if (one_read < s->page_size)
1463 memset(s->page + one_read, 0xff, s->page_size - one_read);
1464 total_read += one_read;
1467 if (s->oob_format & NAND_OOB_SW_ECC)
1470 memset(s->oob, 0xff, s->oob_size);
1471 for (uint32_t i = 0, j = 0; i < s->page_size; i += 256)
1473 nand_calculate_ecc(nand, s->page + i, ecc);
1474 s->oob[s->eccpos[j++]] = ecc[0];
1475 s->oob[s->eccpos[j++]] = ecc[1];
1476 s->oob[s->eccpos[j++]] = ecc[2];
1479 else if (s->oob_format & NAND_OOB_SW_ECC_KW)
1482 * In this case eccpos is not used as
1483 * the ECC data is always stored contigously
1484 * at the end of the OOB area. It consists
1485 * of 10 bytes per 512-byte data block.
1487 uint8_t *ecc = s->oob + s->oob_size - s->page_size / 512 * 10;
1488 memset(s->oob, 0xff, s->oob_size);
1489 for (uint32_t i = 0; i < s->page_size; i += 512)
1491 nand_calculate_ecc_kw(nand, s->page + i, ecc);
1495 else if (NULL != s->oob)
1497 fileio_read(&s->fileio, s->oob_size, s->oob, &one_read);
1498 if (one_read < s->oob_size)
1499 memset(s->oob + one_read, 0xff, s->oob_size - one_read);
1500 total_read += one_read;
1505 COMMAND_HANDLER(handle_nand_write_command)
1507 struct nand_device *nand = NULL;
1508 struct nand_fileio_state s;
1509 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1510 &s, &nand, FILEIO_READ, false, true);
1511 if (ERROR_OK != retval)
1514 uint32_t total_bytes = s.size;
1517 int bytes_read = nand_fileio_read(nand, &s);
1518 if (bytes_read <= 0)
1520 command_print(CMD_CTX, "error while reading file");
1521 return nand_fileio_cleanup(&s);
1523 s.size -= bytes_read;
1525 retval = nand_write_page(nand, s.address / nand->page_size,
1526 s.page, s.page_size, s.oob, s.oob_size);
1527 if (ERROR_OK != retval)
1529 command_print(CMD_CTX, "failed writing file %s "
1530 "to NAND flash %s at offset 0x%8.8" PRIx32,
1531 CMD_ARGV[1], CMD_ARGV[0], s.address);
1532 return nand_fileio_cleanup(&s);
1534 s.address += s.page_size;
1537 if (nand_fileio_finish(&s))
1539 command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
1540 "offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1541 CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
1542 duration_kbps(&s.bench, total_bytes));
1547 COMMAND_HANDLER(handle_nand_verify_command)
1549 struct nand_device *nand = NULL;
1550 struct nand_fileio_state file;
1551 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1552 &file, &nand, FILEIO_READ, false, true);
1553 if (ERROR_OK != retval)
1556 struct nand_fileio_state dev;
1557 nand_fileio_init(&dev);
1558 dev.address = file.address;
1559 dev.size = file.size;
1560 dev.oob_format = file.oob_format;
1561 retval = nand_fileio_start(CMD_CTX, nand, NULL, FILEIO_NONE, &dev);
1562 if (ERROR_OK != retval)
1565 while (file.size > 0)
1567 int retval = nand_read_page(nand, dev.address / dev.page_size,
1568 dev.page, dev.page_size, dev.oob, dev.oob_size);
1569 if (ERROR_OK != retval)
1571 command_print(CMD_CTX, "reading NAND flash page failed");
1572 nand_fileio_cleanup(&dev);
1573 return nand_fileio_cleanup(&file);
1576 int bytes_read = nand_fileio_read(nand, &file);
1577 if (bytes_read <= 0)
1579 command_print(CMD_CTX, "error while reading file");
1580 nand_fileio_cleanup(&dev);
1581 return nand_fileio_cleanup(&file);
1584 if ((dev.page && memcmp(dev.page, file.page, dev.page_size)) ||
1585 (dev.oob && memcmp(dev.oob, file.oob, dev.oob_size)) )
1587 command_print(CMD_CTX, "NAND flash contents differ "
1588 "at 0x%8.8" PRIx32, dev.address);
1589 nand_fileio_cleanup(&dev);
1590 return nand_fileio_cleanup(&file);
1593 file.size -= bytes_read;
1594 file.address += nand->page_size;
1597 if (nand_fileio_finish(&file) == ERROR_OK)
1599 command_print(CMD_CTX, "verified file %s in NAND flash %s "
1600 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1601 CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
1602 duration_kbps(&file.bench, dev.size));
1605 return nand_fileio_cleanup(&dev);
1608 COMMAND_HANDLER(handle_nand_dump_command)
1610 struct nand_device *nand = NULL;
1611 struct nand_fileio_state s;
1612 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1613 &s, &nand, FILEIO_WRITE, true, false);
1614 if (ERROR_OK != retval)
1619 size_t size_written;
1620 int retval = nand_read_page(nand, s.address / nand->page_size,
1621 s.page, s.page_size, s.oob, s.oob_size);
1622 if (ERROR_OK != retval)
1624 command_print(CMD_CTX, "reading NAND flash page failed");
1625 return nand_fileio_cleanup(&s);
1629 fileio_write(&s.fileio, s.page_size, s.page, &size_written);
1632 fileio_write(&s.fileio, s.oob_size, s.oob, &size_written);
1634 s.size -= nand->page_size;
1635 s.address += nand->page_size;
1638 if (nand_fileio_finish(&s) == ERROR_OK)
1640 command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)",
1641 s.fileio.size, duration_elapsed(&s.bench),
1642 duration_kbps(&s.bench, s.fileio.size));
1647 COMMAND_HANDLER(handle_nand_raw_access_command)
1649 if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
1651 return ERROR_COMMAND_SYNTAX_ERROR;
1654 struct nand_device *p;
1655 int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
1656 if (ERROR_OK != retval)
1659 if (NULL == p->device)
1661 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1667 if (strcmp("enable", CMD_ARGV[1]) == 0)
1669 else if (strcmp("disable", CMD_ARGV[1]) == 0)
1672 return ERROR_COMMAND_SYNTAX_ERROR;
1675 const char *msg = p->use_raw ? "enabled" : "disabled";
1676 command_print(CMD_CTX, "raw access is %s", msg);
1681 int nand_init(struct command_context *cmd_ctx)
1686 register_command(cmd_ctx, nand_cmd, "list",
1687 handle_nand_list_command, COMMAND_EXEC,
1688 "list configured NAND flash devices");
1689 register_command(cmd_ctx, nand_cmd, "info",
1690 handle_nand_info_command, COMMAND_EXEC,
1691 "print info about NAND flash device <num>");
1692 register_command(cmd_ctx, nand_cmd, "probe",
1693 handle_nand_probe_command, COMMAND_EXEC,
1694 "identify NAND flash device <num>");
1696 register_command(cmd_ctx, nand_cmd, "check_bad_blocks",
1697 handle_nand_check_bad_blocks_command, COMMAND_EXEC,
1698 "check NAND flash device <num> for bad blocks [<offset> <length>]");
1699 register_command(cmd_ctx, nand_cmd, "erase",
1700 handle_nand_erase_command, COMMAND_EXEC,
1701 "erase blocks on NAND flash device <num> [<offset> <length>]");
1702 register_command(cmd_ctx, nand_cmd, "dump",
1703 handle_nand_dump_command, COMMAND_EXEC,
1704 "dump from NAND flash device <num> <filename> "
1705 "<offset> <length> [oob_raw | oob_only]");
1706 register_command(cmd_ctx, nand_cmd, "verify",
1707 &handle_nand_verify_command, COMMAND_EXEC,
1708 "verify NAND flash device <num> <filename> <offset> "
1709 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
1710 register_command(cmd_ctx, nand_cmd, "write",
1711 handle_nand_write_command, COMMAND_EXEC,
1712 "write to NAND flash device <num> <filename> <offset> "
1713 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
1715 register_command(cmd_ctx, nand_cmd, "raw_access",
1716 handle_nand_raw_access_command, COMMAND_EXEC,
1717 "raw access to NAND flash device <num> ['enable'|'disable']");