1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
53 /* END ATMEL COPYRIGHT */
62 #include <helper/membuf.h>
63 #include <helper/time_support.h>
65 #define REG_NAME_WIDTH (12)
68 #define FLASH_BANK0_BASE 0x00080000
69 #define FLASH_BANK1_BASE 0x00100000
71 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
72 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
73 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
74 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
75 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
76 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
77 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
78 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
79 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
80 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
81 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
82 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
83 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
84 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
85 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
86 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
87 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
88 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
90 #define offset_EFC_FMR 0
91 #define offset_EFC_FCR 4
92 #define offset_EFC_FSR 8
93 #define offset_EFC_FRR 12
97 _tomhz(uint32_t freq_hz)
101 f = ((float)(freq_hz)) / 1000000.0;
105 // How the chip is configured.
107 uint32_t unique_id[4];
111 uint32_t mainosc_freq;
121 #define SAM3_CHIPID_CIDR (0x400E0740)
122 uint32_t CHIPID_CIDR;
123 #define SAM3_CHIPID_EXID (0x400E0744)
124 uint32_t CHIPID_EXID;
126 #define SAM3_SUPC_CR (0x400E1210)
129 #define SAM3_PMC_BASE (0x400E0400)
130 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
132 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
134 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
136 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
138 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
140 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
142 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
144 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
146 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
148 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
150 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
152 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
154 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
156 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
161 struct sam3_bank_private {
163 // DANGER: THERE ARE DRAGONS HERE..
164 // NOTE: If you add more 'ghost' pointers
165 // be aware that you must *manually* update
166 // these pointers in the function sam3_GetDetails()
167 // See the comment "Here there be dragons"
169 // so we can find the chip we belong to
170 struct sam3_chip *pChip;
171 // so we can find the orginal bank pointer
172 struct flash_bank *pBank;
173 unsigned bank_number;
174 uint32_t controller_address;
175 uint32_t base_address;
179 unsigned sector_size;
183 struct sam3_chip_details {
184 // THERE ARE DRAGONS HERE..
185 // note: If you add pointers here
186 // becareful about them as they
187 // may need to be updated inside
188 // the function: "sam3_GetDetails()
189 // which copy/overwrites the
190 // 'runtime' copy of this structure
191 uint32_t chipid_cidr;
195 #define SAM3_N_NVM_BITS 3
196 unsigned gpnvm[SAM3_N_NVM_BITS];
197 unsigned total_flash_size;
198 unsigned total_sram_size;
200 #define SAM3_MAX_FLASH_BANKS 2
201 // these are "initialized" from the global const data
202 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
207 struct sam3_chip *next;
210 // this is "initialized" from the global const structure
211 struct sam3_chip_details details;
212 struct target *target;
219 struct sam3_reg_list {
220 uint32_t address; size_t struct_offset; const char *name;
221 void (*explain_func)(struct sam3_chip *pInfo);
225 static struct sam3_chip *all_sam3_chips;
227 static struct sam3_chip *
228 get_current_sam3(struct command_context *cmd_ctx)
231 static struct sam3_chip *p;
233 t = get_current_target(cmd_ctx);
235 command_print(cmd_ctx, "No current target?");
241 // this should not happen
242 // the command is not registered until the chip is created?
243 command_print(cmd_ctx, "No SAM3 chips exist?");
248 if (p->target == t) {
253 command_print(cmd_ctx, "Cannot find SAM3 chip?");
258 // these are used to *initialize* the "pChip->details" structure.
259 static const struct sam3_chip_details all_sam3_details[] = {
261 .chipid_cidr = 0x28100960,
262 .name = "at91sam3u4e",
263 .total_flash_size = 256 * 1024,
264 .total_sram_size = 52 * 1024,
268 // System boots at address 0x0
269 // gpnvm[1] = selects boot code
271 // boot is via "SAMBA" (rom)
274 // Selection is via gpnvm[2]
277 // NOTE: banks 0 & 1 switch places
279 // Bank0 is the boot rom
281 // Bank1 is the boot rom
290 .base_address = FLASH_BANK0_BASE,
291 .controller_address = 0x400e0800,
293 .size_bytes = 128 * 1024,
305 .base_address = FLASH_BANK1_BASE,
306 .controller_address = 0x400e0a00,
308 .size_bytes = 128 * 1024,
317 .chipid_cidr = 0x281a0760,
318 .name = "at91sam3u2e",
319 .total_flash_size = 128 * 1024,
320 .total_sram_size = 36 * 1024,
324 // System boots at address 0x0
325 // gpnvm[1] = selects boot code
327 // boot is via "SAMBA" (rom)
330 // Selection is via gpnvm[2]
339 .base_address = FLASH_BANK0_BASE,
340 .controller_address = 0x400e0800,
342 .size_bytes = 128 * 1024,
356 .chipid_cidr = 0x28190560,
357 .name = "at91sam3u1e",
358 .total_flash_size = 64 * 1024,
359 .total_sram_size = 20 * 1024,
363 // System boots at address 0x0
364 // gpnvm[1] = selects boot code
366 // boot is via "SAMBA" (rom)
369 // Selection is via gpnvm[2]
380 .base_address = FLASH_BANK0_BASE,
381 .controller_address = 0x400e0800,
383 .size_bytes = 64 * 1024,
399 .chipid_cidr = 0x28000960,
400 .name = "at91sam3u4c",
401 .total_flash_size = 256 * 1024,
402 .total_sram_size = 52 * 1024,
406 // System boots at address 0x0
407 // gpnvm[1] = selects boot code
409 // boot is via "SAMBA" (rom)
412 // Selection is via gpnvm[2]
415 // NOTE: banks 0 & 1 switch places
417 // Bank0 is the boot rom
419 // Bank1 is the boot rom
428 .base_address = FLASH_BANK0_BASE,
429 .controller_address = 0x400e0800,
431 .size_bytes = 128 * 1024,
442 .base_address = FLASH_BANK1_BASE,
443 .controller_address = 0x400e0a00,
445 .size_bytes = 128 * 1024,
454 .chipid_cidr = 0x280a0760,
455 .name = "at91sam3u2c",
456 .total_flash_size = 128 * 1024,
457 .total_sram_size = 36 * 1024,
461 // System boots at address 0x0
462 // gpnvm[1] = selects boot code
464 // boot is via "SAMBA" (rom)
467 // Selection is via gpnvm[2]
476 .base_address = FLASH_BANK0_BASE,
477 .controller_address = 0x400e0800,
479 .size_bytes = 128 * 1024,
493 .chipid_cidr = 0x28090560,
494 .name = "at91sam3u1c",
495 .total_flash_size = 64 * 1024,
496 .total_sram_size = 20 * 1024,
500 // System boots at address 0x0
501 // gpnvm[1] = selects boot code
503 // boot is via "SAMBA" (rom)
506 // Selection is via gpnvm[2]
517 .base_address = FLASH_BANK0_BASE,
518 .controller_address = 0x400e0800,
520 .size_bytes = 64 * 1024,
543 /***********************************************************************
544 **********************************************************************
545 **********************************************************************
546 **********************************************************************
547 **********************************************************************
548 **********************************************************************/
549 /* *ATMEL* style code - from the SAM3 driver code */
552 * Get the current status of the EEFC and
553 * the value of some status bits (LOCKE, PROGE).
554 * @param pPrivate - info about the bank
555 * @param v - result goes here
558 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
561 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
562 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
564 ((unsigned int)((*v >> 2) & 1)),
565 ((unsigned int)((*v >> 1) & 1)),
566 ((unsigned int)((*v >> 0) & 1)));
572 * Get the result of the last executed command.
573 * @param pPrivate - info about the bank
574 * @param v - result goes here
577 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
581 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
585 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
590 EFC_StartCommand(struct sam3_bank_private *pPrivate,
591 unsigned command, unsigned argument)
600 // Check command & argument
603 case AT91C_EFC_FCMD_WP:
604 case AT91C_EFC_FCMD_WPL:
605 case AT91C_EFC_FCMD_EWP:
606 case AT91C_EFC_FCMD_EWPL:
607 // case AT91C_EFC_FCMD_EPL:
608 // case AT91C_EFC_FCMD_EPA:
609 case AT91C_EFC_FCMD_SLB:
610 case AT91C_EFC_FCMD_CLB:
611 n = (pPrivate->size_bytes / pPrivate->page_size);
613 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
617 case AT91C_EFC_FCMD_SFB:
618 case AT91C_EFC_FCMD_CFB:
619 if (argument >= pPrivate->pChip->details.n_gpnvms) {
620 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
621 pPrivate->pChip->details.n_gpnvms);
625 case AT91C_EFC_FCMD_GETD:
626 case AT91C_EFC_FCMD_EA:
627 case AT91C_EFC_FCMD_GLB:
628 case AT91C_EFC_FCMD_GFB:
629 case AT91C_EFC_FCMD_STUI:
630 case AT91C_EFC_FCMD_SPUI:
632 LOG_ERROR("Argument is meaningless for cmd: %d", command);
636 LOG_ERROR("Unknown command %d", command);
640 if (command == AT91C_EFC_FCMD_SPUI) {
641 // this is a very special situation.
642 // Situation (1) - error/retry - see below
643 // And we are being called recursively
644 // Situation (2) - normal, finished reading unique id
646 // it should be "ready"
647 EFC_GetStatus(pPrivate, &v);
653 // we have done this before
654 // the controller is not responding.
655 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
659 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
660 pPrivate->bank_number);
661 // we do that by issuing the *STOP* command
662 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
663 // above is recursive, and further recursion is blocked by
664 // if (command == AT91C_EFC_FCMD_SPUI) above
670 v = (0x5A << 24) | (argument << 8) | command;
671 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
672 r = target_write_u32(pPrivate->pBank->target,
673 pPrivate->controller_address + offset_EFC_FCR,
676 LOG_DEBUG("Error Write failed");
682 * Performs the given command and wait until its completion (or an error).
683 * @param pPrivate - info about the bank
684 * @param command - Command to perform.
685 * @param argument - Optional command argument.
686 * @param status - put command status bits here
689 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
697 long long ms_now, ms_end;
704 r = EFC_StartCommand(pPrivate, command, argument);
709 ms_end = 500 + timeval_ms();
713 r = EFC_GetStatus(pPrivate, &v);
717 ms_now = timeval_ms();
718 if (ms_now > ms_end) {
720 LOG_ERROR("Command timeout");
740 * Read the unique ID.
741 * @param pPrivate - info about the bank
742 * The unique ID is stored in the 'pPrivate' structure.
745 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
751 pPrivate->pChip->cfg.unique_id[0] = 0;
752 pPrivate->pChip->cfg.unique_id[1] = 0;
753 pPrivate->pChip->cfg.unique_id[2] = 0;
754 pPrivate->pChip->cfg.unique_id[3] = 0;
757 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
762 for (x = 0 ; x < 4 ; x++) {
763 r = target_read_u32(pPrivate->pChip->target,
764 pPrivate->pBank->base + (x * 4),
769 pPrivate->pChip->cfg.unique_id[x] = v;
772 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
773 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
775 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
776 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
777 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
778 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
784 * Erases the entire flash.
785 * @param pPrivate - the info about the bank.
788 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
791 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
797 * Gets current GPNVM state.
798 * @param pPrivate - info about the bank.
799 * @param gpnvm - GPNVM bit index.
800 * @param puthere - result stored here.
802 //------------------------------------------------------------------------------
804 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
810 if (pPrivate->bank_number != 0) {
811 LOG_ERROR("GPNVM only works with Bank0");
815 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
816 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
817 gpnvm,pPrivate->pChip->details.n_gpnvms);
822 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
828 r = EFC_GetResult(pPrivate, &v);
831 // Check if GPNVM is set
832 // get the bit and make it a 0/1
833 *puthere = (v >> gpnvm) & 1;
843 * Clears the selected GPNVM bit.
844 * @param pPrivate info about the bank
845 * @param gpnvm GPNVM index.
846 * @returns 0 if successful; otherwise returns an error code.
849 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
855 if (pPrivate->bank_number != 0) {
856 LOG_ERROR("GPNVM only works with Bank0");
860 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
861 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
862 gpnvm,pPrivate->pChip->details.n_gpnvms);
866 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
868 LOG_DEBUG("Failed: %d",r);
871 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
872 LOG_DEBUG("End: %d",r);
879 * Sets the selected GPNVM bit.
880 * @param pPrivate info about the bank
881 * @param gpnvm GPNVM index.
884 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
889 if (pPrivate->bank_number != 0) {
890 LOG_ERROR("GPNVM only works with Bank0");
894 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
895 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
896 gpnvm,pPrivate->pChip->details.n_gpnvms);
900 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
909 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
916 * Returns a bit field (at most 64) of locked regions within a page.
917 * @param pPrivate info about the bank
918 * @param v where to store locked bits
921 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
925 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
927 r = EFC_GetResult(pPrivate, v);
929 LOG_DEBUG("End: %d",r);
935 * Unlocks all the regions in the given address range.
936 * @param pPrivate info about the bank
937 * @param start_sector first sector to unlock
938 * @param end_sector last (inclusive) to unlock
942 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
943 unsigned start_sector,
949 uint32_t pages_per_sector;
951 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
953 /* Unlock all pages */
954 while (start_sector <= end_sector) {
955 pg = start_sector * pages_per_sector;
957 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
970 * @param pPrivate - info about the bank
971 * @param start_sector - first sector to lock
972 * @param end_sector - last sector (inclusive) to lock
975 FLASHD_Lock(struct sam3_bank_private *pPrivate,
976 unsigned start_sector,
981 uint32_t pages_per_sector;
984 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
987 while (start_sector <= end_sector) {
988 pg = start_sector * pages_per_sector;
990 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1000 /****** END SAM3 CODE ********/
1002 /* begin helpful debug code */
1005 sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
1009 if (pChip->mbuf == NULL) {
1013 membuf_vsprintf(pChip->mbuf, fmt, ap);
1017 // print the fieldname, the field value, in dec & hex, and return field value
1019 sam3_reg_fieldname(struct sam3_chip *pChip,
1020 const char *regname,
1029 // extract the field
1031 v = v & ((1 << width)-1);
1041 sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ",
1042 REG_NAME_WIDTH, regname,
1049 static const char _unknown[] = "unknown";
1050 static const char * const eproc_names[] = {
1069 #define nvpsize2 nvpsize // these two tables are identical
1070 static const char * const nvpsize[] = {
1083 "1024K bytes", // 12
1085 "2048K bytes", // 14
1090 static const char * const sramsize[] = {
1110 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1111 { 0x19, "AT91SAM9xx Series" },
1112 { 0x29, "AT91SAM9XExx Series" },
1113 { 0x34, "AT91x34 Series" },
1114 { 0x37, "CAP7 Series" },
1115 { 0x39, "CAP9 Series" },
1116 { 0x3B, "CAP11 Series" },
1117 { 0x40, "AT91x40 Series" },
1118 { 0x42, "AT91x42 Series" },
1119 { 0x55, "AT91x55 Series" },
1120 { 0x60, "AT91SAM7Axx Series" },
1121 { 0x61, "AT91SAM7AQxx Series" },
1122 { 0x63, "AT91x63 Series" },
1123 { 0x70, "AT91SAM7Sxx Series" },
1124 { 0x71, "AT91SAM7XCxx Series" },
1125 { 0x72, "AT91SAM7SExx Series" },
1126 { 0x73, "AT91SAM7Lxx Series" },
1127 { 0x75, "AT91SAM7Xxx Series" },
1128 { 0x76, "AT91SAM7SLxx Series" },
1129 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1130 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1131 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1132 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1133 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1134 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1135 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1136 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1137 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1138 { 0x92, "AT91x92 Series" },
1139 { 0xF0, "AT75Cxx Series" },
1144 static const char * const nvptype[] = {
1146 "romless or onchip flash", // 1
1147 "embedded flash memory", // 2
1148 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1149 "sram emulating flash", // 4
1156 static const char *_yes_or_no(uint32_t v)
1165 static const char * const _rc_freq[] = {
1166 "4 MHz", "8 MHz", "12 MHz", "reserved"
1170 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1175 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1176 sam3_sprintf(pChip, "(main xtal enabled: %s)\n",
1178 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1179 sam3_sprintf(pChip, "(main osc bypass: %s)\n",
1181 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1182 sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n",
1184 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1185 sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n",
1188 pChip->cfg.rc_freq = 0;
1192 pChip->cfg.rc_freq = 0;
1194 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1197 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1200 pChip->cfg.rc_freq = 12* 1000 * 1000;
1205 v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1206 sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n",
1207 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1208 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1209 sam3_sprintf(pChip, "(mainosc source: %s)\n",
1210 v ? "external xtal" : "internal RC");
1212 v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1213 sam3_sprintf(pChip, "(clock failure enabled: %s)\n",
1220 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1226 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1227 sam3_sprintf(pChip,"\n");
1229 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1230 sam3_sprintf(pChip, "%s\n", eproc_names[v]);
1232 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1233 sam3_sprintf(pChip, "%s\n", nvpsize[v]);
1235 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1236 sam3_sprintf(pChip, "%s\n", nvpsize2[v]);
1238 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1239 sam3_sprintf(pChip, "%s\n", sramsize[ v ]);
1241 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1243 for (x = 0 ; archnames[x].name ; x++) {
1244 if (v == archnames[x].value) {
1245 cp = archnames[x].name;
1250 sam3_sprintf(pChip, "%s\n", cp);
1252 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1253 sam3_sprintf(pChip, "%s\n", nvptype[ v ]);
1255 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1256 sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v));
1260 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1265 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1266 sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v));
1268 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1270 v = (v * pChip->cfg.slow_freq) / 16;
1271 pChip->cfg.mainosc_freq = v;
1273 sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1275 pChip->cfg.slow_freq / 1000,
1276 pChip->cfg.slow_freq % 1000);
1281 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1285 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1286 sam3_sprintf(pChip,"\n");
1287 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1288 sam3_sprintf(pChip,"\n");
1289 pChip->cfg.plla_freq = 0;
1291 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n");
1292 } else if (diva == 0) {
1293 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n");
1294 } else if (diva == 1) {
1295 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1296 sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n",
1297 _tomhz(pChip->cfg.plla_freq));
1303 sam3_explain_mckr(struct sam3_chip *pChip)
1305 uint32_t css, pres, fin = 0;
1307 const char *cp = NULL;
1309 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1312 fin = pChip->cfg.slow_freq;
1316 fin = pChip->cfg.mainosc_freq;
1320 fin = pChip->cfg.plla_freq;
1324 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1325 fin = 480 * 1000 * 1000;
1329 cp = "upll (*ERROR* UPLL is disabled)";
1337 sam3_sprintf(pChip, "%s (%3.03f Mhz)\n",
1340 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1341 switch (pres & 0x07) {
1344 cp = "selected clock";
1377 sam3_sprintf(pChip, "(%s)\n", cp);
1379 // sam3 has a *SINGLE* clock -
1380 // other at91 series parts have divisors for these.
1381 pChip->cfg.cpu_freq = fin;
1382 pChip->cfg.mclk_freq = fin;
1383 pChip->cfg.fclk_freq = fin;
1384 sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n",
1389 static struct sam3_chip *
1390 target2sam3(struct target *pTarget)
1392 struct sam3_chip *pChip;
1394 if (pTarget == NULL) {
1398 pChip = all_sam3_chips;
1400 if (pChip->target == pTarget) {
1401 break; // return below
1403 pChip = pChip->next;
1411 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1413 // this function exists to help
1414 // keep funky offsetof() errors
1415 // and casting from causing bugs
1417 // By using prototypes - we can detect what would
1418 // be casting errors.
1420 return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
1424 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1425 static const struct sam3_reg_list sam3_all_regs[] = {
1426 SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1427 SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1428 SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1429 SAM3_ENTRY(CKGR_UCKR , NULL),
1430 SAM3_ENTRY(PMC_FSMR , NULL),
1431 SAM3_ENTRY(PMC_FSPR , NULL),
1432 SAM3_ENTRY(PMC_IMR , NULL),
1433 SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1434 SAM3_ENTRY(PMC_PCK0 , NULL),
1435 SAM3_ENTRY(PMC_PCK1 , NULL),
1436 SAM3_ENTRY(PMC_PCK2 , NULL),
1437 SAM3_ENTRY(PMC_PCSR , NULL),
1438 SAM3_ENTRY(PMC_SCSR , NULL),
1439 SAM3_ENTRY(PMC_SR , NULL),
1440 SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1441 SAM3_ENTRY(CHIPID_EXID , NULL),
1442 SAM3_ENTRY(SUPC_CR, NULL),
1444 // TERMINATE THE LIST
1452 static struct sam3_bank_private *
1453 get_sam3_bank_private(struct flash_bank *bank)
1455 return (struct sam3_bank_private *)(bank->driver_priv);
1459 * Given a pointer to where it goes in the structure,
1460 * determine the register name, address from the all registers table.
1462 static const struct sam3_reg_list *
1463 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1465 const struct sam3_reg_list *pReg;
1467 pReg = &(sam3_all_regs[0]);
1468 while (pReg->name) {
1469 uint32_t *pPossible;
1471 // calculate where this one go..
1472 // it is "possibly" this register.
1474 pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1476 // well? Is it this register
1477 if (pPossible == goes_here) {
1485 // This is *TOTAL*PANIC* - we are totally screwed.
1486 LOG_ERROR("INVALID SAM3 REGISTER");
1492 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1494 const struct sam3_reg_list *pReg;
1497 pReg = sam3_GetReg(pChip, goes_here);
1502 r = target_read_u32(pChip->target, pReg->address, goes_here);
1503 if (r != ERROR_OK) {
1504 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1505 pReg->name, (unsigned)(pReg->address), r);
1513 sam3_ReadAllRegs(struct sam3_chip *pChip)
1516 const struct sam3_reg_list *pReg;
1518 pReg = &(sam3_all_regs[0]);
1519 while (pReg->name) {
1520 r = sam3_ReadThisReg(pChip,
1521 sam3_get_reg_ptr(&(pChip->cfg), pReg));
1522 if (r != ERROR_OK) {
1523 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1524 pReg->name, ((unsigned)(pReg->address)), r);
1536 sam3_GetInfo(struct sam3_chip *pChip)
1538 const struct sam3_reg_list *pReg;
1541 membuf_reset(pChip->mbuf);
1544 pReg = &(sam3_all_regs[0]);
1545 while (pReg->name) {
1547 LOG_DEBUG("Start: %s", pReg->name);
1548 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1549 sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n",
1554 if (pReg->explain_func) {
1555 (*(pReg->explain_func))(pChip);
1557 LOG_DEBUG("End: %s", pReg->name);
1560 sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1561 sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1562 sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1563 sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1564 sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1567 sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1568 pChip->cfg.unique_id[0],
1569 pChip->cfg.unique_id[1],
1570 pChip->cfg.unique_id[2],
1571 pChip->cfg.unique_id[3]);
1579 sam3_erase_check(struct flash_bank *bank)
1584 if (bank->target->state != TARGET_HALTED) {
1585 LOG_ERROR("Target not halted");
1586 return ERROR_TARGET_NOT_HALTED;
1588 if (0 == bank->num_sectors) {
1589 LOG_ERROR("Target: not supported/not probed\n");
1593 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1594 for (x = 0 ; x < bank->num_sectors ; x++) {
1595 bank->sectors[x].is_erased = 1;
1603 sam3_protect_check(struct flash_bank *bank)
1608 struct sam3_bank_private *pPrivate;
1611 if (bank->target->state != TARGET_HALTED) {
1612 LOG_ERROR("Target not halted");
1613 return ERROR_TARGET_NOT_HALTED;
1616 pPrivate = get_sam3_bank_private(bank);
1618 LOG_ERROR("no private for this bank?");
1621 if (!(pPrivate->probed)) {
1622 return ERROR_FLASH_BANK_NOT_PROBED;
1625 r = FLASHD_GetLockBits(pPrivate , &v);
1626 if (r != ERROR_OK) {
1627 LOG_DEBUG("Failed: %d",r);
1631 for (x = 0 ; x < pPrivate->nsectors ; x++) {
1632 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1638 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
1640 struct sam3_chip *pChip;
1642 pChip = all_sam3_chips;
1644 // is this an existing chip?
1646 if (pChip->target == bank->target) {
1649 pChip = pChip->next;
1653 // this is a *NEW* chip
1654 pChip = calloc(1, sizeof(struct sam3_chip));
1656 LOG_ERROR("NO RAM!");
1659 pChip->target = bank->target;
1661 pChip->next = all_sam3_chips;
1662 all_sam3_chips = pChip;
1663 pChip->target = bank->target;
1664 // assumption is this runs at 32khz
1665 pChip->cfg.slow_freq = 32768;
1667 pChip->mbuf = membuf_new();
1668 if (!(pChip->mbuf)) {
1669 LOG_ERROR("no memory");
1674 switch (bank->base) {
1676 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1677 ((unsigned int)(bank->base)),
1678 ((unsigned int)(FLASH_BANK0_BASE)),
1679 ((unsigned int)(FLASH_BANK1_BASE)));
1682 case FLASH_BANK0_BASE:
1683 bank->driver_priv = &(pChip->details.bank[0]);
1684 bank->bank_number = 0;
1685 pChip->details.bank[0].pChip = pChip;
1686 pChip->details.bank[0].pBank = bank;
1688 case FLASH_BANK1_BASE:
1689 bank->driver_priv = &(pChip->details.bank[1]);
1690 bank->bank_number = 1;
1691 pChip->details.bank[1].pChip = pChip;
1692 pChip->details.bank[1].pBank = bank;
1696 // we initialize after probing.
1701 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1703 const struct sam3_chip_details *pDetails;
1704 struct sam3_chip *pChip;
1706 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
1712 pDetails = all_sam3_details;
1713 while (pDetails->name) {
1714 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
1720 if (pDetails->name == NULL) {
1721 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1722 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1723 // Help the victim, print details about the chip
1724 membuf_reset(pPrivate->pChip->mbuf);
1725 membuf_sprintf(pPrivate->pChip->mbuf,
1726 "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1727 pPrivate->pChip->cfg.CHIPID_CIDR);
1728 sam3_explain_chipid_cidr(pPrivate->pChip);
1729 cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
1732 cp = membuf_strtok(NULL, "\n", &vp);
1737 // DANGER: THERE ARE DRAGONS HERE
1739 // get our pChip - it is going
1740 // to be over-written shortly
1741 pChip = pPrivate->pChip;
1743 // Note that, in reality:
1745 // pPrivate = &(pChip->details.bank[0])
1746 // or pPrivate = &(pChip->details.bank[1])
1749 // save the "bank" pointers
1750 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1751 saved_banks[ x ] = pChip->details.bank[x].pBank;
1754 // Overwrite the "details" structure.
1755 memcpy(&(pPrivate->pChip->details),
1757 sizeof(pPrivate->pChip->details));
1759 // now fix the ghosted pointers
1760 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1761 pChip->details.bank[x].pChip = pChip;
1762 pChip->details.bank[x].pBank = saved_banks[x];
1765 // update the *BANK*SIZE*
1774 _sam3_probe(struct flash_bank *bank, int noise)
1778 struct sam3_bank_private *pPrivate;
1781 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1782 if (bank->target->state != TARGET_HALTED)
1784 LOG_ERROR("Target not halted");
1785 return ERROR_TARGET_NOT_HALTED;
1788 pPrivate = get_sam3_bank_private(bank);
1790 LOG_ERROR("Invalid/unknown bank number\n");
1794 r = sam3_ReadAllRegs(pPrivate->pChip);
1795 if (r != ERROR_OK) {
1801 r = sam3_GetInfo(pPrivate->pChip);
1802 if (r != ERROR_OK) {
1805 if (!(pPrivate->pChip->probed)) {
1806 pPrivate->pChip->probed = 1;
1808 r = sam3_GetDetails(pPrivate);
1809 if (r != ERROR_OK) {
1814 // update the flash bank size
1815 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1816 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
1817 bank->size = pPrivate->pChip->details.bank[0].size_bytes;
1822 if (bank->sectors == NULL) {
1823 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1824 if (bank->sectors == NULL) {
1825 LOG_ERROR("No memory!");
1828 bank->num_sectors = pPrivate->nsectors;
1830 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
1831 bank->sectors[x].size = pPrivate->sector_size;
1832 bank->sectors[x].offset = x * (pPrivate->sector_size);
1834 bank->sectors[x].is_erased = -1;
1835 bank->sectors[x].is_protected = -1;
1839 pPrivate->probed = 1;
1841 r = sam3_protect_check(bank);
1842 if (r != ERROR_OK) {
1846 LOG_DEBUG("Bank = %d, nbanks = %d",
1847 pPrivate->bank_number , pPrivate->pChip->details.n_banks);
1848 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1850 // it appears to be associated with the *last* flash bank.
1851 FLASHD_ReadUniqueID(pPrivate);
1858 sam3_probe(struct flash_bank *bank)
1860 return _sam3_probe(bank, 1);
1864 sam3_auto_probe(struct flash_bank *bank)
1866 return _sam3_probe(bank, 0);
1872 sam3_erase(struct flash_bank *bank, int first, int last)
1874 struct sam3_bank_private *pPrivate;
1878 if (bank->target->state != TARGET_HALTED) {
1879 LOG_ERROR("Target not halted");
1880 return ERROR_TARGET_NOT_HALTED;
1883 r = sam3_auto_probe(bank);
1884 if (r != ERROR_OK) {
1885 LOG_DEBUG("Here,r=%d",r);
1889 pPrivate = get_sam3_bank_private(bank);
1890 if (!(pPrivate->probed)) {
1891 return ERROR_FLASH_BANK_NOT_PROBED;
1894 if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
1897 return FLASHD_EraseEntireBank(pPrivate);
1899 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1904 sam3_protect(struct flash_bank *bank, int set, int first, int last)
1906 struct sam3_bank_private *pPrivate;
1910 if (bank->target->state != TARGET_HALTED) {
1911 LOG_ERROR("Target not halted");
1912 return ERROR_TARGET_NOT_HALTED;
1915 pPrivate = get_sam3_bank_private(bank);
1916 if (!(pPrivate->probed)) {
1917 return ERROR_FLASH_BANK_NOT_PROBED;
1921 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1923 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1925 LOG_DEBUG("End: r=%d",r);
1933 sam3_info(struct flash_bank *bank, char *buf, int buf_size)
1935 if (bank->target->state != TARGET_HALTED) {
1936 LOG_ERROR("Target not halted");
1937 return ERROR_TARGET_NOT_HALTED;
1944 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1949 adr = pagenum * pPrivate->page_size;
1950 adr += adr + pPrivate->base_address;
1952 r = target_read_memory(pPrivate->pChip->target,
1954 4, /* THIS*MUST*BE* in 32bit values */
1955 pPrivate->page_size / 4,
1957 if (r != ERROR_OK) {
1958 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
1963 // The code below is basically this:
1965 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
1967 // Only the *CPU* can write to the flash buffer.
1968 // the DAP cannot... so - we download this 28byte thing
1969 // Run the algorithm - (below)
1970 // to program the device
1972 // ========================================
1973 // #include <stdint.h>
1977 // const uint32_t *src;
1979 // volatile uint32_t *base;
1984 // uint32_t sam3_function(struct foo *p)
1986 // volatile uint32_t *v;
1988 // const uint32_t *s;
2010 // ========================================
2014 static const uint8_t
2015 sam3_page_write_opcodes[] = {
2016 // 24 0000 0446 mov r4, r0
2018 // 25 0002 6168 ldr r1, [r4, #4]
2020 // 26 0004 0068 ldr r0, [r0, #0]
2022 // 27 0006 A268 ldr r2, [r4, #8]
2024 // 28 @ lr needed for prologue
2026 // 30 0008 51F8043B ldr r3, [r1], #4
2027 0x51,0xf8,0x04,0x3b,
2028 // 31 000c 12F1FF32 adds r2, r2, #-1
2029 0x12,0xf1,0xff,0x32,
2030 // 32 0010 40F8043B str r3, [r0], #4
2031 0x40,0xf8,0x04,0x3b,
2032 // 33 0014 F8D1 bne .L2
2034 // 34 0016 E268 ldr r2, [r4, #12]
2036 // 35 0018 2369 ldr r3, [r4, #16]
2038 // 36 001a 5360 str r3, [r2, #4]
2040 // 37 001c 0832 adds r2, r2, #8
2043 // 39 001e 1068 ldr r0, [r2, #0]
2045 // 40 0020 10F0010F tst r0, #1
2046 0x10,0xf0,0x01,0x0f,
2047 // 41 0024 FBD0 beq .L4
2050 // 43 0026 FEE7 b .done
2056 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2062 adr = pagenum * pPrivate->page_size;
2063 adr += (adr + pPrivate->base_address);
2065 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2066 r = target_write_memory(pPrivate->pChip->target,
2068 4, /* THIS*MUST*BE* in 32bit values */
2069 pPrivate->page_size / 4,
2071 if (r != ERROR_OK) {
2072 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2076 r = EFC_PerformCommand(pPrivate,
2077 // send Erase & Write Page
2082 if (r != ERROR_OK) {
2083 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2085 if (status & (1 << 2)) {
2086 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2089 if (status & (1 << 1)) {
2090 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2101 sam3_write(struct flash_bank *bank,
2110 unsigned page_offset;
2111 struct sam3_bank_private *pPrivate;
2112 uint8_t *pagebuffer;
2114 // incase we bail further below, set this to null
2117 // ignore dumb requests
2123 if (bank->target->state != TARGET_HALTED) {
2124 LOG_ERROR("Target not halted");
2125 r = ERROR_TARGET_NOT_HALTED;
2129 pPrivate = get_sam3_bank_private(bank);
2130 if (!(pPrivate->probed)) {
2131 r = ERROR_FLASH_BANK_NOT_PROBED;
2136 if ((offset + count) > pPrivate->size_bytes) {
2137 LOG_ERROR("Flash write error - past end of bank");
2138 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2139 (unsigned int)(offset),
2140 (unsigned int)(count),
2141 (unsigned int)(pPrivate->size_bytes));
2146 pagebuffer = malloc(pPrivate->page_size);
2148 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2153 // what page do we start & end in?
2154 page_cur = offset / pPrivate->page_size;
2155 page_end = (offset + count - 1) / pPrivate->page_size;
2157 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2158 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2160 // Special case: all one page
2163 // (1) non-aligned start
2165 // (3) non-aligned end.
2167 // Handle special case - all one page.
2168 if (page_cur == page_end) {
2169 LOG_DEBUG("Special case, all in one page");
2170 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2171 if (r != ERROR_OK) {
2175 page_offset = (offset & (pPrivate->page_size-1));
2176 memcpy(pagebuffer + page_offset,
2180 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2181 if (r != ERROR_OK) {
2188 // non-aligned start
2189 page_offset = offset & (pPrivate->page_size - 1);
2191 LOG_DEBUG("Not-Aligned start");
2193 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2194 if (r != ERROR_OK) {
2198 // over-write with new data
2199 n = (pPrivate->page_size - page_offset);
2200 memcpy(pagebuffer + page_offset,
2204 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2205 if (r != ERROR_OK) {
2215 // intermediate large pages
2216 // also - the final *terminal*
2217 // if that terminal page is a full page
2218 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2219 (int)page_cur, (int)page_end, (unsigned int)(count));
2221 while ((page_cur < page_end) &&
2222 (count >= pPrivate->page_size)) {
2223 r = sam3_page_write(pPrivate, page_cur, buffer);
2224 if (r != ERROR_OK) {
2227 count -= pPrivate->page_size;
2228 buffer += pPrivate->page_size;
2232 // terminal partial page?
2234 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2235 // we have a partial page
2236 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2237 if (r != ERROR_OK) {
2240 // data goes at start
2241 memcpy(pagebuffer, buffer, count);
2242 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2243 if (r != ERROR_OK) {
2258 COMMAND_HANDLER(sam3_handle_info_command)
2260 struct sam3_chip *pChip;
2266 pChip = get_current_sam3(CMD_CTX);
2273 // bank0 must exist before we can do anything
2274 if (pChip->details.bank[0].pBank == NULL) {
2277 command_print(CMD_CTX,
2278 "Please define bank %d via command: flash bank %s ... ",
2280 at91sam3_flash.name);
2284 // if bank 0 is not probed, then probe it
2285 if (!(pChip->details.bank[0].probed)) {
2286 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2287 if (r != ERROR_OK) {
2291 // above garentees the "chip details" structure is valid
2292 // and thus, bank private areas are valid
2293 // and we have a SAM3 chip, what a concept!
2296 // auto-probe other banks, 0 done above
2297 for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2298 // skip banks not present
2299 if (!(pChip->details.bank[x].present)) {
2303 if (pChip->details.bank[x].pBank == NULL) {
2307 if (pChip->details.bank[x].probed) {
2311 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2312 if (r != ERROR_OK) {
2318 r = sam3_GetInfo(pChip);
2319 if (r != ERROR_OK) {
2320 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2326 cp = membuf_strtok(pChip->mbuf, "\n", &vp);
2328 command_print(CMD_CTX,"%s", cp);
2329 cp = membuf_strtok(NULL, "\n", &vp);
2334 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2338 struct sam3_chip *pChip;
2340 pChip = get_current_sam3(CMD_CTX);
2345 if (pChip->target->state != TARGET_HALTED) {
2346 LOG_ERROR("sam3 - target not halted");
2347 return ERROR_TARGET_NOT_HALTED;
2351 if (pChip->details.bank[0].pBank == NULL) {
2352 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2353 at91sam3_flash.name);
2356 if (!pChip->details.bank[0].probed) {
2357 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2358 if (r != ERROR_OK) {
2366 command_print(CMD_CTX,"Too many parameters\n");
2367 return ERROR_COMMAND_SYNTAX_ERROR;
2377 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) {
2381 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2387 if (0 == strcmp("show", CMD_ARGV[0])) {
2391 for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2392 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2393 if (r != ERROR_OK) {
2396 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
2400 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2401 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2402 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
2405 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
2406 return ERROR_COMMAND_SYNTAX_ERROR;
2411 command_print(CMD_CTX, "Missing GPNVM number");
2412 return ERROR_COMMAND_SYNTAX_ERROR;
2415 if (0 == strcmp("set", CMD_ARGV[0])) {
2416 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2417 } else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2418 (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
2419 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2421 command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
2422 r = ERROR_COMMAND_SYNTAX_ERROR;
2427 COMMAND_HANDLER(sam3_handle_slowclk_command)
2429 struct sam3_chip *pChip;
2431 pChip = get_current_sam3(CMD_CTX);
2445 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2447 // absurd slow clock of 200Khz?
2448 command_print(CMD_CTX,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2449 return ERROR_COMMAND_SYNTAX_ERROR;
2451 pChip->cfg.slow_freq = v;
2456 command_print(CMD_CTX,"Too many parameters");
2457 return ERROR_COMMAND_SYNTAX_ERROR;
2460 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2461 (int)(pChip->cfg.slow_freq/ 1000),
2462 (int)(pChip->cfg.slow_freq% 1000));
2466 static const struct command_registration at91sam3_exec_command_handlers[] = {
2469 .handler = &sam3_handle_gpnvm_command,
2470 .mode = COMMAND_EXEC,
2471 .usage = "[(set|clear) [<bit_id>]]",
2472 .help = "Without arguments, shows the gpnvm register; "
2473 "otherwise, sets or clear the specified bit.",
2477 .handler = &sam3_handle_info_command,
2478 .mode = COMMAND_EXEC,
2479 .help = "print information about the current sam3 chip",
2483 .handler = &sam3_handle_slowclk_command,
2484 .mode = COMMAND_EXEC,
2486 .help = "set the slowclock frequency (default 32768hz)",
2488 COMMAND_REGISTRATION_DONE
2490 static const struct command_registration at91sam3_command_handlers[] = {
2493 .mode = COMMAND_ANY,
2494 .help = "at91sam3 flash command group",
2495 .chain = at91sam3_exec_command_handlers,
2497 COMMAND_REGISTRATION_DONE
2500 struct flash_driver at91sam3_flash = {
2502 .commands = at91sam3_command_handlers,
2503 .flash_bank_command = &sam3_flash_bank_command,
2504 .erase = &sam3_erase,
2505 .protect = &sam3_protect,
2506 .write = &sam3_write,
2507 .probe = &sam3_probe,
2508 .auto_probe = &sam3_auto_probe,
2509 .erase_check = &sam3_erase_check,
2510 .protect_check = &sam3_protect_check,