1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ****************************************************************************/
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
58 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
76 /* at91sam3sd series (has always two flash banks) */
77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
81 /* at91sam3n series (has always one flash bank) */
82 #define FLASH_BANK_BASE_N 0x00400000
84 /* at91sam3a/x series has two flash banks*/
85 #define FLASH_BANK0_BASE_AX 0x00080000
86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
87 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
88 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
90 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
91 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
92 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
93 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
94 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
95 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
99 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
100 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
101 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
102 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
103 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
104 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
105 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
106 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
107 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
109 #define offset_EFC_FMR 0
110 #define offset_EFC_FCR 4
111 #define offset_EFC_FSR 8
112 #define offset_EFC_FRR 12
114 extern struct flash_driver at91sam3_flash;
116 static float _tomhz(uint32_t freq_hz)
120 f = ((float)(freq_hz)) / 1000000.0;
124 /* How the chip is configured. */
126 uint32_t unique_id[4];
130 uint32_t mainosc_freq;
140 #define SAM3_CHIPID_CIDR (0x400E0740)
141 uint32_t CHIPID_CIDR;
142 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_CIDR2;
144 #define SAM3_CHIPID_EXID (0x400E0744)
145 uint32_t CHIPID_EXID;
146 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
147 uint32_t CHIPID_EXID2;
150 #define SAM3_PMC_BASE (0x400E0400)
151 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
153 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
155 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
157 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
159 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
161 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
163 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
165 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
167 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
169 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
171 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
173 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
175 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
177 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
182 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
183 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
184 * the flash wait state (FWS) should be set to 6. It seems like that the
185 * cause of the problem is not the flash itself, but the flash write
186 * buffer. Ie the wait states have to be set before writing into the
188 * Tested and confirmed with SAM3N and SAM3U
191 struct sam3_bank_private {
193 /* DANGER: THERE ARE DRAGONS HERE.. */
194 /* NOTE: If you add more 'ghost' pointers */
195 /* be aware that you must *manually* update */
196 /* these pointers in the function sam3_GetDetails() */
197 /* See the comment "Here there be dragons" */
199 /* so we can find the chip we belong to */
200 struct sam3_chip *pChip;
201 /* so we can find the original bank pointer */
202 struct flash_bank *pBank;
203 unsigned bank_number;
204 uint32_t controller_address;
205 uint32_t base_address;
206 uint32_t flash_wait_states;
210 unsigned sector_size;
214 struct sam3_chip_details {
215 /* THERE ARE DRAGONS HERE.. */
216 /* note: If you add pointers here */
217 /* be careful about them as they */
218 /* may need to be updated inside */
219 /* the function: "sam3_GetDetails() */
220 /* which copy/overwrites the */
221 /* 'runtime' copy of this structure */
222 uint32_t chipid_cidr;
226 #define SAM3_N_NVM_BITS 3
227 unsigned gpnvm[SAM3_N_NVM_BITS];
228 unsigned total_flash_size;
229 unsigned total_sram_size;
231 #define SAM3_MAX_FLASH_BANKS 2
232 /* these are "initialized" from the global const data */
233 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
237 struct sam3_chip *next;
240 /* this is "initialized" from the global const structure */
241 struct sam3_chip_details details;
242 struct target *target;
247 struct sam3_reg_list {
248 uint32_t address; size_t struct_offset; const char *name;
249 void (*explain_func)(struct sam3_chip *pInfo);
252 static struct sam3_chip *all_sam3_chips;
254 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
257 static struct sam3_chip *p;
259 t = get_current_target(cmd_ctx);
261 command_print(cmd_ctx, "No current target?");
267 /* this should not happen */
268 /* the command is not registered until the chip is created? */
269 command_print(cmd_ctx, "No SAM3 chips exist?");
278 command_print(cmd_ctx, "Cannot find SAM3 chip?");
282 /* these are used to *initialize* the "pChip->details" structure. */
283 static const struct sam3_chip_details all_sam3_details[] = {
284 /* Start at91sam3u* series */
286 .chipid_cidr = 0x28100960,
287 .name = "at91sam3u4e",
288 .total_flash_size = 256 * 1024,
289 .total_sram_size = 52 * 1024,
293 /* System boots at address 0x0 */
294 /* gpnvm[1] = selects boot code */
295 /* if gpnvm[1] == 0 */
296 /* boot is via "SAMBA" (rom) */
298 /* boot is via FLASH */
299 /* Selection is via gpnvm[2] */
302 /* NOTE: banks 0 & 1 switch places */
303 /* if gpnvm[2] == 0 */
304 /* Bank0 is the boot rom */
306 /* Bank1 is the boot rom */
315 .base_address = FLASH_BANK0_BASE_U,
316 .controller_address = 0x400e0800,
317 .flash_wait_states = 6, /* workaround silicon bug */
319 .size_bytes = 128 * 1024,
331 .base_address = FLASH_BANK1_BASE_U,
332 .controller_address = 0x400e0a00,
333 .flash_wait_states = 6, /* workaround silicon bug */
335 .size_bytes = 128 * 1024,
344 .chipid_cidr = 0x281a0760,
345 .name = "at91sam3u2e",
346 .total_flash_size = 128 * 1024,
347 .total_sram_size = 36 * 1024,
351 /* System boots at address 0x0 */
352 /* gpnvm[1] = selects boot code */
353 /* if gpnvm[1] == 0 */
354 /* boot is via "SAMBA" (rom) */
356 /* boot is via FLASH */
357 /* Selection is via gpnvm[2] */
366 .base_address = FLASH_BANK0_BASE_U,
367 .controller_address = 0x400e0800,
368 .flash_wait_states = 6, /* workaround silicon bug */
370 .size_bytes = 128 * 1024,
384 .chipid_cidr = 0x28190560,
385 .name = "at91sam3u1e",
386 .total_flash_size = 64 * 1024,
387 .total_sram_size = 20 * 1024,
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
408 .base_address = FLASH_BANK0_BASE_U,
409 .controller_address = 0x400e0800,
410 .flash_wait_states = 6, /* workaround silicon bug */
412 .size_bytes = 64 * 1024,
428 .chipid_cidr = 0x28000960,
429 .name = "at91sam3u4c",
430 .total_flash_size = 256 * 1024,
431 .total_sram_size = 52 * 1024,
435 /* System boots at address 0x0 */
436 /* gpnvm[1] = selects boot code */
437 /* if gpnvm[1] == 0 */
438 /* boot is via "SAMBA" (rom) */
440 /* boot is via FLASH */
441 /* Selection is via gpnvm[2] */
444 /* NOTE: banks 0 & 1 switch places */
445 /* if gpnvm[2] == 0 */
446 /* Bank0 is the boot rom */
448 /* Bank1 is the boot rom */
457 .base_address = FLASH_BANK0_BASE_U,
458 .controller_address = 0x400e0800,
459 .flash_wait_states = 6, /* workaround silicon bug */
461 .size_bytes = 128 * 1024,
472 .base_address = FLASH_BANK1_BASE_U,
473 .controller_address = 0x400e0a00,
474 .flash_wait_states = 6, /* workaround silicon bug */
476 .size_bytes = 128 * 1024,
485 .chipid_cidr = 0x280a0760,
486 .name = "at91sam3u2c",
487 .total_flash_size = 128 * 1024,
488 .total_sram_size = 36 * 1024,
492 /* System boots at address 0x0 */
493 /* gpnvm[1] = selects boot code */
494 /* if gpnvm[1] == 0 */
495 /* boot is via "SAMBA" (rom) */
497 /* boot is via FLASH */
498 /* Selection is via gpnvm[2] */
507 .base_address = FLASH_BANK0_BASE_U,
508 .controller_address = 0x400e0800,
509 .flash_wait_states = 6, /* workaround silicon bug */
511 .size_bytes = 128 * 1024,
525 .chipid_cidr = 0x28090560,
526 .name = "at91sam3u1c",
527 .total_flash_size = 64 * 1024,
528 .total_sram_size = 20 * 1024,
532 /* System boots at address 0x0 */
533 /* gpnvm[1] = selects boot code */
534 /* if gpnvm[1] == 0 */
535 /* boot is via "SAMBA" (rom) */
537 /* boot is via FLASH */
538 /* Selection is via gpnvm[2] */
549 .base_address = FLASH_BANK0_BASE_U,
550 .controller_address = 0x400e0800,
551 .flash_wait_states = 6, /* workaround silicon bug */
553 .size_bytes = 64 * 1024,
568 /* Start at91sam3s* series */
570 /* Note: The preliminary at91sam3s datasheet says on page 302 */
571 /* that the flash controller is at address 0x400E0800. */
572 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
574 .chipid_cidr = 0x28A00960,
575 .name = "at91sam3s4c",
576 .total_flash_size = 256 * 1024,
577 .total_sram_size = 48 * 1024,
587 .base_address = FLASH_BANK_BASE_S,
588 .controller_address = 0x400e0a00,
589 .flash_wait_states = 6, /* workaround silicon bug */
591 .size_bytes = 256 * 1024,
593 .sector_size = 16384,
607 .chipid_cidr = 0x28900960,
608 .name = "at91sam3s4b",
609 .total_flash_size = 256 * 1024,
610 .total_sram_size = 48 * 1024,
620 .base_address = FLASH_BANK_BASE_S,
621 .controller_address = 0x400e0a00,
622 .flash_wait_states = 6, /* workaround silicon bug */
624 .size_bytes = 256 * 1024,
626 .sector_size = 16384,
639 .chipid_cidr = 0x28800960,
640 .name = "at91sam3s4a",
641 .total_flash_size = 256 * 1024,
642 .total_sram_size = 48 * 1024,
652 .base_address = FLASH_BANK_BASE_S,
653 .controller_address = 0x400e0a00,
654 .flash_wait_states = 6, /* workaround silicon bug */
656 .size_bytes = 256 * 1024,
658 .sector_size = 16384,
671 .chipid_cidr = 0x28AA0760,
672 .name = "at91sam3s2c",
673 .total_flash_size = 128 * 1024,
674 .total_sram_size = 32 * 1024,
684 .base_address = FLASH_BANK_BASE_S,
685 .controller_address = 0x400e0a00,
686 .flash_wait_states = 6, /* workaround silicon bug */
688 .size_bytes = 128 * 1024,
690 .sector_size = 16384,
703 .chipid_cidr = 0x289A0760,
704 .name = "at91sam3s2b",
705 .total_flash_size = 128 * 1024,
706 .total_sram_size = 32 * 1024,
716 .base_address = FLASH_BANK_BASE_S,
717 .controller_address = 0x400e0a00,
718 .flash_wait_states = 6, /* workaround silicon bug */
720 .size_bytes = 128 * 1024,
722 .sector_size = 16384,
735 .chipid_cidr = 0x298B0A60,
736 .name = "at91sam3sd8a",
737 .total_flash_size = 512 * 1024,
738 .total_sram_size = 64 * 1024,
748 .base_address = FLASH_BANK0_BASE_SD,
749 .controller_address = 0x400e0a00,
750 .flash_wait_states = 6, /* workaround silicon bug */
752 .size_bytes = 256 * 1024,
754 .sector_size = 32768,
763 .base_address = FLASH_BANK1_BASE_512K_SD,
764 .controller_address = 0x400e0a00,
765 .flash_wait_states = 6, /* workaround silicon bug */
767 .size_bytes = 256 * 1024,
769 .sector_size = 32768,
775 .chipid_cidr = 0x299B0A60,
776 .name = "at91sam3sd8b",
777 .total_flash_size = 512 * 1024,
778 .total_sram_size = 64 * 1024,
788 .base_address = FLASH_BANK0_BASE_SD,
789 .controller_address = 0x400e0a00,
790 .flash_wait_states = 6, /* workaround silicon bug */
792 .size_bytes = 256 * 1024,
794 .sector_size = 32768,
803 .base_address = FLASH_BANK1_BASE_512K_SD,
804 .controller_address = 0x400e0a00,
805 .flash_wait_states = 6, /* workaround silicon bug */
807 .size_bytes = 256 * 1024,
809 .sector_size = 32768,
815 .chipid_cidr = 0x29ab0a60,
816 .name = "at91sam3sd8c",
817 .total_flash_size = 512 * 1024,
818 .total_sram_size = 64 * 1024,
828 .base_address = FLASH_BANK0_BASE_SD,
829 .controller_address = 0x400e0a00,
830 .flash_wait_states = 6, /* workaround silicon bug */
832 .size_bytes = 256 * 1024,
834 .sector_size = 32768,
843 .base_address = FLASH_BANK1_BASE_512K_SD,
844 .controller_address = 0x400e0a00,
845 .flash_wait_states = 6, /* workaround silicon bug */
847 .size_bytes = 256 * 1024,
849 .sector_size = 32768,
855 .chipid_cidr = 0x288A0760,
856 .name = "at91sam3s2a",
857 .total_flash_size = 128 * 1024,
858 .total_sram_size = 32 * 1024,
868 .base_address = FLASH_BANK_BASE_S,
869 .controller_address = 0x400e0a00,
870 .flash_wait_states = 6, /* workaround silicon bug */
872 .size_bytes = 128 * 1024,
874 .sector_size = 16384,
887 .chipid_cidr = 0x28A90560,
888 .name = "at91sam3s1c",
889 .total_flash_size = 64 * 1024,
890 .total_sram_size = 16 * 1024,
900 .base_address = FLASH_BANK_BASE_S,
901 .controller_address = 0x400e0a00,
902 .flash_wait_states = 6, /* workaround silicon bug */
904 .size_bytes = 64 * 1024,
906 .sector_size = 16384,
919 .chipid_cidr = 0x28990560,
920 .name = "at91sam3s1b",
921 .total_flash_size = 64 * 1024,
922 .total_sram_size = 16 * 1024,
932 .base_address = FLASH_BANK_BASE_S,
933 .controller_address = 0x400e0a00,
934 .flash_wait_states = 6, /* workaround silicon bug */
936 .size_bytes = 64 * 1024,
938 .sector_size = 16384,
951 .chipid_cidr = 0x28890560,
952 .name = "at91sam3s1a",
953 .total_flash_size = 64 * 1024,
954 .total_sram_size = 16 * 1024,
964 .base_address = FLASH_BANK_BASE_S,
965 .controller_address = 0x400e0a00,
966 .flash_wait_states = 6, /* workaround silicon bug */
968 .size_bytes = 64 * 1024,
970 .sector_size = 16384,
983 .chipid_cidr = 0x288B0A60,
984 .name = "at91sam3s8a",
985 .total_flash_size = 256 * 2048,
986 .total_sram_size = 64 * 1024,
996 .base_address = FLASH_BANK_BASE_S,
997 .controller_address = 0x400e0a00,
998 .flash_wait_states = 6, /* workaround silicon bug */
1000 .size_bytes = 256 * 2048,
1002 .sector_size = 32768,
1015 .chipid_cidr = 0x289B0A60,
1016 .name = "at91sam3s8b",
1017 .total_flash_size = 256 * 2048,
1018 .total_sram_size = 64 * 1024,
1028 .base_address = FLASH_BANK_BASE_S,
1029 .controller_address = 0x400e0a00,
1030 .flash_wait_states = 6, /* workaround silicon bug */
1032 .size_bytes = 256 * 2048,
1034 .sector_size = 32768,
1047 .chipid_cidr = 0x28AB0A60,
1048 .name = "at91sam3s8c",
1049 .total_flash_size = 256 * 2048,
1050 .total_sram_size = 64 * 1024,
1060 .base_address = FLASH_BANK_BASE_S,
1061 .controller_address = 0x400e0a00,
1062 .flash_wait_states = 6, /* workaround silicon bug */
1064 .size_bytes = 256 * 2048,
1066 .sector_size = 32768,
1079 /* Start at91sam3n* series */
1081 .chipid_cidr = 0x29540960,
1082 .name = "at91sam3n4c",
1083 .total_flash_size = 256 * 1024,
1084 .total_sram_size = 24 * 1024,
1088 /* System boots at address 0x0 */
1089 /* gpnvm[1] = selects boot code */
1090 /* if gpnvm[1] == 0 */
1091 /* boot is via "SAMBA" (rom) */
1093 /* boot is via FLASH */
1094 /* Selection is via gpnvm[2] */
1097 /* NOTE: banks 0 & 1 switch places */
1098 /* if gpnvm[2] == 0 */
1099 /* Bank0 is the boot rom */
1101 /* Bank1 is the boot rom */
1110 .base_address = FLASH_BANK_BASE_N,
1111 .controller_address = 0x400e0A00,
1112 .flash_wait_states = 6, /* workaround silicon bug */
1114 .size_bytes = 256 * 1024,
1116 .sector_size = 16384,
1130 .chipid_cidr = 0x29440960,
1131 .name = "at91sam3n4b",
1132 .total_flash_size = 256 * 1024,
1133 .total_sram_size = 24 * 1024,
1137 /* System boots at address 0x0 */
1138 /* gpnvm[1] = selects boot code */
1139 /* if gpnvm[1] == 0 */
1140 /* boot is via "SAMBA" (rom) */
1142 /* boot is via FLASH */
1143 /* Selection is via gpnvm[2] */
1146 /* NOTE: banks 0 & 1 switch places */
1147 /* if gpnvm[2] == 0 */
1148 /* Bank0 is the boot rom */
1150 /* Bank1 is the boot rom */
1159 .base_address = FLASH_BANK_BASE_N,
1160 .controller_address = 0x400e0A00,
1161 .flash_wait_states = 6, /* workaround silicon bug */
1163 .size_bytes = 256 * 1024,
1165 .sector_size = 16384,
1179 .chipid_cidr = 0x29340960,
1180 .name = "at91sam3n4a",
1181 .total_flash_size = 256 * 1024,
1182 .total_sram_size = 24 * 1024,
1186 /* System boots at address 0x0 */
1187 /* gpnvm[1] = selects boot code */
1188 /* if gpnvm[1] == 0 */
1189 /* boot is via "SAMBA" (rom) */
1191 /* boot is via FLASH */
1192 /* Selection is via gpnvm[2] */
1195 /* NOTE: banks 0 & 1 switch places */
1196 /* if gpnvm[2] == 0 */
1197 /* Bank0 is the boot rom */
1199 /* Bank1 is the boot rom */
1208 .base_address = FLASH_BANK_BASE_N,
1209 .controller_address = 0x400e0A00,
1210 .flash_wait_states = 6, /* workaround silicon bug */
1212 .size_bytes = 256 * 1024,
1214 .sector_size = 16384,
1228 .chipid_cidr = 0x29590760,
1229 .name = "at91sam3n2c",
1230 .total_flash_size = 128 * 1024,
1231 .total_sram_size = 16 * 1024,
1235 /* System boots at address 0x0 */
1236 /* gpnvm[1] = selects boot code */
1237 /* if gpnvm[1] == 0 */
1238 /* boot is via "SAMBA" (rom) */
1240 /* boot is via FLASH */
1241 /* Selection is via gpnvm[2] */
1244 /* NOTE: banks 0 & 1 switch places */
1245 /* if gpnvm[2] == 0 */
1246 /* Bank0 is the boot rom */
1248 /* Bank1 is the boot rom */
1257 .base_address = FLASH_BANK_BASE_N,
1258 .controller_address = 0x400e0A00,
1259 .flash_wait_states = 6, /* workaround silicon bug */
1261 .size_bytes = 128 * 1024,
1263 .sector_size = 16384,
1277 .chipid_cidr = 0x29490760,
1278 .name = "at91sam3n2b",
1279 .total_flash_size = 128 * 1024,
1280 .total_sram_size = 16 * 1024,
1284 /* System boots at address 0x0 */
1285 /* gpnvm[1] = selects boot code */
1286 /* if gpnvm[1] == 0 */
1287 /* boot is via "SAMBA" (rom) */
1289 /* boot is via FLASH */
1290 /* Selection is via gpnvm[2] */
1293 /* NOTE: banks 0 & 1 switch places */
1294 /* if gpnvm[2] == 0 */
1295 /* Bank0 is the boot rom */
1297 /* Bank1 is the boot rom */
1306 .base_address = FLASH_BANK_BASE_N,
1307 .controller_address = 0x400e0A00,
1308 .flash_wait_states = 6, /* workaround silicon bug */
1310 .size_bytes = 128 * 1024,
1312 .sector_size = 16384,
1326 .chipid_cidr = 0x29390760,
1327 .name = "at91sam3n2a",
1328 .total_flash_size = 128 * 1024,
1329 .total_sram_size = 16 * 1024,
1333 /* System boots at address 0x0 */
1334 /* gpnvm[1] = selects boot code */
1335 /* if gpnvm[1] == 0 */
1336 /* boot is via "SAMBA" (rom) */
1338 /* boot is via FLASH */
1339 /* Selection is via gpnvm[2] */
1342 /* NOTE: banks 0 & 1 switch places */
1343 /* if gpnvm[2] == 0 */
1344 /* Bank0 is the boot rom */
1346 /* Bank1 is the boot rom */
1355 .base_address = FLASH_BANK_BASE_N,
1356 .controller_address = 0x400e0A00,
1357 .flash_wait_states = 6, /* workaround silicon bug */
1359 .size_bytes = 128 * 1024,
1361 .sector_size = 16384,
1375 .chipid_cidr = 0x29580560,
1376 .name = "at91sam3n1c",
1377 .total_flash_size = 64 * 1024,
1378 .total_sram_size = 8 * 1024,
1382 /* System boots at address 0x0 */
1383 /* gpnvm[1] = selects boot code */
1384 /* if gpnvm[1] == 0 */
1385 /* boot is via "SAMBA" (rom) */
1387 /* boot is via FLASH */
1388 /* Selection is via gpnvm[2] */
1391 /* NOTE: banks 0 & 1 switch places */
1392 /* if gpnvm[2] == 0 */
1393 /* Bank0 is the boot rom */
1395 /* Bank1 is the boot rom */
1404 .base_address = FLASH_BANK_BASE_N,
1405 .controller_address = 0x400e0A00,
1406 .flash_wait_states = 6, /* workaround silicon bug */
1408 .size_bytes = 64 * 1024,
1410 .sector_size = 16384,
1424 .chipid_cidr = 0x29480560,
1425 .name = "at91sam3n1b",
1426 .total_flash_size = 64 * 1024,
1427 .total_sram_size = 8 * 1024,
1431 /* System boots at address 0x0 */
1432 /* gpnvm[1] = selects boot code */
1433 /* if gpnvm[1] == 0 */
1434 /* boot is via "SAMBA" (rom) */
1436 /* boot is via FLASH */
1437 /* Selection is via gpnvm[2] */
1440 /* NOTE: banks 0 & 1 switch places */
1441 /* if gpnvm[2] == 0 */
1442 /* Bank0 is the boot rom */
1444 /* Bank1 is the boot rom */
1453 .base_address = FLASH_BANK_BASE_N,
1454 .controller_address = 0x400e0A00,
1455 .flash_wait_states = 6, /* workaround silicon bug */
1457 .size_bytes = 64 * 1024,
1459 .sector_size = 16384,
1473 .chipid_cidr = 0x29380560,
1474 .name = "at91sam3n1a",
1475 .total_flash_size = 64 * 1024,
1476 .total_sram_size = 8 * 1024,
1480 /* System boots at address 0x0 */
1481 /* gpnvm[1] = selects boot code */
1482 /* if gpnvm[1] == 0 */
1483 /* boot is via "SAMBA" (rom) */
1485 /* boot is via FLASH */
1486 /* Selection is via gpnvm[2] */
1489 /* NOTE: banks 0 & 1 switch places */
1490 /* if gpnvm[2] == 0 */
1491 /* Bank0 is the boot rom */
1493 /* Bank1 is the boot rom */
1502 .base_address = FLASH_BANK_BASE_N,
1503 .controller_address = 0x400e0A00,
1504 .flash_wait_states = 6, /* workaround silicon bug */
1506 .size_bytes = 64 * 1024,
1508 .sector_size = 16384,
1522 .chipid_cidr = 0x29480360,
1523 .name = "at91sam3n0b",
1524 .total_flash_size = 32 * 1024,
1525 .total_sram_size = 8 * 1024,
1536 .base_address = FLASH_BANK_BASE_N,
1537 .controller_address = 0x400e0A00,
1538 .flash_wait_states = 6, /* workaround silicon bug */
1540 .size_bytes = 32 * 1024,
1542 .sector_size = 16384,
1556 .chipid_cidr = 0x29380360,
1557 .name = "at91sam3n0a",
1558 .total_flash_size = 32 * 1024,
1559 .total_sram_size = 8 * 1024,
1570 .base_address = FLASH_BANK_BASE_N,
1571 .controller_address = 0x400e0A00,
1572 .flash_wait_states = 6, /* workaround silicon bug */
1574 .size_bytes = 32 * 1024,
1576 .sector_size = 16384,
1590 .chipid_cidr = 0x29450260,
1591 .name = "at91sam3n00b",
1592 .total_flash_size = 16 * 1024,
1593 .total_sram_size = 4 * 1024,
1604 .base_address = FLASH_BANK_BASE_N,
1605 .controller_address = 0x400e0A00,
1606 .flash_wait_states = 6, /* workaround silicon bug */
1608 .size_bytes = 16 * 1024,
1610 .sector_size = 16384,
1624 .chipid_cidr = 0x29350260,
1625 .name = "at91sam3n00a",
1626 .total_flash_size = 16 * 1024,
1627 .total_sram_size = 4 * 1024,
1638 .base_address = FLASH_BANK_BASE_N,
1639 .controller_address = 0x400e0A00,
1640 .flash_wait_states = 6, /* workaround silicon bug */
1642 .size_bytes = 16 * 1024,
1644 .sector_size = 16384,
1658 /* Start at91sam3a series*/
1659 /* System boots at address 0x0 */
1660 /* gpnvm[1] = selects boot code */
1661 /* if gpnvm[1] == 0 */
1662 /* boot is via "SAMBA" (rom) */
1664 /* boot is via FLASH */
1665 /* Selection is via gpnvm[2] */
1668 /* NOTE: banks 0 & 1 switch places */
1669 /* if gpnvm[2] == 0 */
1670 /* Bank0 is the boot rom */
1672 /* Bank1 is the boot rom */
1676 .chipid_cidr = 0x283E0A60,
1677 .name = "at91sam3a8c",
1678 .total_flash_size = 512 * 1024,
1679 .total_sram_size = 96 * 1024,
1689 .base_address = FLASH_BANK0_BASE_AX,
1690 .controller_address = 0x400e0a00,
1691 .flash_wait_states = 6, /* workaround silicon bug */
1693 .size_bytes = 256 * 1024,
1695 .sector_size = 16384,
1704 .base_address = FLASH_BANK1_BASE_512K_AX,
1705 .controller_address = 0x400e0c00,
1706 .flash_wait_states = 6, /* workaround silicon bug */
1708 .size_bytes = 256 * 1024,
1710 .sector_size = 16384,
1717 .chipid_cidr = 0x283B0960,
1718 .name = "at91sam3a4c",
1719 .total_flash_size = 256 * 1024,
1720 .total_sram_size = 64 * 1024,
1730 .base_address = FLASH_BANK0_BASE_AX,
1731 .controller_address = 0x400e0a00,
1732 .flash_wait_states = 6, /* workaround silicon bug */
1734 .size_bytes = 128 * 1024,
1736 .sector_size = 16384,
1745 .base_address = FLASH_BANK1_BASE_256K_AX,
1746 .controller_address = 0x400e0c00,
1747 .flash_wait_states = 6, /* workaround silicon bug */
1749 .size_bytes = 128 * 1024,
1751 .sector_size = 16384,
1758 /* Start at91sam3x* series */
1759 /* System boots at address 0x0 */
1760 /* gpnvm[1] = selects boot code */
1761 /* if gpnvm[1] == 0 */
1762 /* boot is via "SAMBA" (rom) */
1764 /* boot is via FLASH */
1765 /* Selection is via gpnvm[2] */
1768 /* NOTE: banks 0 & 1 switch places */
1769 /* if gpnvm[2] == 0 */
1770 /* Bank0 is the boot rom */
1772 /* Bank1 is the boot rom */
1774 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1776 .chipid_cidr = 0x286E0A20,
1777 .name = "at91sam3x8h - ES",
1778 .total_flash_size = 512 * 1024,
1779 .total_sram_size = 96 * 1024,
1789 .base_address = FLASH_BANK0_BASE_AX,
1790 .controller_address = 0x400e0a00,
1791 .flash_wait_states = 6, /* workaround silicon bug */
1793 .size_bytes = 256 * 1024,
1795 .sector_size = 16384,
1804 .base_address = FLASH_BANK1_BASE_512K_AX,
1805 .controller_address = 0x400e0c00,
1806 .flash_wait_states = 6, /* workaround silicon bug */
1808 .size_bytes = 256 * 1024,
1810 .sector_size = 16384,
1816 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1818 .chipid_cidr = 0x286E0A60,
1819 .name = "at91sam3x8h",
1820 .total_flash_size = 512 * 1024,
1821 .total_sram_size = 96 * 1024,
1831 .base_address = FLASH_BANK0_BASE_AX,
1832 .controller_address = 0x400e0a00,
1833 .flash_wait_states = 6, /* workaround silicon bug */
1835 .size_bytes = 256 * 1024,
1837 .sector_size = 16384,
1846 .base_address = FLASH_BANK1_BASE_512K_AX,
1847 .controller_address = 0x400e0c00,
1848 .flash_wait_states = 6, /* workaround silicon bug */
1850 .size_bytes = 256 * 1024,
1852 .sector_size = 16384,
1859 .chipid_cidr = 0x285E0A60,
1860 .name = "at91sam3x8e",
1861 .total_flash_size = 512 * 1024,
1862 .total_sram_size = 96 * 1024,
1872 .base_address = FLASH_BANK0_BASE_AX,
1873 .controller_address = 0x400e0a00,
1874 .flash_wait_states = 6, /* workaround silicon bug */
1876 .size_bytes = 256 * 1024,
1878 .sector_size = 16384,
1887 .base_address = FLASH_BANK1_BASE_512K_AX,
1888 .controller_address = 0x400e0c00,
1889 .flash_wait_states = 6, /* workaround silicon bug */
1891 .size_bytes = 256 * 1024,
1893 .sector_size = 16384,
1900 .chipid_cidr = 0x284E0A60,
1901 .name = "at91sam3x8c",
1902 .total_flash_size = 512 * 1024,
1903 .total_sram_size = 96 * 1024,
1913 .base_address = FLASH_BANK0_BASE_AX,
1914 .controller_address = 0x400e0a00,
1915 .flash_wait_states = 6, /* workaround silicon bug */
1917 .size_bytes = 256 * 1024,
1919 .sector_size = 16384,
1928 .base_address = FLASH_BANK1_BASE_512K_AX ,
1929 .controller_address = 0x400e0c00,
1930 .flash_wait_states = 6, /* workaround silicon bug */
1932 .size_bytes = 256 * 1024,
1934 .sector_size = 16384,
1941 .chipid_cidr = 0x285B0960,
1942 .name = "at91sam3x4e",
1943 .total_flash_size = 256 * 1024,
1944 .total_sram_size = 64 * 1024,
1954 .base_address = FLASH_BANK0_BASE_AX,
1955 .controller_address = 0x400e0a00,
1956 .flash_wait_states = 6, /* workaround silicon bug */
1958 .size_bytes = 128 * 1024,
1960 .sector_size = 16384,
1969 .base_address = FLASH_BANK1_BASE_256K_AX,
1970 .controller_address = 0x400e0c00,
1971 .flash_wait_states = 6, /* workaround silicon bug */
1973 .size_bytes = 128 * 1024,
1975 .sector_size = 16384,
1982 .chipid_cidr = 0x284B0960,
1983 .name = "at91sam3x4c",
1984 .total_flash_size = 256 * 1024,
1985 .total_sram_size = 64 * 1024,
1995 .base_address = FLASH_BANK0_BASE_AX,
1996 .controller_address = 0x400e0a00,
1997 .flash_wait_states = 6, /* workaround silicon bug */
1999 .size_bytes = 128 * 1024,
2001 .sector_size = 16384,
2010 .base_address = FLASH_BANK1_BASE_256K_AX,
2011 .controller_address = 0x400e0c00,
2012 .flash_wait_states = 6, /* workaround silicon bug */
2014 .size_bytes = 128 * 1024,
2016 .sector_size = 16384,
2030 /***********************************************************************
2031 **********************************************************************
2032 **********************************************************************
2033 **********************************************************************
2034 **********************************************************************
2035 **********************************************************************/
2036 /* *ATMEL* style code - from the SAM3 driver code */
2039 * Get the current status of the EEFC and
2040 * the value of some status bits (LOCKE, PROGE).
2041 * @param pPrivate - info about the bank
2042 * @param v - result goes here
2044 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
2047 r = target_read_u32(pPrivate->pChip->target,
2048 pPrivate->controller_address + offset_EFC_FSR,
2050 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2052 ((unsigned int)((*v >> 2) & 1)),
2053 ((unsigned int)((*v >> 1) & 1)),
2054 ((unsigned int)((*v >> 0) & 1)));
2060 * Get the result of the last executed command.
2061 * @param pPrivate - info about the bank
2062 * @param v - result goes here
2064 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
2068 r = target_read_u32(pPrivate->pChip->target,
2069 pPrivate->controller_address + offset_EFC_FRR,
2073 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2077 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
2078 unsigned command, unsigned argument)
2087 /* Check command & argument */
2090 case AT91C_EFC_FCMD_WP:
2091 case AT91C_EFC_FCMD_WPL:
2092 case AT91C_EFC_FCMD_EWP:
2093 case AT91C_EFC_FCMD_EWPL:
2094 /* case AT91C_EFC_FCMD_EPL: */
2095 /* case AT91C_EFC_FCMD_EPA: */
2096 case AT91C_EFC_FCMD_SLB:
2097 case AT91C_EFC_FCMD_CLB:
2098 n = (pPrivate->size_bytes / pPrivate->page_size);
2100 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
2103 case AT91C_EFC_FCMD_SFB:
2104 case AT91C_EFC_FCMD_CFB:
2105 if (argument >= pPrivate->pChip->details.n_gpnvms) {
2106 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2107 pPrivate->pChip->details.n_gpnvms);
2111 case AT91C_EFC_FCMD_GETD:
2112 case AT91C_EFC_FCMD_EA:
2113 case AT91C_EFC_FCMD_GLB:
2114 case AT91C_EFC_FCMD_GFB:
2115 case AT91C_EFC_FCMD_STUI:
2116 case AT91C_EFC_FCMD_SPUI:
2118 LOG_ERROR("Argument is meaningless for cmd: %d", command);
2121 LOG_ERROR("Unknown command %d", command);
2125 if (command == AT91C_EFC_FCMD_SPUI) {
2126 /* this is a very special situation. */
2127 /* Situation (1) - error/retry - see below */
2128 /* And we are being called recursively */
2129 /* Situation (2) - normal, finished reading unique id */
2131 /* it should be "ready" */
2132 EFC_GetStatus(pPrivate, &v);
2134 /* then it is ready */
2138 /* we have done this before */
2139 /* the controller is not responding. */
2140 LOG_ERROR("flash controller(%d) is not ready! Error",
2141 pPrivate->bank_number);
2145 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2146 pPrivate->bank_number);
2147 /* we do that by issuing the *STOP* command */
2148 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
2149 /* above is recursive, and further recursion is blocked by */
2150 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2156 v = (0x5A << 24) | (argument << 8) | command;
2157 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2158 r = target_write_u32(pPrivate->pBank->target,
2159 pPrivate->controller_address + offset_EFC_FCR, v);
2161 LOG_DEBUG("Error Write failed");
2166 * Performs the given command and wait until its completion (or an error).
2167 * @param pPrivate - info about the bank
2168 * @param command - Command to perform.
2169 * @param argument - Optional command argument.
2170 * @param status - put command status bits here
2172 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
2180 long long ms_now, ms_end;
2186 r = EFC_StartCommand(pPrivate, command, argument);
2190 ms_end = 500 + timeval_ms();
2193 r = EFC_GetStatus(pPrivate, &v);
2196 ms_now = timeval_ms();
2197 if (ms_now > ms_end) {
2199 LOG_ERROR("Command timeout");
2202 } while ((v & 1) == 0);
2206 *status = (v & 0x6);
2212 * Read the unique ID.
2213 * @param pPrivate - info about the bank
2214 * The unique ID is stored in the 'pPrivate' structure.
2216 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
2222 pPrivate->pChip->cfg.unique_id[0] = 0;
2223 pPrivate->pChip->cfg.unique_id[1] = 0;
2224 pPrivate->pChip->cfg.unique_id[2] = 0;
2225 pPrivate->pChip->cfg.unique_id[3] = 0;
2228 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
2232 for (x = 0; x < 4; x++) {
2233 r = target_read_u32(pPrivate->pChip->target,
2234 pPrivate->pBank->base + (x * 4),
2238 pPrivate->pChip->cfg.unique_id[x] = v;
2241 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
2242 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2244 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
2245 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
2246 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
2247 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
2253 * Erases the entire flash.
2254 * @param pPrivate - the info about the bank.
2256 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
2259 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
2263 * Gets current GPNVM state.
2264 * @param pPrivate - info about the bank.
2265 * @param gpnvm - GPNVM bit index.
2266 * @param puthere - result stored here.
2268 /* ------------------------------------------------------------------------------ */
2269 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
2275 if (pPrivate->bank_number != 0) {
2276 LOG_ERROR("GPNVM only works with Bank0");
2280 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2281 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2282 gpnvm, pPrivate->pChip->details.n_gpnvms);
2286 /* Get GPNVMs status */
2287 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
2288 if (r != ERROR_OK) {
2289 LOG_ERROR("Failed");
2293 r = EFC_GetResult(pPrivate, &v);
2296 /* Check if GPNVM is set */
2297 /* get the bit and make it a 0/1 */
2298 *puthere = (v >> gpnvm) & 1;
2305 * Clears the selected GPNVM bit.
2306 * @param pPrivate info about the bank
2307 * @param gpnvm GPNVM index.
2308 * @returns 0 if successful; otherwise returns an error code.
2310 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2316 if (pPrivate->bank_number != 0) {
2317 LOG_ERROR("GPNVM only works with Bank0");
2321 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2322 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2323 gpnvm, pPrivate->pChip->details.n_gpnvms);
2327 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2328 if (r != ERROR_OK) {
2329 LOG_DEBUG("Failed: %d", r);
2332 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2333 LOG_DEBUG("End: %d", r);
2338 * Sets the selected GPNVM bit.
2339 * @param pPrivate info about the bank
2340 * @param gpnvm GPNVM index.
2342 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2347 if (pPrivate->bank_number != 0) {
2348 LOG_ERROR("GPNVM only works with Bank0");
2352 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2353 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2354 gpnvm, pPrivate->pChip->details.n_gpnvms);
2358 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2366 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2372 * Returns a bit field (at most 64) of locked regions within a page.
2373 * @param pPrivate info about the bank
2374 * @param v where to store locked bits
2376 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2380 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2382 r = EFC_GetResult(pPrivate, v);
2383 LOG_DEBUG("End: %d", r);
2388 * Unlocks all the regions in the given address range.
2389 * @param pPrivate info about the bank
2390 * @param start_sector first sector to unlock
2391 * @param end_sector last (inclusive) to unlock
2394 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2395 unsigned start_sector,
2396 unsigned end_sector)
2401 uint32_t pages_per_sector;
2403 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2405 /* Unlock all pages */
2406 while (start_sector <= end_sector) {
2407 pg = start_sector * pages_per_sector;
2409 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2420 * @param pPrivate - info about the bank
2421 * @param start_sector - first sector to lock
2422 * @param end_sector - last sector (inclusive) to lock
2424 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2425 unsigned start_sector,
2426 unsigned end_sector)
2430 uint32_t pages_per_sector;
2433 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2435 /* Lock all pages */
2436 while (start_sector <= end_sector) {
2437 pg = start_sector * pages_per_sector;
2439 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2447 /****** END SAM3 CODE ********/
2449 /* begin helpful debug code */
2450 /* print the fieldname, the field value, in dec & hex, and return field value */
2451 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2452 const char *regname,
2461 /* extract the field */
2463 v = v & ((1 << width)-1);
2472 /* show the basics */
2473 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2474 REG_NAME_WIDTH, regname,
2480 static const char _unknown[] = "unknown";
2481 static const char *const eproc_names[] = {
2485 "cortex-m3", /* 3 */
2487 "arm926ejs", /* 5 */
2500 #define nvpsize2 nvpsize /* these two tables are identical */
2501 static const char *const nvpsize[] = {
2504 "16K bytes", /* 2 */
2505 "32K bytes", /* 3 */
2507 "64K bytes", /* 5 */
2509 "128K bytes", /* 7 */
2511 "256K bytes", /* 9 */
2512 "512K bytes", /* 10 */
2514 "1024K bytes", /* 12 */
2516 "2048K bytes", /* 14 */
2520 static const char *const sramsize[] = {
2521 "48K Bytes", /* 0 */
2525 "112K Bytes", /* 4 */
2527 "80K Bytes", /* 6 */
2528 "160K Bytes", /* 7 */
2530 "16K Bytes", /* 9 */
2531 "32K Bytes", /* 10 */
2532 "64K Bytes", /* 11 */
2533 "128K Bytes", /* 12 */
2534 "256K Bytes", /* 13 */
2535 "96K Bytes", /* 14 */
2536 "512K Bytes", /* 15 */
2540 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2541 { 0x19, "AT91SAM9xx Series" },
2542 { 0x29, "AT91SAM9XExx Series" },
2543 { 0x34, "AT91x34 Series" },
2544 { 0x37, "CAP7 Series" },
2545 { 0x39, "CAP9 Series" },
2546 { 0x3B, "CAP11 Series" },
2547 { 0x40, "AT91x40 Series" },
2548 { 0x42, "AT91x42 Series" },
2549 { 0x55, "AT91x55 Series" },
2550 { 0x60, "AT91SAM7Axx Series" },
2551 { 0x61, "AT91SAM7AQxx Series" },
2552 { 0x63, "AT91x63 Series" },
2553 { 0x70, "AT91SAM7Sxx Series" },
2554 { 0x71, "AT91SAM7XCxx Series" },
2555 { 0x72, "AT91SAM7SExx Series" },
2556 { 0x73, "AT91SAM7Lxx Series" },
2557 { 0x75, "AT91SAM7Xxx Series" },
2558 { 0x76, "AT91SAM7SLxx Series" },
2559 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2560 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2561 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2562 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2563 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2564 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2565 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2566 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2567 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2568 { 0x92, "AT91x92 Series" },
2569 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2570 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2571 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2572 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2573 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2574 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2575 { 0xA5, "ATSAM5A" },
2576 { 0xF0, "AT75Cxx Series" },
2580 static const char *const nvptype[] = {
2582 "romless or onchip flash", /* 1 */
2583 "embedded flash memory",/* 2 */
2584 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2585 "sram emulating flash", /* 4 */
2591 static const char *_yes_or_no(uint32_t v)
2599 static const char *const _rc_freq[] = {
2600 "4 MHz", "8 MHz", "12 MHz", "reserved"
2603 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2608 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2609 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2610 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2611 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2612 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2613 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2614 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2615 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2617 pChip->cfg.rc_freq = 0;
2621 pChip->cfg.rc_freq = 0;
2624 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2627 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2630 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2635 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2636 LOG_USER("(startup clks, time= %f uSecs)",
2637 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2638 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2639 LOG_USER("(mainosc source: %s)",
2640 v ? "external xtal" : "internal RC");
2642 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2643 LOG_USER("(clock failure enabled: %s)",
2647 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2653 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2656 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2657 LOG_USER("%s", eproc_names[v]);
2659 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2660 LOG_USER("%s", nvpsize[v]);
2662 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2663 LOG_USER("%s", nvpsize2[v]);
2665 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2666 LOG_USER("%s", sramsize[v]);
2668 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2670 for (x = 0; archnames[x].name; x++) {
2671 if (v == archnames[x].value) {
2672 cp = archnames[x].name;
2679 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2680 LOG_USER("%s", nvptype[v]);
2682 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2683 LOG_USER("(exists: %s)", _yes_or_no(v));
2686 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2690 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2691 LOG_USER("(main ready: %s)", _yes_or_no(v));
2693 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2695 v = (v * pChip->cfg.slow_freq) / 16;
2696 pChip->cfg.mainosc_freq = v;
2698 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2700 (uint32_t)(pChip->cfg.slow_freq / 1000),
2701 (uint32_t)(pChip->cfg.slow_freq % 1000));
2704 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2706 uint32_t mula, diva;
2708 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2710 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2712 pChip->cfg.plla_freq = 0;
2714 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2716 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2717 else if (diva >= 1) {
2718 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2719 LOG_USER("\tPLLA Freq: %3.03f MHz",
2720 _tomhz(pChip->cfg.plla_freq));
2724 static void sam3_explain_mckr(struct sam3_chip *pChip)
2726 uint32_t css, pres, fin = 0;
2728 const char *cp = NULL;
2730 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2733 fin = pChip->cfg.slow_freq;
2737 fin = pChip->cfg.mainosc_freq;
2741 fin = pChip->cfg.plla_freq;
2745 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2746 fin = 480 * 1000 * 1000;
2750 cp = "upll (*ERROR* UPLL is disabled)";
2758 LOG_USER("%s (%3.03f Mhz)",
2761 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2762 switch (pres & 0x07) {
2765 cp = "selected clock";
2799 LOG_USER("(%s)", cp);
2801 /* sam3 has a *SINGLE* clock - */
2802 /* other at91 series parts have divisors for these. */
2803 pChip->cfg.cpu_freq = fin;
2804 pChip->cfg.mclk_freq = fin;
2805 pChip->cfg.fclk_freq = fin;
2806 LOG_USER("\t\tResult CPU Freq: %3.03f",
2811 static struct sam3_chip *target2sam3(struct target *pTarget)
2813 struct sam3_chip *pChip;
2815 if (pTarget == NULL)
2818 pChip = all_sam3_chips;
2820 if (pChip->target == pTarget)
2821 break; /* return below */
2823 pChip = pChip->next;
2829 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2831 /* this function exists to help */
2832 /* keep funky offsetof() errors */
2833 /* and casting from causing bugs */
2835 /* By using prototypes - we can detect what would */
2836 /* be casting errors. */
2838 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2842 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2844 NAME), # NAME, FUNC }
2845 static const struct sam3_reg_list sam3_all_regs[] = {
2846 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2847 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2848 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2849 SAM3_ENTRY(CKGR_UCKR, NULL),
2850 SAM3_ENTRY(PMC_FSMR, NULL),
2851 SAM3_ENTRY(PMC_FSPR, NULL),
2852 SAM3_ENTRY(PMC_IMR, NULL),
2853 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2854 SAM3_ENTRY(PMC_PCK0, NULL),
2855 SAM3_ENTRY(PMC_PCK1, NULL),
2856 SAM3_ENTRY(PMC_PCK2, NULL),
2857 SAM3_ENTRY(PMC_PCSR, NULL),
2858 SAM3_ENTRY(PMC_SCSR, NULL),
2859 SAM3_ENTRY(PMC_SR, NULL),
2860 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2861 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2862 SAM3_ENTRY(CHIPID_EXID, NULL),
2863 SAM3_ENTRY(CHIPID_EXID2, NULL),
2864 /* TERMINATE THE LIST */
2869 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2871 return bank->driver_priv;
2875 * Given a pointer to where it goes in the structure,
2876 * determine the register name, address from the all registers table.
2878 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2880 const struct sam3_reg_list *pReg;
2882 pReg = &(sam3_all_regs[0]);
2883 while (pReg->name) {
2884 uint32_t *pPossible;
2886 /* calculate where this one go.. */
2887 /* it is "possibly" this register. */
2889 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2891 /* well? Is it this register */
2892 if (pPossible == goes_here) {
2900 /* This is *TOTAL*PANIC* - we are totally screwed. */
2901 LOG_ERROR("INVALID SAM3 REGISTER");
2905 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2907 const struct sam3_reg_list *pReg;
2910 pReg = sam3_GetReg(pChip, goes_here);
2914 r = target_read_u32(pChip->target, pReg->address, goes_here);
2915 if (r != ERROR_OK) {
2916 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2917 pReg->name, (unsigned)(pReg->address), r);
2922 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2925 const struct sam3_reg_list *pReg;
2927 pReg = &(sam3_all_regs[0]);
2928 while (pReg->name) {
2929 r = sam3_ReadThisReg(pChip,
2930 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2931 if (r != ERROR_OK) {
2932 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2933 pReg->name, ((unsigned)(pReg->address)), r);
2939 /* Chip identification register
2941 * Unfortunately, the chip identification register is not at
2942 * a constant address across all of the SAM3 series'. As a
2943 * consequence, a simple heuristic is used to find where it's
2946 * If the contents at the first address is zero, then we know
2947 * that the second address is where the chip id register is.
2948 * We can deduce this because for those SAM's that have the
2949 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2950 * located in the memory map of the Power Management Controller
2951 * (PMC). Furthermore, the address is not used by the PMC.
2952 * So when read, the memory controller returns zero.*/
2953 if (pChip->cfg.CHIPID_CIDR == 0) {
2954 /*Put the correct CIDR and EXID values in the pChip structure */
2955 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2956 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2961 static int sam3_GetInfo(struct sam3_chip *pChip)
2963 const struct sam3_reg_list *pReg;
2966 pReg = &(sam3_all_regs[0]);
2967 while (pReg->name) {
2968 /* display all regs */
2969 LOG_DEBUG("Start: %s", pReg->name);
2970 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2971 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2976 if (pReg->explain_func)
2977 (*(pReg->explain_func))(pChip);
2978 LOG_DEBUG("End: %s", pReg->name);
2981 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2982 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2983 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2984 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2985 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2987 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2988 pChip->cfg.unique_id[0],
2989 pChip->cfg.unique_id[1],
2990 pChip->cfg.unique_id[2],
2991 pChip->cfg.unique_id[3]);
2996 static int sam3_erase_check(struct flash_bank *bank)
3001 if (bank->target->state != TARGET_HALTED) {
3002 LOG_ERROR("Target not halted");
3003 return ERROR_TARGET_NOT_HALTED;
3005 if (0 == bank->num_sectors) {
3006 LOG_ERROR("Target: not supported/not probed");
3010 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
3011 for (x = 0; x < bank->num_sectors; x++)
3012 bank->sectors[x].is_erased = 1;
3018 static int sam3_protect_check(struct flash_bank *bank)
3023 struct sam3_bank_private *pPrivate;
3026 if (bank->target->state != TARGET_HALTED) {
3027 LOG_ERROR("Target not halted");
3028 return ERROR_TARGET_NOT_HALTED;
3031 pPrivate = get_sam3_bank_private(bank);
3033 LOG_ERROR("no private for this bank?");
3036 if (!(pPrivate->probed))
3037 return ERROR_FLASH_BANK_NOT_PROBED;
3039 r = FLASHD_GetLockBits(pPrivate, &v);
3040 if (r != ERROR_OK) {
3041 LOG_DEBUG("Failed: %d", r);
3045 for (x = 0; x < pPrivate->nsectors; x++)
3046 bank->sectors[x].is_protected = (!!(v & (1 << x)));
3051 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
3053 struct sam3_chip *pChip;
3055 pChip = all_sam3_chips;
3057 /* is this an existing chip? */
3059 if (pChip->target == bank->target)
3061 pChip = pChip->next;
3065 /* this is a *NEW* chip */
3066 pChip = calloc(1, sizeof(struct sam3_chip));
3068 LOG_ERROR("NO RAM!");
3071 pChip->target = bank->target;
3072 /* insert at head */
3073 pChip->next = all_sam3_chips;
3074 all_sam3_chips = pChip;
3075 pChip->target = bank->target;
3076 /* assumption is this runs at 32khz */
3077 pChip->cfg.slow_freq = 32768;
3081 switch (bank->base) {
3083 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3084 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3085 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3086 ((unsigned int)(bank->base)),
3087 ((unsigned int)(FLASH_BANK0_BASE_U)),
3088 ((unsigned int)(FLASH_BANK1_BASE_U)),
3089 ((unsigned int)(FLASH_BANK_BASE_S)),
3090 ((unsigned int)(FLASH_BANK_BASE_N)),
3091 ((unsigned int)(FLASH_BANK0_BASE_AX)),
3092 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
3093 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
3097 /* at91sam3s and at91sam3n series only has bank 0*/
3098 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3099 case FLASH_BANK_BASE_S:
3100 case FLASH_BANK0_BASE_U:
3101 bank->driver_priv = &(pChip->details.bank[0]);
3102 bank->bank_number = 0;
3103 pChip->details.bank[0].pChip = pChip;
3104 pChip->details.bank[0].pBank = bank;
3107 /* Bank 1 of at91sam3u or at91sam3ax series */
3108 case FLASH_BANK1_BASE_U:
3109 case FLASH_BANK1_BASE_256K_AX:
3110 case FLASH_BANK1_BASE_512K_AX:
3111 bank->driver_priv = &(pChip->details.bank[1]);
3112 bank->bank_number = 1;
3113 pChip->details.bank[1].pChip = pChip;
3114 pChip->details.bank[1].pBank = bank;
3118 /* we initialize after probing. */
3122 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
3124 const struct sam3_chip_details *pDetails;
3125 struct sam3_chip *pChip;
3126 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
3130 pDetails = all_sam3_details;
3131 while (pDetails->name) {
3132 /* Compare cidr without version bits */
3133 if (((pDetails->chipid_cidr ^ pPrivate->pChip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
3138 if (pDetails->name == NULL) {
3139 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3140 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
3141 /* Help the victim, print details about the chip */
3142 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
3143 pPrivate->pChip->cfg.CHIPID_CIDR);
3144 sam3_explain_chipid_cidr(pPrivate->pChip);
3148 /* DANGER: THERE ARE DRAGONS HERE */
3150 /* get our pChip - it is going */
3151 /* to be over-written shortly */
3152 pChip = pPrivate->pChip;
3154 /* Note that, in reality: */
3156 /* pPrivate = &(pChip->details.bank[0]) */
3157 /* or pPrivate = &(pChip->details.bank[1]) */
3160 /* save the "bank" pointers */
3161 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
3162 saved_banks[x] = pChip->details.bank[x].pBank;
3164 /* Overwrite the "details" structure. */
3165 memcpy(&(pPrivate->pChip->details),
3167 sizeof(pPrivate->pChip->details));
3169 /* now fix the ghosted pointers */
3170 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3171 pChip->details.bank[x].pChip = pChip;
3172 pChip->details.bank[x].pBank = saved_banks[x];
3175 /* update the *BANK*SIZE* */
3181 static int _sam3_probe(struct flash_bank *bank, int noise)
3185 struct sam3_bank_private *pPrivate;
3188 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
3189 if (bank->target->state != TARGET_HALTED) {
3190 LOG_ERROR("Target not halted");
3191 return ERROR_TARGET_NOT_HALTED;
3194 pPrivate = get_sam3_bank_private(bank);
3196 LOG_ERROR("Invalid/unknown bank number");
3200 r = sam3_ReadAllRegs(pPrivate->pChip);
3205 if (pPrivate->pChip->probed)
3206 r = sam3_GetInfo(pPrivate->pChip);
3208 r = sam3_GetDetails(pPrivate);
3212 /* update the flash bank size */
3213 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3214 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
3215 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
3220 if (bank->sectors == NULL) {
3221 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
3222 if (bank->sectors == NULL) {
3223 LOG_ERROR("No memory!");
3226 bank->num_sectors = pPrivate->nsectors;
3228 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
3229 bank->sectors[x].size = pPrivate->sector_size;
3230 bank->sectors[x].offset = x * (pPrivate->sector_size);
3231 /* mark as unknown */
3232 bank->sectors[x].is_erased = -1;
3233 bank->sectors[x].is_protected = -1;
3237 pPrivate->probed = 1;
3239 r = sam3_protect_check(bank);
3243 LOG_DEBUG("Bank = %d, nbanks = %d",
3244 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
3245 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
3246 /* read unique id, */
3247 /* it appears to be associated with the *last* flash bank. */
3248 FLASHD_ReadUniqueID(pPrivate);
3254 static int sam3_probe(struct flash_bank *bank)
3256 return _sam3_probe(bank, 1);
3259 static int sam3_auto_probe(struct flash_bank *bank)
3261 return _sam3_probe(bank, 0);
3264 static int sam3_erase(struct flash_bank *bank, int first, int last)
3266 struct sam3_bank_private *pPrivate;
3270 if (bank->target->state != TARGET_HALTED) {
3271 LOG_ERROR("Target not halted");
3272 return ERROR_TARGET_NOT_HALTED;
3275 r = sam3_auto_probe(bank);
3276 if (r != ERROR_OK) {
3277 LOG_DEBUG("Here,r=%d", r);
3281 pPrivate = get_sam3_bank_private(bank);
3282 if (!(pPrivate->probed))
3283 return ERROR_FLASH_BANK_NOT_PROBED;
3285 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
3288 return FLASHD_EraseEntireBank(pPrivate);
3290 LOG_INFO("sam3 auto-erases while programming (request ignored)");
3294 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
3296 struct sam3_bank_private *pPrivate;
3300 if (bank->target->state != TARGET_HALTED) {
3301 LOG_ERROR("Target not halted");
3302 return ERROR_TARGET_NOT_HALTED;
3305 pPrivate = get_sam3_bank_private(bank);
3306 if (!(pPrivate->probed))
3307 return ERROR_FLASH_BANK_NOT_PROBED;
3310 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
3312 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
3313 LOG_DEBUG("End: r=%d", r);
3319 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3324 adr = pagenum * pPrivate->page_size;
3325 adr += pPrivate->base_address;
3327 r = target_read_memory(pPrivate->pChip->target,
3329 4, /* THIS*MUST*BE* in 32bit values */
3330 pPrivate->page_size / 4,
3333 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3334 (unsigned int)(adr));
3338 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
3342 uint32_t fmr; /* EEFC Flash Mode Register */
3345 adr = pagenum * pPrivate->page_size;
3346 adr += pPrivate->base_address;
3348 /* Get flash mode register value */
3349 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3351 LOG_DEBUG("Error Read failed: read flash mode register");
3353 /* Clear flash wait state field */
3356 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3357 fmr |= (pPrivate->flash_wait_states << 8);
3359 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3360 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3362 LOG_DEBUG("Error Write failed: set flash mode register");
3364 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3365 r = target_write_memory(pPrivate->pChip->target,
3367 4, /* THIS*MUST*BE* in 32bit values */
3368 pPrivate->page_size / 4,
3370 if (r != ERROR_OK) {
3371 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3372 (unsigned int)(adr));
3376 r = EFC_PerformCommand(pPrivate,
3377 /* send Erase & Write Page */
3383 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3384 (unsigned int)(adr));
3385 if (status & (1 << 2)) {
3386 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3389 if (status & (1 << 1)) {
3390 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3396 static int sam3_write(struct flash_bank *bank,
3397 const uint8_t *buffer,
3405 unsigned page_offset;
3406 struct sam3_bank_private *pPrivate;
3407 uint8_t *pagebuffer;
3409 /* incase we bail further below, set this to null */
3412 /* ignore dumb requests */
3418 if (bank->target->state != TARGET_HALTED) {
3419 LOG_ERROR("Target not halted");
3420 r = ERROR_TARGET_NOT_HALTED;
3424 pPrivate = get_sam3_bank_private(bank);
3425 if (!(pPrivate->probed)) {
3426 r = ERROR_FLASH_BANK_NOT_PROBED;
3430 if ((offset + count) > pPrivate->size_bytes) {
3431 LOG_ERROR("Flash write error - past end of bank");
3432 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3433 (unsigned int)(offset),
3434 (unsigned int)(count),
3435 (unsigned int)(pPrivate->size_bytes));
3440 pagebuffer = malloc(pPrivate->page_size);
3442 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3447 /* what page do we start & end in? */
3448 page_cur = offset / pPrivate->page_size;
3449 page_end = (offset + count - 1) / pPrivate->page_size;
3451 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3452 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3454 /* Special case: all one page */
3457 /* (1) non-aligned start */
3458 /* (2) body pages */
3459 /* (3) non-aligned end. */
3461 /* Handle special case - all one page. */
3462 if (page_cur == page_end) {
3463 LOG_DEBUG("Special case, all in one page");
3464 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3468 page_offset = (offset & (pPrivate->page_size-1));
3469 memcpy(pagebuffer + page_offset,
3473 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3480 /* non-aligned start */
3481 page_offset = offset & (pPrivate->page_size - 1);
3483 LOG_DEBUG("Not-Aligned start");
3484 /* read the partial */
3485 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3489 /* over-write with new data */
3490 n = (pPrivate->page_size - page_offset);
3491 memcpy(pagebuffer + page_offset,
3495 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3505 /* By checking that offset is correct here, we also
3506 fix a clang warning */
3507 assert(offset % pPrivate->page_size == 0);
3509 /* intermediate large pages */
3510 /* also - the final *terminal* */
3511 /* if that terminal page is a full page */
3512 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3513 (int)page_cur, (int)page_end, (unsigned int)(count));
3515 while ((page_cur < page_end) &&
3516 (count >= pPrivate->page_size)) {
3517 r = sam3_page_write(pPrivate, page_cur, buffer);
3520 count -= pPrivate->page_size;
3521 buffer += pPrivate->page_size;
3525 /* terminal partial page? */
3527 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3528 /* we have a partial page */
3529 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3532 /* data goes at start */
3533 memcpy(pagebuffer, buffer, count);
3534 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3546 COMMAND_HANDLER(sam3_handle_info_command)
3548 struct sam3_chip *pChip;
3549 pChip = get_current_sam3(CMD_CTX);
3556 /* bank0 must exist before we can do anything */
3557 if (pChip->details.bank[0].pBank == NULL) {
3560 command_print(CMD_CTX,
3561 "Please define bank %d via command: flash bank %s ... ",
3563 at91sam3_flash.name);
3567 /* if bank 0 is not probed, then probe it */
3568 if (!(pChip->details.bank[0].probed)) {
3569 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3573 /* above guarantees the "chip details" structure is valid */
3574 /* and thus, bank private areas are valid */
3575 /* and we have a SAM3 chip, what a concept! */
3577 /* auto-probe other banks, 0 done above */
3578 for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3579 /* skip banks not present */
3580 if (!(pChip->details.bank[x].present))
3583 if (pChip->details.bank[x].pBank == NULL)
3586 if (pChip->details.bank[x].probed)
3589 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3594 r = sam3_GetInfo(pChip);
3595 if (r != ERROR_OK) {
3596 LOG_DEBUG("Sam3Info, Failed %d", r);
3603 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3607 struct sam3_chip *pChip;
3609 pChip = get_current_sam3(CMD_CTX);
3613 if (pChip->target->state != TARGET_HALTED) {
3614 LOG_ERROR("sam3 - target not halted");
3615 return ERROR_TARGET_NOT_HALTED;
3618 if (pChip->details.bank[0].pBank == NULL) {
3619 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3620 at91sam3_flash.name);
3623 if (!pChip->details.bank[0].probed) {
3624 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3631 return ERROR_COMMAND_SYNTAX_ERROR;
3640 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3644 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3650 if (0 == strcmp("show", CMD_ARGV[0])) {
3654 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3655 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3658 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3662 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3663 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3664 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3667 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3668 return ERROR_COMMAND_SYNTAX_ERROR;
3673 command_print(CMD_CTX, "Missing GPNVM number");
3674 return ERROR_COMMAND_SYNTAX_ERROR;
3677 if (0 == strcmp("set", CMD_ARGV[0]))
3678 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3679 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3680 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3681 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3683 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3684 r = ERROR_COMMAND_SYNTAX_ERROR;
3689 COMMAND_HANDLER(sam3_handle_slowclk_command)
3691 struct sam3_chip *pChip;
3693 pChip = get_current_sam3(CMD_CTX);
3705 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3707 /* absurd slow clock of 200Khz? */
3708 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3709 return ERROR_COMMAND_SYNTAX_ERROR;
3711 pChip->cfg.slow_freq = v;
3716 command_print(CMD_CTX, "Too many parameters");
3717 return ERROR_COMMAND_SYNTAX_ERROR;
3720 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3721 (int)(pChip->cfg.slow_freq / 1000),
3722 (int)(pChip->cfg.slow_freq % 1000));
3726 static const struct command_registration at91sam3_exec_command_handlers[] = {
3729 .handler = sam3_handle_gpnvm_command,
3730 .mode = COMMAND_EXEC,
3731 .usage = "[('clr'|'set'|'show') bitnum]",
3732 .help = "Without arguments, shows all bits in the gpnvm "
3733 "register. Otherwise, clears, sets, or shows one "
3734 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3738 .handler = sam3_handle_info_command,
3739 .mode = COMMAND_EXEC,
3740 .help = "Print information about the current at91sam3 chip"
3741 "and its flash configuration.",
3745 .handler = sam3_handle_slowclk_command,
3746 .mode = COMMAND_EXEC,
3747 .usage = "[clock_hz]",
3748 .help = "Display or set the slowclock frequency "
3749 "(default 32768 Hz).",
3751 COMMAND_REGISTRATION_DONE
3753 static const struct command_registration at91sam3_command_handlers[] = {
3756 .mode = COMMAND_ANY,
3757 .help = "at91sam3 flash command group",
3759 .chain = at91sam3_exec_command_handlers,
3761 COMMAND_REGISTRATION_DONE
3764 struct flash_driver at91sam3_flash = {
3766 .commands = at91sam3_command_handlers,
3767 .flash_bank_command = sam3_flash_bank_command,
3768 .erase = sam3_erase,
3769 .protect = sam3_protect,
3770 .write = sam3_write,
3771 .read = default_flash_read,
3772 .probe = sam3_probe,
3773 .auto_probe = sam3_auto_probe,
3774 .erase_check = sam3_erase_check,
3775 .protect_check = sam3_protect_check,