1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
17 * GNU General public License for more details. *
19 * You should have received a copy of the GNU General public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 // at91sam3u series (has one or two flash banks)
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 // at91sam3s series (has always one flash bank)
74 #define FLASH_BANK_BASE_S 0x00400000
76 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
77 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
78 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
79 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
80 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
81 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
82 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
83 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
84 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
85 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
86 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
87 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
88 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
89 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
90 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
91 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
92 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
93 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
95 #define offset_EFC_FMR 0
96 #define offset_EFC_FCR 4
97 #define offset_EFC_FSR 8
98 #define offset_EFC_FRR 12
101 extern struct flash_driver at91sam3_flash;
104 _tomhz(uint32_t freq_hz)
108 f = ((float)(freq_hz)) / 1000000.0;
112 // How the chip is configured.
114 uint32_t unique_id[4];
118 uint32_t mainosc_freq;
128 #define SAM3_CHIPID_CIDR (0x400E0740)
129 uint32_t CHIPID_CIDR;
130 #define SAM3_CHIPID_EXID (0x400E0744)
131 uint32_t CHIPID_EXID;
133 #define SAM3_SUPC_CR (0x400E1210)
136 #define SAM3_PMC_BASE (0x400E0400)
137 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
139 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
141 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
143 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
145 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
147 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
149 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
151 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
153 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
155 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
157 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
159 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
161 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
163 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
168 struct sam3_bank_private {
170 // DANGER: THERE ARE DRAGONS HERE..
171 // NOTE: If you add more 'ghost' pointers
172 // be aware that you must *manually* update
173 // these pointers in the function sam3_GetDetails()
174 // See the comment "Here there be dragons"
176 // so we can find the chip we belong to
177 struct sam3_chip *pChip;
178 // so we can find the orginal bank pointer
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
186 unsigned sector_size;
190 struct sam3_chip_details {
191 // THERE ARE DRAGONS HERE..
192 // note: If you add pointers here
193 // becareful about them as they
194 // may need to be updated inside
195 // the function: "sam3_GetDetails()
196 // which copy/overwrites the
197 // 'runtime' copy of this structure
198 uint32_t chipid_cidr;
202 #define SAM3_N_NVM_BITS 3
203 unsigned gpnvm[SAM3_N_NVM_BITS];
204 unsigned total_flash_size;
205 unsigned total_sram_size;
207 #define SAM3_MAX_FLASH_BANKS 2
208 // these are "initialized" from the global const data
209 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
214 struct sam3_chip *next;
217 // this is "initialized" from the global const structure
218 struct sam3_chip_details details;
219 struct target *target;
224 struct sam3_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam3_chip *pInfo);
230 static struct sam3_chip *all_sam3_chips;
232 static struct sam3_chip *
233 get_current_sam3(struct command_context *cmd_ctx)
236 static struct sam3_chip *p;
238 t = get_current_target(cmd_ctx);
240 command_print(cmd_ctx, "No current target?");
246 // this should not happen
247 // the command is not registered until the chip is created?
248 command_print(cmd_ctx, "No SAM3 chips exist?");
253 if (p->target == t) {
258 command_print(cmd_ctx, "Cannot find SAM3 chip?");
263 // these are used to *initialize* the "pChip->details" structure.
264 static const struct sam3_chip_details all_sam3_details[] = {
265 // Start at91sam3u* series
267 .chipid_cidr = 0x28100960,
268 .name = "at91sam3u4e",
269 .total_flash_size = 256 * 1024,
270 .total_sram_size = 52 * 1024,
274 // System boots at address 0x0
275 // gpnvm[1] = selects boot code
277 // boot is via "SAMBA" (rom)
280 // Selection is via gpnvm[2]
283 // NOTE: banks 0 & 1 switch places
285 // Bank0 is the boot rom
287 // Bank1 is the boot rom
296 .base_address = FLASH_BANK0_BASE_U,
297 .controller_address = 0x400e0800,
299 .size_bytes = 128 * 1024,
311 .base_address = FLASH_BANK1_BASE_U,
312 .controller_address = 0x400e0a00,
314 .size_bytes = 128 * 1024,
323 .chipid_cidr = 0x281a0760,
324 .name = "at91sam3u2e",
325 .total_flash_size = 128 * 1024,
326 .total_sram_size = 36 * 1024,
330 // System boots at address 0x0
331 // gpnvm[1] = selects boot code
333 // boot is via "SAMBA" (rom)
336 // Selection is via gpnvm[2]
345 .base_address = FLASH_BANK0_BASE_U,
346 .controller_address = 0x400e0800,
348 .size_bytes = 128 * 1024,
362 .chipid_cidr = 0x28190560,
363 .name = "at91sam3u1e",
364 .total_flash_size = 64 * 1024,
365 .total_sram_size = 20 * 1024,
369 // System boots at address 0x0
370 // gpnvm[1] = selects boot code
372 // boot is via "SAMBA" (rom)
375 // Selection is via gpnvm[2]
386 .base_address = FLASH_BANK0_BASE_U,
387 .controller_address = 0x400e0800,
389 .size_bytes = 64 * 1024,
405 .chipid_cidr = 0x28000960,
406 .name = "at91sam3u4c",
407 .total_flash_size = 256 * 1024,
408 .total_sram_size = 52 * 1024,
412 // System boots at address 0x0
413 // gpnvm[1] = selects boot code
415 // boot is via "SAMBA" (rom)
418 // Selection is via gpnvm[2]
421 // NOTE: banks 0 & 1 switch places
423 // Bank0 is the boot rom
425 // Bank1 is the boot rom
434 .base_address = FLASH_BANK0_BASE_U,
435 .controller_address = 0x400e0800,
437 .size_bytes = 128 * 1024,
448 .base_address = FLASH_BANK1_BASE_U,
449 .controller_address = 0x400e0a00,
451 .size_bytes = 128 * 1024,
460 .chipid_cidr = 0x280a0760,
461 .name = "at91sam3u2c",
462 .total_flash_size = 128 * 1024,
463 .total_sram_size = 36 * 1024,
467 // System boots at address 0x0
468 // gpnvm[1] = selects boot code
470 // boot is via "SAMBA" (rom)
473 // Selection is via gpnvm[2]
482 .base_address = FLASH_BANK0_BASE_U,
483 .controller_address = 0x400e0800,
485 .size_bytes = 128 * 1024,
499 .chipid_cidr = 0x28090560,
500 .name = "at91sam3u1c",
501 .total_flash_size = 64 * 1024,
502 .total_sram_size = 20 * 1024,
506 // System boots at address 0x0
507 // gpnvm[1] = selects boot code
509 // boot is via "SAMBA" (rom)
512 // Selection is via gpnvm[2]
523 .base_address = FLASH_BANK0_BASE_U,
524 .controller_address = 0x400e0800,
526 .size_bytes = 64 * 1024,
541 // Start at91sam3s* series
543 // Note: The preliminary at91sam3s datasheet says on page 302
544 // that the flash controller is at address 0x400E0800.
545 // This is _not_ the case, the controller resides at address 0x400e0a0.
547 .chipid_cidr = 0x28A00960,
548 .name = "at91sam3s4c",
549 .total_flash_size = 256 * 1024,
550 .total_sram_size = 48 * 1024,
560 .base_address = FLASH_BANK_BASE_S,
562 .controller_address = 0x400e0a00,
564 .size_bytes = 256 * 1024,
580 .chipid_cidr = 0x28900960,
581 .name = "at91sam3s4b",
582 .total_flash_size = 256 * 1024,
583 .total_sram_size = 48 * 1024,
593 .base_address = FLASH_BANK_BASE_S,
595 .controller_address = 0x400e0a00,
597 .size_bytes = 256 * 1024,
612 .chipid_cidr = 0x28800960,
613 .name = "at91sam3s4a",
614 .total_flash_size = 256 * 1024,
615 .total_sram_size = 48 * 1024,
625 .base_address = FLASH_BANK_BASE_S,
627 .controller_address = 0x400e0a00,
629 .size_bytes = 256 * 1024,
644 .chipid_cidr = 0x28AA0760,
645 .name = "at91sam3s2c",
646 .total_flash_size = 128 * 1024,
647 .total_sram_size = 32 * 1024,
657 .base_address = FLASH_BANK_BASE_S,
659 .controller_address = 0x400e0a00,
661 .size_bytes = 128 * 1024,
676 .chipid_cidr = 0x289A0760,
677 .name = "at91sam3s2b",
678 .total_flash_size = 128 * 1024,
679 .total_sram_size = 32 * 1024,
689 .base_address = FLASH_BANK_BASE_S,
691 .controller_address = 0x400e0a00,
693 .size_bytes = 128 * 1024,
708 .chipid_cidr = 0x288A0760,
709 .name = "at91sam3s2a",
710 .total_flash_size = 128 * 1024,
711 .total_sram_size = 32 * 1024,
721 .base_address = FLASH_BANK_BASE_S,
723 .controller_address = 0x400e0a00,
725 .size_bytes = 128 * 1024,
740 .chipid_cidr = 0x28A90560,
741 .name = "at91sam3s1c",
742 .total_flash_size = 64 * 1024,
743 .total_sram_size = 16 * 1024,
753 .base_address = FLASH_BANK_BASE_S,
755 .controller_address = 0x400e0a00,
757 .size_bytes = 64 * 1024,
772 .chipid_cidr = 0x28990560,
773 .name = "at91sam3s1b",
774 .total_flash_size = 64 * 1024,
775 .total_sram_size = 16 * 1024,
785 .base_address = FLASH_BANK_BASE_S,
787 .controller_address = 0x400e0a00,
789 .size_bytes = 64 * 1024,
804 .chipid_cidr = 0x28890560,
805 .name = "at91sam3s1a",
806 .total_flash_size = 64 * 1024,
807 .total_sram_size = 16 * 1024,
817 .base_address = FLASH_BANK_BASE_S,
819 .controller_address = 0x400e0a00,
821 .size_bytes = 64 * 1024,
843 /***********************************************************************
844 **********************************************************************
845 **********************************************************************
846 **********************************************************************
847 **********************************************************************
848 **********************************************************************/
849 /* *ATMEL* style code - from the SAM3 driver code */
852 * Get the current status of the EEFC and
853 * the value of some status bits (LOCKE, PROGE).
854 * @param pPrivate - info about the bank
855 * @param v - result goes here
858 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
861 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
862 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
864 ((unsigned int)((*v >> 2) & 1)),
865 ((unsigned int)((*v >> 1) & 1)),
866 ((unsigned int)((*v >> 0) & 1)));
872 * Get the result of the last executed command.
873 * @param pPrivate - info about the bank
874 * @param v - result goes here
877 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
881 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
885 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
890 EFC_StartCommand(struct sam3_bank_private *pPrivate,
891 unsigned command, unsigned argument)
900 // Check command & argument
903 case AT91C_EFC_FCMD_WP:
904 case AT91C_EFC_FCMD_WPL:
905 case AT91C_EFC_FCMD_EWP:
906 case AT91C_EFC_FCMD_EWPL:
907 // case AT91C_EFC_FCMD_EPL:
908 // case AT91C_EFC_FCMD_EPA:
909 case AT91C_EFC_FCMD_SLB:
910 case AT91C_EFC_FCMD_CLB:
911 n = (pPrivate->size_bytes / pPrivate->page_size);
913 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
917 case AT91C_EFC_FCMD_SFB:
918 case AT91C_EFC_FCMD_CFB:
919 if (argument >= pPrivate->pChip->details.n_gpnvms) {
920 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
921 pPrivate->pChip->details.n_gpnvms);
925 case AT91C_EFC_FCMD_GETD:
926 case AT91C_EFC_FCMD_EA:
927 case AT91C_EFC_FCMD_GLB:
928 case AT91C_EFC_FCMD_GFB:
929 case AT91C_EFC_FCMD_STUI:
930 case AT91C_EFC_FCMD_SPUI:
932 LOG_ERROR("Argument is meaningless for cmd: %d", command);
936 LOG_ERROR("Unknown command %d", command);
940 if (command == AT91C_EFC_FCMD_SPUI) {
941 // this is a very special situation.
942 // Situation (1) - error/retry - see below
943 // And we are being called recursively
944 // Situation (2) - normal, finished reading unique id
946 // it should be "ready"
947 EFC_GetStatus(pPrivate, &v);
953 // we have done this before
954 // the controller is not responding.
955 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
959 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
960 pPrivate->bank_number);
961 // we do that by issuing the *STOP* command
962 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
963 // above is recursive, and further recursion is blocked by
964 // if (command == AT91C_EFC_FCMD_SPUI) above
970 v = (0x5A << 24) | (argument << 8) | command;
971 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
972 r = target_write_u32(pPrivate->pBank->target,
973 pPrivate->controller_address + offset_EFC_FCR,
976 LOG_DEBUG("Error Write failed");
982 * Performs the given command and wait until its completion (or an error).
983 * @param pPrivate - info about the bank
984 * @param command - Command to perform.
985 * @param argument - Optional command argument.
986 * @param status - put command status bits here
989 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
997 long long ms_now, ms_end;
1004 r = EFC_StartCommand(pPrivate, command, argument);
1005 if (r != ERROR_OK) {
1009 ms_end = 500 + timeval_ms();
1013 r = EFC_GetStatus(pPrivate, &v);
1014 if (r != ERROR_OK) {
1017 ms_now = timeval_ms();
1018 if (ms_now > ms_end) {
1020 LOG_ERROR("Command timeout");
1024 while ((v & 1) == 0)
1029 *status = (v & 0x6);
1040 * Read the unique ID.
1041 * @param pPrivate - info about the bank
1042 * The unique ID is stored in the 'pPrivate' structure.
1045 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
1051 pPrivate->pChip->cfg.unique_id[0] = 0;
1052 pPrivate->pChip->cfg.unique_id[1] = 0;
1053 pPrivate->pChip->cfg.unique_id[2] = 0;
1054 pPrivate->pChip->cfg.unique_id[3] = 0;
1057 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1062 for (x = 0 ; x < 4 ; x++) {
1063 r = target_read_u32(pPrivate->pChip->target,
1064 pPrivate->pBank->base + (x * 4),
1069 pPrivate->pChip->cfg.unique_id[x] = v;
1072 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1073 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1075 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1076 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1077 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1078 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1084 * Erases the entire flash.
1085 * @param pPrivate - the info about the bank.
1088 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1091 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1097 * Gets current GPNVM state.
1098 * @param pPrivate - info about the bank.
1099 * @param gpnvm - GPNVM bit index.
1100 * @param puthere - result stored here.
1102 //------------------------------------------------------------------------------
1104 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1110 if (pPrivate->bank_number != 0) {
1111 LOG_ERROR("GPNVM only works with Bank0");
1115 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1116 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1117 gpnvm,pPrivate->pChip->details.n_gpnvms);
1121 // Get GPNVMs status
1122 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1123 if (r != ERROR_OK) {
1124 LOG_ERROR("Failed");
1128 r = EFC_GetResult(pPrivate, &v);
1131 // Check if GPNVM is set
1132 // get the bit and make it a 0/1
1133 *puthere = (v >> gpnvm) & 1;
1143 * Clears the selected GPNVM bit.
1144 * @param pPrivate info about the bank
1145 * @param gpnvm GPNVM index.
1146 * @returns 0 if successful; otherwise returns an error code.
1149 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1155 if (pPrivate->bank_number != 0) {
1156 LOG_ERROR("GPNVM only works with Bank0");
1160 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1161 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1162 gpnvm,pPrivate->pChip->details.n_gpnvms);
1166 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1167 if (r != ERROR_OK) {
1168 LOG_DEBUG("Failed: %d",r);
1171 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1172 LOG_DEBUG("End: %d",r);
1179 * Sets the selected GPNVM bit.
1180 * @param pPrivate info about the bank
1181 * @param gpnvm GPNVM index.
1184 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1189 if (pPrivate->bank_number != 0) {
1190 LOG_ERROR("GPNVM only works with Bank0");
1194 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1195 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1196 gpnvm,pPrivate->pChip->details.n_gpnvms);
1200 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1201 if (r != ERROR_OK) {
1209 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1216 * Returns a bit field (at most 64) of locked regions within a page.
1217 * @param pPrivate info about the bank
1218 * @param v where to store locked bits
1221 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
1225 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1226 if (r == ERROR_OK) {
1227 r = EFC_GetResult(pPrivate, v);
1229 LOG_DEBUG("End: %d",r);
1235 * Unlocks all the regions in the given address range.
1236 * @param pPrivate info about the bank
1237 * @param start_sector first sector to unlock
1238 * @param end_sector last (inclusive) to unlock
1242 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
1243 unsigned start_sector,
1244 unsigned end_sector)
1249 uint32_t pages_per_sector;
1251 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1253 /* Unlock all pages */
1254 while (start_sector <= end_sector) {
1255 pg = start_sector * pages_per_sector;
1257 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1258 if (r != ERROR_OK) {
1270 * @param pPrivate - info about the bank
1271 * @param start_sector - first sector to lock
1272 * @param end_sector - last sector (inclusive) to lock
1275 FLASHD_Lock(struct sam3_bank_private *pPrivate,
1276 unsigned start_sector,
1277 unsigned end_sector)
1281 uint32_t pages_per_sector;
1284 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1286 /* Lock all pages */
1287 while (start_sector <= end_sector) {
1288 pg = start_sector * pages_per_sector;
1290 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1291 if (r != ERROR_OK) {
1300 /****** END SAM3 CODE ********/
1302 /* begin helpful debug code */
1303 // print the fieldname, the field value, in dec & hex, and return field value
1305 sam3_reg_fieldname(struct sam3_chip *pChip,
1306 const char *regname,
1315 // extract the field
1317 v = v & ((1 << width)-1);
1327 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1328 REG_NAME_WIDTH, regname,
1335 static const char _unknown[] = "unknown";
1336 static const char * const eproc_names[] = {
1355 #define nvpsize2 nvpsize // these two tables are identical
1356 static const char * const nvpsize[] = {
1369 "1024K bytes", // 12
1371 "2048K bytes", // 14
1376 static const char * const sramsize[] = {
1396 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1397 { 0x19, "AT91SAM9xx Series" },
1398 { 0x29, "AT91SAM9XExx Series" },
1399 { 0x34, "AT91x34 Series" },
1400 { 0x37, "CAP7 Series" },
1401 { 0x39, "CAP9 Series" },
1402 { 0x3B, "CAP11 Series" },
1403 { 0x40, "AT91x40 Series" },
1404 { 0x42, "AT91x42 Series" },
1405 { 0x55, "AT91x55 Series" },
1406 { 0x60, "AT91SAM7Axx Series" },
1407 { 0x61, "AT91SAM7AQxx Series" },
1408 { 0x63, "AT91x63 Series" },
1409 { 0x70, "AT91SAM7Sxx Series" },
1410 { 0x71, "AT91SAM7XCxx Series" },
1411 { 0x72, "AT91SAM7SExx Series" },
1412 { 0x73, "AT91SAM7Lxx Series" },
1413 { 0x75, "AT91SAM7Xxx Series" },
1414 { 0x76, "AT91SAM7SLxx Series" },
1415 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1416 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1417 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1418 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1419 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1420 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1421 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1422 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1423 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1424 { 0x92, "AT91x92 Series" },
1425 { 0xF0, "AT75Cxx Series" },
1430 static const char * const nvptype[] = {
1432 "romless or onchip flash", // 1
1433 "embedded flash memory", // 2
1434 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1435 "sram emulating flash", // 4
1442 static const char *_yes_or_no(uint32_t v)
1451 static const char * const _rc_freq[] = {
1452 "4 MHz", "8 MHz", "12 MHz", "reserved"
1456 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1461 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1462 LOG_USER_N("(main xtal enabled: %s)\n",
1464 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1465 LOG_USER_N("(main osc bypass: %s)\n",
1467 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1468 LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
1470 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1471 LOG_USER_N("(onchip RC-OSC freq: %s)\n",
1474 pChip->cfg.rc_freq = 0;
1478 pChip->cfg.rc_freq = 0;
1480 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1483 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1486 pChip->cfg.rc_freq = 12* 1000 * 1000;
1491 v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1492 LOG_USER_N("(startup clks, time= %f uSecs)\n",
1493 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1494 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1495 LOG_USER_N("(mainosc source: %s)\n",
1496 v ? "external xtal" : "internal RC");
1498 v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1499 LOG_USER_N("(clock failure enabled: %s)\n",
1506 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1512 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1515 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1516 LOG_USER_N("%s\n", eproc_names[v]);
1518 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1519 LOG_USER_N("%s\n", nvpsize[v]);
1521 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1522 LOG_USER_N("%s\n", nvpsize2[v]);
1524 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1525 LOG_USER_N("%s\n", sramsize[ v ]);
1527 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1529 for (x = 0 ; archnames[x].name ; x++) {
1530 if (v == archnames[x].value) {
1531 cp = archnames[x].name;
1536 LOG_USER_N("%s\n", cp);
1538 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1539 LOG_USER_N("%s\n", nvptype[ v ]);
1541 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1542 LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
1546 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1551 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1552 LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
1554 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1556 v = (v * pChip->cfg.slow_freq) / 16;
1557 pChip->cfg.mainosc_freq = v;
1559 LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1561 pChip->cfg.slow_freq / 1000,
1562 pChip->cfg.slow_freq % 1000);
1567 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1571 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1573 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1575 pChip->cfg.plla_freq = 0;
1577 LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
1578 } else if (diva == 0) {
1579 LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
1580 } else if (diva == 1) {
1581 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1582 LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
1583 _tomhz(pChip->cfg.plla_freq));
1589 sam3_explain_mckr(struct sam3_chip *pChip)
1591 uint32_t css, pres, fin = 0;
1593 const char *cp = NULL;
1595 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1598 fin = pChip->cfg.slow_freq;
1602 fin = pChip->cfg.mainosc_freq;
1606 fin = pChip->cfg.plla_freq;
1610 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1611 fin = 480 * 1000 * 1000;
1615 cp = "upll (*ERROR* UPLL is disabled)";
1623 LOG_USER_N("%s (%3.03f Mhz)\n",
1626 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1627 switch (pres & 0x07) {
1630 cp = "selected clock";
1663 LOG_USER_N("(%s)\n", cp);
1665 // sam3 has a *SINGLE* clock -
1666 // other at91 series parts have divisors for these.
1667 pChip->cfg.cpu_freq = fin;
1668 pChip->cfg.mclk_freq = fin;
1669 pChip->cfg.fclk_freq = fin;
1670 LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
1675 static struct sam3_chip *
1676 target2sam3(struct target *pTarget)
1678 struct sam3_chip *pChip;
1680 if (pTarget == NULL) {
1684 pChip = all_sam3_chips;
1686 if (pChip->target == pTarget) {
1687 break; // return below
1689 pChip = pChip->next;
1697 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1699 // this function exists to help
1700 // keep funky offsetof() errors
1701 // and casting from causing bugs
1703 // By using prototypes - we can detect what would
1704 // be casting errors.
1706 return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset));
1710 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1711 static const struct sam3_reg_list sam3_all_regs[] = {
1712 SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1713 SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1714 SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1715 SAM3_ENTRY(CKGR_UCKR , NULL),
1716 SAM3_ENTRY(PMC_FSMR , NULL),
1717 SAM3_ENTRY(PMC_FSPR , NULL),
1718 SAM3_ENTRY(PMC_IMR , NULL),
1719 SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1720 SAM3_ENTRY(PMC_PCK0 , NULL),
1721 SAM3_ENTRY(PMC_PCK1 , NULL),
1722 SAM3_ENTRY(PMC_PCK2 , NULL),
1723 SAM3_ENTRY(PMC_PCSR , NULL),
1724 SAM3_ENTRY(PMC_SCSR , NULL),
1725 SAM3_ENTRY(PMC_SR , NULL),
1726 SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1727 SAM3_ENTRY(CHIPID_EXID , NULL),
1728 SAM3_ENTRY(SUPC_CR, NULL),
1730 // TERMINATE THE LIST
1738 static struct sam3_bank_private *
1739 get_sam3_bank_private(struct flash_bank *bank)
1741 return (struct sam3_bank_private *)(bank->driver_priv);
1745 * Given a pointer to where it goes in the structure,
1746 * determine the register name, address from the all registers table.
1748 static const struct sam3_reg_list *
1749 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1751 const struct sam3_reg_list *pReg;
1753 pReg = &(sam3_all_regs[0]);
1754 while (pReg->name) {
1755 uint32_t *pPossible;
1757 // calculate where this one go..
1758 // it is "possibly" this register.
1760 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1762 // well? Is it this register
1763 if (pPossible == goes_here) {
1771 // This is *TOTAL*PANIC* - we are totally screwed.
1772 LOG_ERROR("INVALID SAM3 REGISTER");
1778 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1780 const struct sam3_reg_list *pReg;
1783 pReg = sam3_GetReg(pChip, goes_here);
1788 r = target_read_u32(pChip->target, pReg->address, goes_here);
1789 if (r != ERROR_OK) {
1790 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1791 pReg->name, (unsigned)(pReg->address), r);
1799 sam3_ReadAllRegs(struct sam3_chip *pChip)
1802 const struct sam3_reg_list *pReg;
1804 pReg = &(sam3_all_regs[0]);
1805 while (pReg->name) {
1806 r = sam3_ReadThisReg(pChip,
1807 sam3_get_reg_ptr(&(pChip->cfg), pReg));
1808 if (r != ERROR_OK) {
1809 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1810 pReg->name, ((unsigned)(pReg->address)), r);
1822 sam3_GetInfo(struct sam3_chip *pChip)
1824 const struct sam3_reg_list *pReg;
1827 pReg = &(sam3_all_regs[0]);
1828 while (pReg->name) {
1830 LOG_DEBUG("Start: %s", pReg->name);
1831 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1832 LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
1837 if (pReg->explain_func) {
1838 (*(pReg->explain_func))(pChip);
1840 LOG_DEBUG("End: %s", pReg->name);
1843 LOG_USER_N(" rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1844 LOG_USER_N(" mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1845 LOG_USER_N(" plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1846 LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1847 LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1850 LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1851 pChip->cfg.unique_id[0],
1852 pChip->cfg.unique_id[1],
1853 pChip->cfg.unique_id[2],
1854 pChip->cfg.unique_id[3]);
1862 sam3_erase_check(struct flash_bank *bank)
1867 if (bank->target->state != TARGET_HALTED) {
1868 LOG_ERROR("Target not halted");
1869 return ERROR_TARGET_NOT_HALTED;
1871 if (0 == bank->num_sectors) {
1872 LOG_ERROR("Target: not supported/not probed\n");
1876 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1877 for (x = 0 ; x < bank->num_sectors ; x++) {
1878 bank->sectors[x].is_erased = 1;
1886 sam3_protect_check(struct flash_bank *bank)
1891 struct sam3_bank_private *pPrivate;
1894 if (bank->target->state != TARGET_HALTED) {
1895 LOG_ERROR("Target not halted");
1896 return ERROR_TARGET_NOT_HALTED;
1899 pPrivate = get_sam3_bank_private(bank);
1901 LOG_ERROR("no private for this bank?");
1904 if (!(pPrivate->probed)) {
1905 return ERROR_FLASH_BANK_NOT_PROBED;
1908 r = FLASHD_GetLockBits(pPrivate , &v);
1909 if (r != ERROR_OK) {
1910 LOG_DEBUG("Failed: %d",r);
1914 for (x = 0 ; x < pPrivate->nsectors ; x++) {
1915 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1921 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
1923 struct sam3_chip *pChip;
1925 pChip = all_sam3_chips;
1927 // is this an existing chip?
1929 if (pChip->target == bank->target) {
1932 pChip = pChip->next;
1936 // this is a *NEW* chip
1937 pChip = calloc(1, sizeof(struct sam3_chip));
1939 LOG_ERROR("NO RAM!");
1942 pChip->target = bank->target;
1944 pChip->next = all_sam3_chips;
1945 all_sam3_chips = pChip;
1946 pChip->target = bank->target;
1947 // assumption is this runs at 32khz
1948 pChip->cfg.slow_freq = 32768;
1952 switch (bank->base) {
1954 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
1955 [at91sam3u series] or 0x%08x [at91sam3s series])",
1956 ((unsigned int)(bank->base)),
1957 ((unsigned int)(FLASH_BANK0_BASE_U)),
1958 ((unsigned int)(FLASH_BANK1_BASE_U)),
1959 ((unsigned int)(FLASH_BANK_BASE_S)));
1964 case FLASH_BANK0_BASE_U:
1965 bank->driver_priv = &(pChip->details.bank[0]);
1966 bank->bank_number = 0;
1967 pChip->details.bank[0].pChip = pChip;
1968 pChip->details.bank[0].pBank = bank;
1970 case FLASH_BANK1_BASE_U:
1971 bank->driver_priv = &(pChip->details.bank[1]);
1972 bank->bank_number = 1;
1973 pChip->details.bank[1].pChip = pChip;
1974 pChip->details.bank[1].pBank = bank;
1977 case FLASH_BANK_BASE_S:
1978 bank->driver_priv = &(pChip->details.bank[0]);
1979 bank->bank_number = 0;
1980 pChip->details.bank[0].pChip = pChip;
1981 pChip->details.bank[0].pBank = bank;
1985 // we initialize after probing.
1990 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1992 const struct sam3_chip_details *pDetails;
1993 struct sam3_chip *pChip;
1994 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
1998 pDetails = all_sam3_details;
1999 while (pDetails->name) {
2000 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
2006 if (pDetails->name == NULL) {
2007 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2008 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2009 // Help the victim, print details about the chip
2010 LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
2011 pPrivate->pChip->cfg.CHIPID_CIDR);
2012 sam3_explain_chipid_cidr(pPrivate->pChip);
2016 // DANGER: THERE ARE DRAGONS HERE
2018 // get our pChip - it is going
2019 // to be over-written shortly
2020 pChip = pPrivate->pChip;
2022 // Note that, in reality:
2024 // pPrivate = &(pChip->details.bank[0])
2025 // or pPrivate = &(pChip->details.bank[1])
2028 // save the "bank" pointers
2029 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2030 saved_banks[ x ] = pChip->details.bank[x].pBank;
2033 // Overwrite the "details" structure.
2034 memcpy(&(pPrivate->pChip->details),
2036 sizeof(pPrivate->pChip->details));
2038 // now fix the ghosted pointers
2039 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2040 pChip->details.bank[x].pChip = pChip;
2041 pChip->details.bank[x].pBank = saved_banks[x];
2044 // update the *BANK*SIZE*
2053 _sam3_probe(struct flash_bank *bank, int noise)
2057 struct sam3_bank_private *pPrivate;
2060 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2061 if (bank->target->state != TARGET_HALTED)
2063 LOG_ERROR("Target not halted");
2064 return ERROR_TARGET_NOT_HALTED;
2067 pPrivate = get_sam3_bank_private(bank);
2069 LOG_ERROR("Invalid/unknown bank number\n");
2073 r = sam3_ReadAllRegs(pPrivate->pChip);
2074 if (r != ERROR_OK) {
2080 if (pPrivate->pChip->probed) {
2081 r = sam3_GetInfo(pPrivate->pChip);
2083 r = sam3_GetDetails(pPrivate);
2085 if (r != ERROR_OK) {
2089 // update the flash bank size
2090 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2091 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
2092 bank->size = pPrivate->pChip->details.bank[0].size_bytes;
2097 if (bank->sectors == NULL) {
2098 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2099 if (bank->sectors == NULL) {
2100 LOG_ERROR("No memory!");
2103 bank->num_sectors = pPrivate->nsectors;
2105 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
2106 bank->sectors[x].size = pPrivate->sector_size;
2107 bank->sectors[x].offset = x * (pPrivate->sector_size);
2109 bank->sectors[x].is_erased = -1;
2110 bank->sectors[x].is_protected = -1;
2114 pPrivate->probed = 1;
2116 r = sam3_protect_check(bank);
2117 if (r != ERROR_OK) {
2121 LOG_DEBUG("Bank = %d, nbanks = %d",
2122 pPrivate->bank_number , pPrivate->pChip->details.n_banks);
2123 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2125 // it appears to be associated with the *last* flash bank.
2126 FLASHD_ReadUniqueID(pPrivate);
2133 sam3_probe(struct flash_bank *bank)
2135 return _sam3_probe(bank, 1);
2139 sam3_auto_probe(struct flash_bank *bank)
2141 return _sam3_probe(bank, 0);
2147 sam3_erase(struct flash_bank *bank, int first, int last)
2149 struct sam3_bank_private *pPrivate;
2153 if (bank->target->state != TARGET_HALTED) {
2154 LOG_ERROR("Target not halted");
2155 return ERROR_TARGET_NOT_HALTED;
2158 r = sam3_auto_probe(bank);
2159 if (r != ERROR_OK) {
2160 LOG_DEBUG("Here,r=%d",r);
2164 pPrivate = get_sam3_bank_private(bank);
2165 if (!(pPrivate->probed)) {
2166 return ERROR_FLASH_BANK_NOT_PROBED;
2169 if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
2172 return FLASHD_EraseEntireBank(pPrivate);
2174 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2179 sam3_protect(struct flash_bank *bank, int set, int first, int last)
2181 struct sam3_bank_private *pPrivate;
2185 if (bank->target->state != TARGET_HALTED) {
2186 LOG_ERROR("Target not halted");
2187 return ERROR_TARGET_NOT_HALTED;
2190 pPrivate = get_sam3_bank_private(bank);
2191 if (!(pPrivate->probed)) {
2192 return ERROR_FLASH_BANK_NOT_PROBED;
2196 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2198 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2200 LOG_DEBUG("End: r=%d",r);
2208 sam3_info(struct flash_bank *bank, char *buf, int buf_size)
2210 if (bank->target->state != TARGET_HALTED) {
2211 LOG_ERROR("Target not halted");
2212 return ERROR_TARGET_NOT_HALTED;
2219 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2224 adr = pagenum * pPrivate->page_size;
2225 adr += adr + pPrivate->base_address;
2227 r = target_read_memory(pPrivate->pChip->target,
2229 4, /* THIS*MUST*BE* in 32bit values */
2230 pPrivate->page_size / 4,
2232 if (r != ERROR_OK) {
2233 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
2238 // The code below is basically this:
2240 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2242 // Only the *CPU* can write to the flash buffer.
2243 // the DAP cannot... so - we download this 28byte thing
2244 // Run the algorithm - (below)
2245 // to program the device
2247 // ========================================
2248 // #include <stdint.h>
2252 // const uint32_t *src;
2254 // volatile uint32_t *base;
2259 // uint32_t sam3_function(struct foo *p)
2261 // volatile uint32_t *v;
2263 // const uint32_t *s;
2285 // ========================================
2289 static const uint8_t
2290 sam3_page_write_opcodes[] = {
2291 // 24 0000 0446 mov r4, r0
2293 // 25 0002 6168 ldr r1, [r4, #4]
2295 // 26 0004 0068 ldr r0, [r0, #0]
2297 // 27 0006 A268 ldr r2, [r4, #8]
2299 // 28 @ lr needed for prologue
2301 // 30 0008 51F8043B ldr r3, [r1], #4
2302 0x51,0xf8,0x04,0x3b,
2303 // 31 000c 12F1FF32 adds r2, r2, #-1
2304 0x12,0xf1,0xff,0x32,
2305 // 32 0010 40F8043B str r3, [r0], #4
2306 0x40,0xf8,0x04,0x3b,
2307 // 33 0014 F8D1 bne .L2
2309 // 34 0016 E268 ldr r2, [r4, #12]
2311 // 35 0018 2369 ldr r3, [r4, #16]
2313 // 36 001a 5360 str r3, [r2, #4]
2315 // 37 001c 0832 adds r2, r2, #8
2318 // 39 001e 1068 ldr r0, [r2, #0]
2320 // 40 0020 10F0010F tst r0, #1
2321 0x10,0xf0,0x01,0x0f,
2322 // 41 0024 FBD0 beq .L4
2324 0x00,0xBE /* bkpt #0 */
2329 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2335 adr = pagenum * pPrivate->page_size;
2336 adr += (adr + pPrivate->base_address);
2338 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2339 r = target_write_memory(pPrivate->pChip->target,
2341 4, /* THIS*MUST*BE* in 32bit values */
2342 pPrivate->page_size / 4,
2344 if (r != ERROR_OK) {
2345 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2349 r = EFC_PerformCommand(pPrivate,
2350 // send Erase & Write Page
2355 if (r != ERROR_OK) {
2356 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2358 if (status & (1 << 2)) {
2359 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2362 if (status & (1 << 1)) {
2363 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2374 sam3_write(struct flash_bank *bank,
2383 unsigned page_offset;
2384 struct sam3_bank_private *pPrivate;
2385 uint8_t *pagebuffer;
2387 // incase we bail further below, set this to null
2390 // ignore dumb requests
2396 if (bank->target->state != TARGET_HALTED) {
2397 LOG_ERROR("Target not halted");
2398 r = ERROR_TARGET_NOT_HALTED;
2402 pPrivate = get_sam3_bank_private(bank);
2403 if (!(pPrivate->probed)) {
2404 r = ERROR_FLASH_BANK_NOT_PROBED;
2409 if ((offset + count) > pPrivate->size_bytes) {
2410 LOG_ERROR("Flash write error - past end of bank");
2411 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2412 (unsigned int)(offset),
2413 (unsigned int)(count),
2414 (unsigned int)(pPrivate->size_bytes));
2419 pagebuffer = malloc(pPrivate->page_size);
2421 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2426 // what page do we start & end in?
2427 page_cur = offset / pPrivate->page_size;
2428 page_end = (offset + count - 1) / pPrivate->page_size;
2430 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2431 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2433 // Special case: all one page
2436 // (1) non-aligned start
2438 // (3) non-aligned end.
2440 // Handle special case - all one page.
2441 if (page_cur == page_end) {
2442 LOG_DEBUG("Special case, all in one page");
2443 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2444 if (r != ERROR_OK) {
2448 page_offset = (offset & (pPrivate->page_size-1));
2449 memcpy(pagebuffer + page_offset,
2453 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2454 if (r != ERROR_OK) {
2461 // non-aligned start
2462 page_offset = offset & (pPrivate->page_size - 1);
2464 LOG_DEBUG("Not-Aligned start");
2466 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2467 if (r != ERROR_OK) {
2471 // over-write with new data
2472 n = (pPrivate->page_size - page_offset);
2473 memcpy(pagebuffer + page_offset,
2477 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2478 if (r != ERROR_OK) {
2488 // intermediate large pages
2489 // also - the final *terminal*
2490 // if that terminal page is a full page
2491 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2492 (int)page_cur, (int)page_end, (unsigned int)(count));
2494 while ((page_cur < page_end) &&
2495 (count >= pPrivate->page_size)) {
2496 r = sam3_page_write(pPrivate, page_cur, buffer);
2497 if (r != ERROR_OK) {
2500 count -= pPrivate->page_size;
2501 buffer += pPrivate->page_size;
2505 // terminal partial page?
2507 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2508 // we have a partial page
2509 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2510 if (r != ERROR_OK) {
2513 // data goes at start
2514 memcpy(pagebuffer, buffer, count);
2515 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2516 if (r != ERROR_OK) {
2531 COMMAND_HANDLER(sam3_handle_info_command)
2533 struct sam3_chip *pChip;
2537 pChip = get_current_sam3(CMD_CTX);
2544 // bank0 must exist before we can do anything
2545 if (pChip->details.bank[0].pBank == NULL) {
2548 command_print(CMD_CTX,
2549 "Please define bank %d via command: flash bank %s ... ",
2551 at91sam3_flash.name);
2555 // if bank 0 is not probed, then probe it
2556 if (!(pChip->details.bank[0].probed)) {
2557 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2558 if (r != ERROR_OK) {
2562 // above guarantees the "chip details" structure is valid
2563 // and thus, bank private areas are valid
2564 // and we have a SAM3 chip, what a concept!
2567 // auto-probe other banks, 0 done above
2568 for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2569 // skip banks not present
2570 if (!(pChip->details.bank[x].present)) {
2574 if (pChip->details.bank[x].pBank == NULL) {
2578 if (pChip->details.bank[x].probed) {
2582 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2583 if (r != ERROR_OK) {
2589 r = sam3_GetInfo(pChip);
2590 if (r != ERROR_OK) {
2591 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2598 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2602 struct sam3_chip *pChip;
2604 pChip = get_current_sam3(CMD_CTX);
2609 if (pChip->target->state != TARGET_HALTED) {
2610 LOG_ERROR("sam3 - target not halted");
2611 return ERROR_TARGET_NOT_HALTED;
2615 if (pChip->details.bank[0].pBank == NULL) {
2616 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2617 at91sam3_flash.name);
2620 if (!pChip->details.bank[0].probed) {
2621 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2622 if (r != ERROR_OK) {
2630 command_print(CMD_CTX,"Too many parameters\n");
2631 return ERROR_COMMAND_SYNTAX_ERROR;
2641 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) {
2645 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2651 if (0 == strcmp("show", CMD_ARGV[0])) {
2655 for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2656 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2657 if (r != ERROR_OK) {
2660 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
2664 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2665 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2666 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
2669 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
2670 return ERROR_COMMAND_SYNTAX_ERROR;
2675 command_print(CMD_CTX, "Missing GPNVM number");
2676 return ERROR_COMMAND_SYNTAX_ERROR;
2679 if (0 == strcmp("set", CMD_ARGV[0])) {
2680 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2681 } else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2682 (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
2683 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2685 command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
2686 r = ERROR_COMMAND_SYNTAX_ERROR;
2691 COMMAND_HANDLER(sam3_handle_slowclk_command)
2693 struct sam3_chip *pChip;
2695 pChip = get_current_sam3(CMD_CTX);
2709 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2711 // absurd slow clock of 200Khz?
2712 command_print(CMD_CTX,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2713 return ERROR_COMMAND_SYNTAX_ERROR;
2715 pChip->cfg.slow_freq = v;
2720 command_print(CMD_CTX,"Too many parameters");
2721 return ERROR_COMMAND_SYNTAX_ERROR;
2724 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2725 (int)(pChip->cfg.slow_freq/ 1000),
2726 (int)(pChip->cfg.slow_freq% 1000));
2730 static const struct command_registration at91sam3_exec_command_handlers[] = {
2733 .handler = sam3_handle_gpnvm_command,
2734 .mode = COMMAND_EXEC,
2735 .usage = "[('clr'|'set'|'show') bitnum]",
2736 .help = "Without arguments, shows all bits in the gpnvm "
2737 "register. Otherwise, clears, sets, or shows one "
2738 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2742 .handler = sam3_handle_info_command,
2743 .mode = COMMAND_EXEC,
2744 .help = "Print information about the current at91sam3 chip"
2745 "and its flash configuration.",
2749 .handler = sam3_handle_slowclk_command,
2750 .mode = COMMAND_EXEC,
2751 .usage = "[clock_hz]",
2752 .help = "Display or set the slowclock frequency "
2753 "(default 32768 Hz).",
2755 COMMAND_REGISTRATION_DONE
2757 static const struct command_registration at91sam3_command_handlers[] = {
2760 .mode = COMMAND_ANY,
2761 .help = "at91sam3 flash command group",
2762 .chain = at91sam3_exec_command_handlers,
2764 COMMAND_REGISTRATION_DONE
2767 struct flash_driver at91sam3_flash = {
2769 .commands = at91sam3_command_handlers,
2770 .flash_bank_command = sam3_flash_bank_command,
2771 .erase = sam3_erase,
2772 .protect = sam3_protect,
2773 .write = sam3_write,
2774 .read = default_flash_read,
2775 .probe = sam3_probe,
2776 .auto_probe = sam3_auto_probe,
2777 .erase_check = sam3_erase_check,
2778 .protect_check = sam3_protect_check,