1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
53 /* END ATMEL COPYRIGHT */
62 #include <helper/time_support.h>
64 #define REG_NAME_WIDTH (12)
67 #define FLASH_BANK0_BASE 0x00080000
68 #define FLASH_BANK1_BASE 0x00100000
70 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
71 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
72 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
73 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
74 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
75 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
76 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
77 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
78 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
79 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
80 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
81 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
82 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
83 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
84 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
85 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
86 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
87 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
89 #define offset_EFC_FMR 0
90 #define offset_EFC_FCR 4
91 #define offset_EFC_FSR 8
92 #define offset_EFC_FRR 12
96 _tomhz(uint32_t freq_hz)
100 f = ((float)(freq_hz)) / 1000000.0;
104 // How the chip is configured.
106 uint32_t unique_id[4];
110 uint32_t mainosc_freq;
120 #define SAM3_CHIPID_CIDR (0x400E0740)
121 uint32_t CHIPID_CIDR;
122 #define SAM3_CHIPID_EXID (0x400E0744)
123 uint32_t CHIPID_EXID;
125 #define SAM3_SUPC_CR (0x400E1210)
128 #define SAM3_PMC_BASE (0x400E0400)
129 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
131 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
133 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
135 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
137 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
139 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
141 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
143 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
145 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
147 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
149 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
151 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
153 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
155 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
160 struct sam3_bank_private {
162 // DANGER: THERE ARE DRAGONS HERE..
163 // NOTE: If you add more 'ghost' pointers
164 // be aware that you must *manually* update
165 // these pointers in the function sam3_GetDetails()
166 // See the comment "Here there be dragons"
168 // so we can find the chip we belong to
169 struct sam3_chip *pChip;
170 // so we can find the orginal bank pointer
171 struct flash_bank *pBank;
172 unsigned bank_number;
173 uint32_t controller_address;
174 uint32_t base_address;
178 unsigned sector_size;
182 struct sam3_chip_details {
183 // THERE ARE DRAGONS HERE..
184 // note: If you add pointers here
185 // becareful about them as they
186 // may need to be updated inside
187 // the function: "sam3_GetDetails()
188 // which copy/overwrites the
189 // 'runtime' copy of this structure
190 uint32_t chipid_cidr;
194 #define SAM3_N_NVM_BITS 3
195 unsigned gpnvm[SAM3_N_NVM_BITS];
196 unsigned total_flash_size;
197 unsigned total_sram_size;
199 #define SAM3_MAX_FLASH_BANKS 2
200 // these are "initialized" from the global const data
201 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
206 struct sam3_chip *next;
209 // this is "initialized" from the global const structure
210 struct sam3_chip_details details;
211 struct target *target;
216 struct sam3_reg_list {
217 uint32_t address; size_t struct_offset; const char *name;
218 void (*explain_func)(struct sam3_chip *pInfo);
222 static struct sam3_chip *all_sam3_chips;
224 static struct sam3_chip *
225 get_current_sam3(struct command_context *cmd_ctx)
228 static struct sam3_chip *p;
230 t = get_current_target(cmd_ctx);
232 command_print(cmd_ctx, "No current target?");
238 // this should not happen
239 // the command is not registered until the chip is created?
240 command_print(cmd_ctx, "No SAM3 chips exist?");
245 if (p->target == t) {
250 command_print(cmd_ctx, "Cannot find SAM3 chip?");
255 // these are used to *initialize* the "pChip->details" structure.
256 static const struct sam3_chip_details all_sam3_details[] = {
258 .chipid_cidr = 0x28100960,
259 .name = "at91sam3u4e",
260 .total_flash_size = 256 * 1024,
261 .total_sram_size = 52 * 1024,
265 // System boots at address 0x0
266 // gpnvm[1] = selects boot code
268 // boot is via "SAMBA" (rom)
271 // Selection is via gpnvm[2]
274 // NOTE: banks 0 & 1 switch places
276 // Bank0 is the boot rom
278 // Bank1 is the boot rom
287 .base_address = FLASH_BANK0_BASE,
288 .controller_address = 0x400e0800,
290 .size_bytes = 128 * 1024,
302 .base_address = FLASH_BANK1_BASE,
303 .controller_address = 0x400e0a00,
305 .size_bytes = 128 * 1024,
314 .chipid_cidr = 0x281a0760,
315 .name = "at91sam3u2e",
316 .total_flash_size = 128 * 1024,
317 .total_sram_size = 36 * 1024,
321 // System boots at address 0x0
322 // gpnvm[1] = selects boot code
324 // boot is via "SAMBA" (rom)
327 // Selection is via gpnvm[2]
336 .base_address = FLASH_BANK0_BASE,
337 .controller_address = 0x400e0800,
339 .size_bytes = 128 * 1024,
353 .chipid_cidr = 0x28190560,
354 .name = "at91sam3u1e",
355 .total_flash_size = 64 * 1024,
356 .total_sram_size = 20 * 1024,
360 // System boots at address 0x0
361 // gpnvm[1] = selects boot code
363 // boot is via "SAMBA" (rom)
366 // Selection is via gpnvm[2]
377 .base_address = FLASH_BANK0_BASE,
378 .controller_address = 0x400e0800,
380 .size_bytes = 64 * 1024,
396 .chipid_cidr = 0x28000960,
397 .name = "at91sam3u4c",
398 .total_flash_size = 256 * 1024,
399 .total_sram_size = 52 * 1024,
403 // System boots at address 0x0
404 // gpnvm[1] = selects boot code
406 // boot is via "SAMBA" (rom)
409 // Selection is via gpnvm[2]
412 // NOTE: banks 0 & 1 switch places
414 // Bank0 is the boot rom
416 // Bank1 is the boot rom
425 .base_address = FLASH_BANK0_BASE,
426 .controller_address = 0x400e0800,
428 .size_bytes = 128 * 1024,
439 .base_address = FLASH_BANK1_BASE,
440 .controller_address = 0x400e0a00,
442 .size_bytes = 128 * 1024,
451 .chipid_cidr = 0x280a0760,
452 .name = "at91sam3u2c",
453 .total_flash_size = 128 * 1024,
454 .total_sram_size = 36 * 1024,
458 // System boots at address 0x0
459 // gpnvm[1] = selects boot code
461 // boot is via "SAMBA" (rom)
464 // Selection is via gpnvm[2]
473 .base_address = FLASH_BANK0_BASE,
474 .controller_address = 0x400e0800,
476 .size_bytes = 128 * 1024,
490 .chipid_cidr = 0x28090560,
491 .name = "at91sam3u1c",
492 .total_flash_size = 64 * 1024,
493 .total_sram_size = 20 * 1024,
497 // System boots at address 0x0
498 // gpnvm[1] = selects boot code
500 // boot is via "SAMBA" (rom)
503 // Selection is via gpnvm[2]
514 .base_address = FLASH_BANK0_BASE,
515 .controller_address = 0x400e0800,
517 .size_bytes = 64 * 1024,
540 /***********************************************************************
541 **********************************************************************
542 **********************************************************************
543 **********************************************************************
544 **********************************************************************
545 **********************************************************************/
546 /* *ATMEL* style code - from the SAM3 driver code */
549 * Get the current status of the EEFC and
550 * the value of some status bits (LOCKE, PROGE).
551 * @param pPrivate - info about the bank
552 * @param v - result goes here
555 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
558 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
559 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
561 ((unsigned int)((*v >> 2) & 1)),
562 ((unsigned int)((*v >> 1) & 1)),
563 ((unsigned int)((*v >> 0) & 1)));
569 * Get the result of the last executed command.
570 * @param pPrivate - info about the bank
571 * @param v - result goes here
574 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
578 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
582 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
587 EFC_StartCommand(struct sam3_bank_private *pPrivate,
588 unsigned command, unsigned argument)
597 // Check command & argument
600 case AT91C_EFC_FCMD_WP:
601 case AT91C_EFC_FCMD_WPL:
602 case AT91C_EFC_FCMD_EWP:
603 case AT91C_EFC_FCMD_EWPL:
604 // case AT91C_EFC_FCMD_EPL:
605 // case AT91C_EFC_FCMD_EPA:
606 case AT91C_EFC_FCMD_SLB:
607 case AT91C_EFC_FCMD_CLB:
608 n = (pPrivate->size_bytes / pPrivate->page_size);
610 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
614 case AT91C_EFC_FCMD_SFB:
615 case AT91C_EFC_FCMD_CFB:
616 if (argument >= pPrivate->pChip->details.n_gpnvms) {
617 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
618 pPrivate->pChip->details.n_gpnvms);
622 case AT91C_EFC_FCMD_GETD:
623 case AT91C_EFC_FCMD_EA:
624 case AT91C_EFC_FCMD_GLB:
625 case AT91C_EFC_FCMD_GFB:
626 case AT91C_EFC_FCMD_STUI:
627 case AT91C_EFC_FCMD_SPUI:
629 LOG_ERROR("Argument is meaningless for cmd: %d", command);
633 LOG_ERROR("Unknown command %d", command);
637 if (command == AT91C_EFC_FCMD_SPUI) {
638 // this is a very special situation.
639 // Situation (1) - error/retry - see below
640 // And we are being called recursively
641 // Situation (2) - normal, finished reading unique id
643 // it should be "ready"
644 EFC_GetStatus(pPrivate, &v);
650 // we have done this before
651 // the controller is not responding.
652 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
656 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
657 pPrivate->bank_number);
658 // we do that by issuing the *STOP* command
659 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
660 // above is recursive, and further recursion is blocked by
661 // if (command == AT91C_EFC_FCMD_SPUI) above
667 v = (0x5A << 24) | (argument << 8) | command;
668 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
669 r = target_write_u32(pPrivate->pBank->target,
670 pPrivate->controller_address + offset_EFC_FCR,
673 LOG_DEBUG("Error Write failed");
679 * Performs the given command and wait until its completion (or an error).
680 * @param pPrivate - info about the bank
681 * @param command - Command to perform.
682 * @param argument - Optional command argument.
683 * @param status - put command status bits here
686 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
694 long long ms_now, ms_end;
701 r = EFC_StartCommand(pPrivate, command, argument);
706 ms_end = 500 + timeval_ms();
710 r = EFC_GetStatus(pPrivate, &v);
714 ms_now = timeval_ms();
715 if (ms_now > ms_end) {
717 LOG_ERROR("Command timeout");
737 * Read the unique ID.
738 * @param pPrivate - info about the bank
739 * The unique ID is stored in the 'pPrivate' structure.
742 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
748 pPrivate->pChip->cfg.unique_id[0] = 0;
749 pPrivate->pChip->cfg.unique_id[1] = 0;
750 pPrivate->pChip->cfg.unique_id[2] = 0;
751 pPrivate->pChip->cfg.unique_id[3] = 0;
754 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
759 for (x = 0 ; x < 4 ; x++) {
760 r = target_read_u32(pPrivate->pChip->target,
761 pPrivate->pBank->base + (x * 4),
766 pPrivate->pChip->cfg.unique_id[x] = v;
769 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
770 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
772 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
773 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
774 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
775 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
781 * Erases the entire flash.
782 * @param pPrivate - the info about the bank.
785 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
788 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
794 * Gets current GPNVM state.
795 * @param pPrivate - info about the bank.
796 * @param gpnvm - GPNVM bit index.
797 * @param puthere - result stored here.
799 //------------------------------------------------------------------------------
801 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
807 if (pPrivate->bank_number != 0) {
808 LOG_ERROR("GPNVM only works with Bank0");
812 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
813 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
814 gpnvm,pPrivate->pChip->details.n_gpnvms);
819 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
825 r = EFC_GetResult(pPrivate, &v);
828 // Check if GPNVM is set
829 // get the bit and make it a 0/1
830 *puthere = (v >> gpnvm) & 1;
840 * Clears the selected GPNVM bit.
841 * @param pPrivate info about the bank
842 * @param gpnvm GPNVM index.
843 * @returns 0 if successful; otherwise returns an error code.
846 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
852 if (pPrivate->bank_number != 0) {
853 LOG_ERROR("GPNVM only works with Bank0");
857 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
858 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
859 gpnvm,pPrivate->pChip->details.n_gpnvms);
863 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
865 LOG_DEBUG("Failed: %d",r);
868 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
869 LOG_DEBUG("End: %d",r);
876 * Sets the selected GPNVM bit.
877 * @param pPrivate info about the bank
878 * @param gpnvm GPNVM index.
881 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
886 if (pPrivate->bank_number != 0) {
887 LOG_ERROR("GPNVM only works with Bank0");
891 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
892 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
893 gpnvm,pPrivate->pChip->details.n_gpnvms);
897 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
906 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
913 * Returns a bit field (at most 64) of locked regions within a page.
914 * @param pPrivate info about the bank
915 * @param v where to store locked bits
918 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
922 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
924 r = EFC_GetResult(pPrivate, v);
926 LOG_DEBUG("End: %d",r);
932 * Unlocks all the regions in the given address range.
933 * @param pPrivate info about the bank
934 * @param start_sector first sector to unlock
935 * @param end_sector last (inclusive) to unlock
939 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
940 unsigned start_sector,
946 uint32_t pages_per_sector;
948 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
950 /* Unlock all pages */
951 while (start_sector <= end_sector) {
952 pg = start_sector * pages_per_sector;
954 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
967 * @param pPrivate - info about the bank
968 * @param start_sector - first sector to lock
969 * @param end_sector - last sector (inclusive) to lock
972 FLASHD_Lock(struct sam3_bank_private *pPrivate,
973 unsigned start_sector,
978 uint32_t pages_per_sector;
981 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
984 while (start_sector <= end_sector) {
985 pg = start_sector * pages_per_sector;
987 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
997 /****** END SAM3 CODE ********/
999 /* begin helpful debug code */
1000 // print the fieldname, the field value, in dec & hex, and return field value
1002 sam3_reg_fieldname(struct sam3_chip *pChip,
1003 const char *regname,
1012 // extract the field
1014 v = v & ((1 << width)-1);
1024 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1025 REG_NAME_WIDTH, regname,
1032 static const char _unknown[] = "unknown";
1033 static const char * const eproc_names[] = {
1052 #define nvpsize2 nvpsize // these two tables are identical
1053 static const char * const nvpsize[] = {
1066 "1024K bytes", // 12
1068 "2048K bytes", // 14
1073 static const char * const sramsize[] = {
1093 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1094 { 0x19, "AT91SAM9xx Series" },
1095 { 0x29, "AT91SAM9XExx Series" },
1096 { 0x34, "AT91x34 Series" },
1097 { 0x37, "CAP7 Series" },
1098 { 0x39, "CAP9 Series" },
1099 { 0x3B, "CAP11 Series" },
1100 { 0x40, "AT91x40 Series" },
1101 { 0x42, "AT91x42 Series" },
1102 { 0x55, "AT91x55 Series" },
1103 { 0x60, "AT91SAM7Axx Series" },
1104 { 0x61, "AT91SAM7AQxx Series" },
1105 { 0x63, "AT91x63 Series" },
1106 { 0x70, "AT91SAM7Sxx Series" },
1107 { 0x71, "AT91SAM7XCxx Series" },
1108 { 0x72, "AT91SAM7SExx Series" },
1109 { 0x73, "AT91SAM7Lxx Series" },
1110 { 0x75, "AT91SAM7Xxx Series" },
1111 { 0x76, "AT91SAM7SLxx Series" },
1112 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1113 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1114 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1115 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1116 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1117 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1118 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1119 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1120 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1121 { 0x92, "AT91x92 Series" },
1122 { 0xF0, "AT75Cxx Series" },
1127 static const char * const nvptype[] = {
1129 "romless or onchip flash", // 1
1130 "embedded flash memory", // 2
1131 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1132 "sram emulating flash", // 4
1139 static const char *_yes_or_no(uint32_t v)
1148 static const char * const _rc_freq[] = {
1149 "4 MHz", "8 MHz", "12 MHz", "reserved"
1153 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1158 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1159 LOG_USER_N("(main xtal enabled: %s)\n",
1161 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1162 LOG_USER_N("(main osc bypass: %s)\n",
1164 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1165 LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
1167 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1168 LOG_USER_N("(onchip RC-OSC freq: %s)\n",
1171 pChip->cfg.rc_freq = 0;
1175 pChip->cfg.rc_freq = 0;
1177 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1180 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1183 pChip->cfg.rc_freq = 12* 1000 * 1000;
1188 v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1189 LOG_USER_N("(startup clks, time= %f uSecs)\n",
1190 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1191 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1192 LOG_USER_N("(mainosc source: %s)\n",
1193 v ? "external xtal" : "internal RC");
1195 v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1196 LOG_USER_N("(clock failure enabled: %s)\n",
1203 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1209 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1212 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1213 LOG_USER_N("%s\n", eproc_names[v]);
1215 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1216 LOG_USER_N("%s\n", nvpsize[v]);
1218 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1219 LOG_USER_N("%s\n", nvpsize2[v]);
1221 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1222 LOG_USER_N("%s\n", sramsize[ v ]);
1224 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1226 for (x = 0 ; archnames[x].name ; x++) {
1227 if (v == archnames[x].value) {
1228 cp = archnames[x].name;
1233 LOG_USER_N("%s\n", cp);
1235 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1236 LOG_USER_N("%s\n", nvptype[ v ]);
1238 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1239 LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
1243 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1248 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1249 LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
1251 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1253 v = (v * pChip->cfg.slow_freq) / 16;
1254 pChip->cfg.mainosc_freq = v;
1256 LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1258 pChip->cfg.slow_freq / 1000,
1259 pChip->cfg.slow_freq % 1000);
1264 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1268 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1270 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1272 pChip->cfg.plla_freq = 0;
1274 LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
1275 } else if (diva == 0) {
1276 LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
1277 } else if (diva == 1) {
1278 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1279 LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
1280 _tomhz(pChip->cfg.plla_freq));
1286 sam3_explain_mckr(struct sam3_chip *pChip)
1288 uint32_t css, pres, fin = 0;
1290 const char *cp = NULL;
1292 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1295 fin = pChip->cfg.slow_freq;
1299 fin = pChip->cfg.mainosc_freq;
1303 fin = pChip->cfg.plla_freq;
1307 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1308 fin = 480 * 1000 * 1000;
1312 cp = "upll (*ERROR* UPLL is disabled)";
1320 LOG_USER_N("%s (%3.03f Mhz)\n",
1323 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1324 switch (pres & 0x07) {
1327 cp = "selected clock";
1360 LOG_USER_N("(%s)\n", cp);
1362 // sam3 has a *SINGLE* clock -
1363 // other at91 series parts have divisors for these.
1364 pChip->cfg.cpu_freq = fin;
1365 pChip->cfg.mclk_freq = fin;
1366 pChip->cfg.fclk_freq = fin;
1367 LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
1372 static struct sam3_chip *
1373 target2sam3(struct target *pTarget)
1375 struct sam3_chip *pChip;
1377 if (pTarget == NULL) {
1381 pChip = all_sam3_chips;
1383 if (pChip->target == pTarget) {
1384 break; // return below
1386 pChip = pChip->next;
1394 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1396 // this function exists to help
1397 // keep funky offsetof() errors
1398 // and casting from causing bugs
1400 // By using prototypes - we can detect what would
1401 // be casting errors.
1403 return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
1407 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1408 static const struct sam3_reg_list sam3_all_regs[] = {
1409 SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1410 SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1411 SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1412 SAM3_ENTRY(CKGR_UCKR , NULL),
1413 SAM3_ENTRY(PMC_FSMR , NULL),
1414 SAM3_ENTRY(PMC_FSPR , NULL),
1415 SAM3_ENTRY(PMC_IMR , NULL),
1416 SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1417 SAM3_ENTRY(PMC_PCK0 , NULL),
1418 SAM3_ENTRY(PMC_PCK1 , NULL),
1419 SAM3_ENTRY(PMC_PCK2 , NULL),
1420 SAM3_ENTRY(PMC_PCSR , NULL),
1421 SAM3_ENTRY(PMC_SCSR , NULL),
1422 SAM3_ENTRY(PMC_SR , NULL),
1423 SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1424 SAM3_ENTRY(CHIPID_EXID , NULL),
1425 SAM3_ENTRY(SUPC_CR, NULL),
1427 // TERMINATE THE LIST
1435 static struct sam3_bank_private *
1436 get_sam3_bank_private(struct flash_bank *bank)
1438 return (struct sam3_bank_private *)(bank->driver_priv);
1442 * Given a pointer to where it goes in the structure,
1443 * determine the register name, address from the all registers table.
1445 static const struct sam3_reg_list *
1446 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1448 const struct sam3_reg_list *pReg;
1450 pReg = &(sam3_all_regs[0]);
1451 while (pReg->name) {
1452 uint32_t *pPossible;
1454 // calculate where this one go..
1455 // it is "possibly" this register.
1457 pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1459 // well? Is it this register
1460 if (pPossible == goes_here) {
1468 // This is *TOTAL*PANIC* - we are totally screwed.
1469 LOG_ERROR("INVALID SAM3 REGISTER");
1475 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1477 const struct sam3_reg_list *pReg;
1480 pReg = sam3_GetReg(pChip, goes_here);
1485 r = target_read_u32(pChip->target, pReg->address, goes_here);
1486 if (r != ERROR_OK) {
1487 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1488 pReg->name, (unsigned)(pReg->address), r);
1496 sam3_ReadAllRegs(struct sam3_chip *pChip)
1499 const struct sam3_reg_list *pReg;
1501 pReg = &(sam3_all_regs[0]);
1502 while (pReg->name) {
1503 r = sam3_ReadThisReg(pChip,
1504 sam3_get_reg_ptr(&(pChip->cfg), pReg));
1505 if (r != ERROR_OK) {
1506 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1507 pReg->name, ((unsigned)(pReg->address)), r);
1519 sam3_GetInfo(struct sam3_chip *pChip)
1521 const struct sam3_reg_list *pReg;
1524 pReg = &(sam3_all_regs[0]);
1525 while (pReg->name) {
1527 LOG_DEBUG("Start: %s", pReg->name);
1528 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1529 LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
1534 if (pReg->explain_func) {
1535 (*(pReg->explain_func))(pChip);
1537 LOG_DEBUG("End: %s", pReg->name);
1540 LOG_USER_N(" rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1541 LOG_USER_N(" mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1542 LOG_USER_N(" plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1543 LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1544 LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1547 LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1548 pChip->cfg.unique_id[0],
1549 pChip->cfg.unique_id[1],
1550 pChip->cfg.unique_id[2],
1551 pChip->cfg.unique_id[3]);
1559 sam3_erase_check(struct flash_bank *bank)
1564 if (bank->target->state != TARGET_HALTED) {
1565 LOG_ERROR("Target not halted");
1566 return ERROR_TARGET_NOT_HALTED;
1568 if (0 == bank->num_sectors) {
1569 LOG_ERROR("Target: not supported/not probed\n");
1573 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1574 for (x = 0 ; x < bank->num_sectors ; x++) {
1575 bank->sectors[x].is_erased = 1;
1583 sam3_protect_check(struct flash_bank *bank)
1588 struct sam3_bank_private *pPrivate;
1591 if (bank->target->state != TARGET_HALTED) {
1592 LOG_ERROR("Target not halted");
1593 return ERROR_TARGET_NOT_HALTED;
1596 pPrivate = get_sam3_bank_private(bank);
1598 LOG_ERROR("no private for this bank?");
1601 if (!(pPrivate->probed)) {
1602 return ERROR_FLASH_BANK_NOT_PROBED;
1605 r = FLASHD_GetLockBits(pPrivate , &v);
1606 if (r != ERROR_OK) {
1607 LOG_DEBUG("Failed: %d",r);
1611 for (x = 0 ; x < pPrivate->nsectors ; x++) {
1612 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1618 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
1620 struct sam3_chip *pChip;
1622 pChip = all_sam3_chips;
1624 // is this an existing chip?
1626 if (pChip->target == bank->target) {
1629 pChip = pChip->next;
1633 // this is a *NEW* chip
1634 pChip = calloc(1, sizeof(struct sam3_chip));
1636 LOG_ERROR("NO RAM!");
1639 pChip->target = bank->target;
1641 pChip->next = all_sam3_chips;
1642 all_sam3_chips = pChip;
1643 pChip->target = bank->target;
1644 // assumption is this runs at 32khz
1645 pChip->cfg.slow_freq = 32768;
1649 switch (bank->base) {
1651 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1652 ((unsigned int)(bank->base)),
1653 ((unsigned int)(FLASH_BANK0_BASE)),
1654 ((unsigned int)(FLASH_BANK1_BASE)));
1657 case FLASH_BANK0_BASE:
1658 bank->driver_priv = &(pChip->details.bank[0]);
1659 bank->bank_number = 0;
1660 pChip->details.bank[0].pChip = pChip;
1661 pChip->details.bank[0].pBank = bank;
1663 case FLASH_BANK1_BASE:
1664 bank->driver_priv = &(pChip->details.bank[1]);
1665 bank->bank_number = 1;
1666 pChip->details.bank[1].pChip = pChip;
1667 pChip->details.bank[1].pBank = bank;
1671 // we initialize after probing.
1676 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1678 const struct sam3_chip_details *pDetails;
1679 struct sam3_chip *pChip;
1680 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
1684 pDetails = all_sam3_details;
1685 while (pDetails->name) {
1686 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
1692 if (pDetails->name == NULL) {
1693 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1694 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1695 // Help the victim, print details about the chip
1696 LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1697 pPrivate->pChip->cfg.CHIPID_CIDR);
1698 sam3_explain_chipid_cidr(pPrivate->pChip);
1702 // DANGER: THERE ARE DRAGONS HERE
1704 // get our pChip - it is going
1705 // to be over-written shortly
1706 pChip = pPrivate->pChip;
1708 // Note that, in reality:
1710 // pPrivate = &(pChip->details.bank[0])
1711 // or pPrivate = &(pChip->details.bank[1])
1714 // save the "bank" pointers
1715 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1716 saved_banks[ x ] = pChip->details.bank[x].pBank;
1719 // Overwrite the "details" structure.
1720 memcpy(&(pPrivate->pChip->details),
1722 sizeof(pPrivate->pChip->details));
1724 // now fix the ghosted pointers
1725 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1726 pChip->details.bank[x].pChip = pChip;
1727 pChip->details.bank[x].pBank = saved_banks[x];
1730 // update the *BANK*SIZE*
1739 _sam3_probe(struct flash_bank *bank, int noise)
1743 struct sam3_bank_private *pPrivate;
1746 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1747 if (bank->target->state != TARGET_HALTED)
1749 LOG_ERROR("Target not halted");
1750 return ERROR_TARGET_NOT_HALTED;
1753 pPrivate = get_sam3_bank_private(bank);
1755 LOG_ERROR("Invalid/unknown bank number\n");
1759 r = sam3_ReadAllRegs(pPrivate->pChip);
1760 if (r != ERROR_OK) {
1766 if (pPrivate->pChip->probed) {
1767 r = sam3_GetInfo(pPrivate->pChip);
1769 r = sam3_GetDetails(pPrivate);
1771 if (r != ERROR_OK) {
1775 // update the flash bank size
1776 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1777 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
1778 bank->size = pPrivate->pChip->details.bank[0].size_bytes;
1783 if (bank->sectors == NULL) {
1784 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1785 if (bank->sectors == NULL) {
1786 LOG_ERROR("No memory!");
1789 bank->num_sectors = pPrivate->nsectors;
1791 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
1792 bank->sectors[x].size = pPrivate->sector_size;
1793 bank->sectors[x].offset = x * (pPrivate->sector_size);
1795 bank->sectors[x].is_erased = -1;
1796 bank->sectors[x].is_protected = -1;
1800 pPrivate->probed = 1;
1802 r = sam3_protect_check(bank);
1803 if (r != ERROR_OK) {
1807 LOG_DEBUG("Bank = %d, nbanks = %d",
1808 pPrivate->bank_number , pPrivate->pChip->details.n_banks);
1809 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1811 // it appears to be associated with the *last* flash bank.
1812 FLASHD_ReadUniqueID(pPrivate);
1819 sam3_probe(struct flash_bank *bank)
1821 return _sam3_probe(bank, 1);
1825 sam3_auto_probe(struct flash_bank *bank)
1827 return _sam3_probe(bank, 0);
1833 sam3_erase(struct flash_bank *bank, int first, int last)
1835 struct sam3_bank_private *pPrivate;
1839 if (bank->target->state != TARGET_HALTED) {
1840 LOG_ERROR("Target not halted");
1841 return ERROR_TARGET_NOT_HALTED;
1844 r = sam3_auto_probe(bank);
1845 if (r != ERROR_OK) {
1846 LOG_DEBUG("Here,r=%d",r);
1850 pPrivate = get_sam3_bank_private(bank);
1851 if (!(pPrivate->probed)) {
1852 return ERROR_FLASH_BANK_NOT_PROBED;
1855 if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
1858 return FLASHD_EraseEntireBank(pPrivate);
1860 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1865 sam3_protect(struct flash_bank *bank, int set, int first, int last)
1867 struct sam3_bank_private *pPrivate;
1871 if (bank->target->state != TARGET_HALTED) {
1872 LOG_ERROR("Target not halted");
1873 return ERROR_TARGET_NOT_HALTED;
1876 pPrivate = get_sam3_bank_private(bank);
1877 if (!(pPrivate->probed)) {
1878 return ERROR_FLASH_BANK_NOT_PROBED;
1882 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1884 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1886 LOG_DEBUG("End: r=%d",r);
1894 sam3_info(struct flash_bank *bank, char *buf, int buf_size)
1896 if (bank->target->state != TARGET_HALTED) {
1897 LOG_ERROR("Target not halted");
1898 return ERROR_TARGET_NOT_HALTED;
1905 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1910 adr = pagenum * pPrivate->page_size;
1911 adr += adr + pPrivate->base_address;
1913 r = target_read_memory(pPrivate->pChip->target,
1915 4, /* THIS*MUST*BE* in 32bit values */
1916 pPrivate->page_size / 4,
1918 if (r != ERROR_OK) {
1919 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
1924 // The code below is basically this:
1926 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
1928 // Only the *CPU* can write to the flash buffer.
1929 // the DAP cannot... so - we download this 28byte thing
1930 // Run the algorithm - (below)
1931 // to program the device
1933 // ========================================
1934 // #include <stdint.h>
1938 // const uint32_t *src;
1940 // volatile uint32_t *base;
1945 // uint32_t sam3_function(struct foo *p)
1947 // volatile uint32_t *v;
1949 // const uint32_t *s;
1971 // ========================================
1975 static const uint8_t
1976 sam3_page_write_opcodes[] = {
1977 // 24 0000 0446 mov r4, r0
1979 // 25 0002 6168 ldr r1, [r4, #4]
1981 // 26 0004 0068 ldr r0, [r0, #0]
1983 // 27 0006 A268 ldr r2, [r4, #8]
1985 // 28 @ lr needed for prologue
1987 // 30 0008 51F8043B ldr r3, [r1], #4
1988 0x51,0xf8,0x04,0x3b,
1989 // 31 000c 12F1FF32 adds r2, r2, #-1
1990 0x12,0xf1,0xff,0x32,
1991 // 32 0010 40F8043B str r3, [r0], #4
1992 0x40,0xf8,0x04,0x3b,
1993 // 33 0014 F8D1 bne .L2
1995 // 34 0016 E268 ldr r2, [r4, #12]
1997 // 35 0018 2369 ldr r3, [r4, #16]
1999 // 36 001a 5360 str r3, [r2, #4]
2001 // 37 001c 0832 adds r2, r2, #8
2004 // 39 001e 1068 ldr r0, [r2, #0]
2006 // 40 0020 10F0010F tst r0, #1
2007 0x10,0xf0,0x01,0x0f,
2008 // 41 0024 FBD0 beq .L4
2010 0x00,0xBE /* bkpt #0 */
2015 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2021 adr = pagenum * pPrivate->page_size;
2022 adr += (adr + pPrivate->base_address);
2024 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2025 r = target_write_memory(pPrivate->pChip->target,
2027 4, /* THIS*MUST*BE* in 32bit values */
2028 pPrivate->page_size / 4,
2030 if (r != ERROR_OK) {
2031 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2035 r = EFC_PerformCommand(pPrivate,
2036 // send Erase & Write Page
2041 if (r != ERROR_OK) {
2042 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2044 if (status & (1 << 2)) {
2045 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2048 if (status & (1 << 1)) {
2049 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2060 sam3_write(struct flash_bank *bank,
2069 unsigned page_offset;
2070 struct sam3_bank_private *pPrivate;
2071 uint8_t *pagebuffer;
2073 // incase we bail further below, set this to null
2076 // ignore dumb requests
2082 if (bank->target->state != TARGET_HALTED) {
2083 LOG_ERROR("Target not halted");
2084 r = ERROR_TARGET_NOT_HALTED;
2088 pPrivate = get_sam3_bank_private(bank);
2089 if (!(pPrivate->probed)) {
2090 r = ERROR_FLASH_BANK_NOT_PROBED;
2095 if ((offset + count) > pPrivate->size_bytes) {
2096 LOG_ERROR("Flash write error - past end of bank");
2097 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2098 (unsigned int)(offset),
2099 (unsigned int)(count),
2100 (unsigned int)(pPrivate->size_bytes));
2105 pagebuffer = malloc(pPrivate->page_size);
2107 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2112 // what page do we start & end in?
2113 page_cur = offset / pPrivate->page_size;
2114 page_end = (offset + count - 1) / pPrivate->page_size;
2116 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2117 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2119 // Special case: all one page
2122 // (1) non-aligned start
2124 // (3) non-aligned end.
2126 // Handle special case - all one page.
2127 if (page_cur == page_end) {
2128 LOG_DEBUG("Special case, all in one page");
2129 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2130 if (r != ERROR_OK) {
2134 page_offset = (offset & (pPrivate->page_size-1));
2135 memcpy(pagebuffer + page_offset,
2139 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2140 if (r != ERROR_OK) {
2147 // non-aligned start
2148 page_offset = offset & (pPrivate->page_size - 1);
2150 LOG_DEBUG("Not-Aligned start");
2152 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2153 if (r != ERROR_OK) {
2157 // over-write with new data
2158 n = (pPrivate->page_size - page_offset);
2159 memcpy(pagebuffer + page_offset,
2163 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2164 if (r != ERROR_OK) {
2174 // intermediate large pages
2175 // also - the final *terminal*
2176 // if that terminal page is a full page
2177 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2178 (int)page_cur, (int)page_end, (unsigned int)(count));
2180 while ((page_cur < page_end) &&
2181 (count >= pPrivate->page_size)) {
2182 r = sam3_page_write(pPrivate, page_cur, buffer);
2183 if (r != ERROR_OK) {
2186 count -= pPrivate->page_size;
2187 buffer += pPrivate->page_size;
2191 // terminal partial page?
2193 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2194 // we have a partial page
2195 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2196 if (r != ERROR_OK) {
2199 // data goes at start
2200 memcpy(pagebuffer, buffer, count);
2201 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2202 if (r != ERROR_OK) {
2217 COMMAND_HANDLER(sam3_handle_info_command)
2219 struct sam3_chip *pChip;
2223 pChip = get_current_sam3(CMD_CTX);
2230 // bank0 must exist before we can do anything
2231 if (pChip->details.bank[0].pBank == NULL) {
2234 command_print(CMD_CTX,
2235 "Please define bank %d via command: flash bank %s ... ",
2237 at91sam3_flash.name);
2241 // if bank 0 is not probed, then probe it
2242 if (!(pChip->details.bank[0].probed)) {
2243 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2244 if (r != ERROR_OK) {
2248 // above guarantees the "chip details" structure is valid
2249 // and thus, bank private areas are valid
2250 // and we have a SAM3 chip, what a concept!
2253 // auto-probe other banks, 0 done above
2254 for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2255 // skip banks not present
2256 if (!(pChip->details.bank[x].present)) {
2260 if (pChip->details.bank[x].pBank == NULL) {
2264 if (pChip->details.bank[x].probed) {
2268 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2269 if (r != ERROR_OK) {
2275 r = sam3_GetInfo(pChip);
2276 if (r != ERROR_OK) {
2277 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2284 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2288 struct sam3_chip *pChip;
2290 pChip = get_current_sam3(CMD_CTX);
2295 if (pChip->target->state != TARGET_HALTED) {
2296 LOG_ERROR("sam3 - target not halted");
2297 return ERROR_TARGET_NOT_HALTED;
2301 if (pChip->details.bank[0].pBank == NULL) {
2302 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2303 at91sam3_flash.name);
2306 if (!pChip->details.bank[0].probed) {
2307 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2308 if (r != ERROR_OK) {
2316 command_print(CMD_CTX,"Too many parameters\n");
2317 return ERROR_COMMAND_SYNTAX_ERROR;
2327 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) {
2331 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2337 if (0 == strcmp("show", CMD_ARGV[0])) {
2341 for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2342 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2343 if (r != ERROR_OK) {
2346 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
2350 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2351 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2352 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
2355 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
2356 return ERROR_COMMAND_SYNTAX_ERROR;
2361 command_print(CMD_CTX, "Missing GPNVM number");
2362 return ERROR_COMMAND_SYNTAX_ERROR;
2365 if (0 == strcmp("set", CMD_ARGV[0])) {
2366 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2367 } else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2368 (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
2369 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2371 command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
2372 r = ERROR_COMMAND_SYNTAX_ERROR;
2377 COMMAND_HANDLER(sam3_handle_slowclk_command)
2379 struct sam3_chip *pChip;
2381 pChip = get_current_sam3(CMD_CTX);
2395 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2397 // absurd slow clock of 200Khz?
2398 command_print(CMD_CTX,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2399 return ERROR_COMMAND_SYNTAX_ERROR;
2401 pChip->cfg.slow_freq = v;
2406 command_print(CMD_CTX,"Too many parameters");
2407 return ERROR_COMMAND_SYNTAX_ERROR;
2410 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2411 (int)(pChip->cfg.slow_freq/ 1000),
2412 (int)(pChip->cfg.slow_freq% 1000));
2416 static const struct command_registration at91sam3_exec_command_handlers[] = {
2419 .handler = sam3_handle_gpnvm_command,
2420 .mode = COMMAND_EXEC,
2421 .usage = "[('clr'|'set'|'show') bitnum]",
2422 .help = "Without arguments, shows all bits in the gpnvm "
2423 "register. Otherwise, clears, sets, or shows one "
2424 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2428 .handler = sam3_handle_info_command,
2429 .mode = COMMAND_EXEC,
2430 .help = "Print information about the current at91sam3 chip"
2431 "and its flash configuration.",
2435 .handler = sam3_handle_slowclk_command,
2436 .mode = COMMAND_EXEC,
2437 .usage = "[clock_hz]",
2438 .help = "Display or set the slowclock frequency "
2439 "(default 32768 Hz).",
2441 COMMAND_REGISTRATION_DONE
2443 static const struct command_registration at91sam3_command_handlers[] = {
2446 .mode = COMMAND_ANY,
2447 .help = "at91sam3 flash command group",
2448 .chain = at91sam3_exec_command_handlers,
2450 COMMAND_REGISTRATION_DONE
2453 struct flash_driver at91sam3_flash = {
2455 .commands = at91sam3_command_handlers,
2456 .flash_bank_command = sam3_flash_bank_command,
2457 .erase = sam3_erase,
2458 .protect = sam3_protect,
2459 .write = sam3_write,
2460 .read = default_flash_read,
2461 .probe = sam3_probe,
2462 .auto_probe = sam3_auto_probe,
2463 .erase_check = sam3_erase_check,
2464 .protect_check = sam3_protect_check,