1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
19 * GNU General public License for more details. *
21 * You should have received a copy of the GNU General public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ****************************************************************************/
27 /* Some of the the lower level code was based on code supplied by
28 * ATMEL under this copyright. */
30 /* BEGIN ATMEL COPYRIGHT */
31 /* ----------------------------------------------------------------------------
32 * ATMEL Microcontroller Software Support
33 * ----------------------------------------------------------------------------
34 * Copyright (c) 2009, Atmel Corporation
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
41 * - Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the disclaimer below.
44 * Atmel's name may not be used to endorse or promote products derived from
45 * this software without specific prior written permission.
47 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
50 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
53 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
56 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ----------------------------------------------------------------------------
59 /* END ATMEL COPYRIGHT */
66 #include <helper/time_support.h>
68 #define REG_NAME_WIDTH (12)
70 /* at91sam4s/at91sam4e series (has always one flash bank)*/
71 #define FLASH_BANK_BASE_S 0x00400000
73 /* at91sam4sd series (two one flash banks), first bank address */
74 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
75 /* at91sam4sd16x, second bank address */
76 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
77 /* at91sam4sd32x, second bank address */
78 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
80 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
81 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
82 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
83 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
84 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
85 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
86 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
87 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
88 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
103 extern struct flash_driver at91sam4_flash;
105 static float _tomhz(uint32_t freq_hz)
109 f = ((float)(freq_hz)) / 1000000.0;
113 /* How the chip is configured. */
115 uint32_t unique_id[4];
119 uint32_t mainosc_freq;
129 #define SAM4_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR;
131 #define SAM4_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID;
134 #define SAM4_PMC_BASE (0x400E0400)
135 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
137 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
139 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
141 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
143 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
145 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
147 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
149 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
151 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
153 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
155 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
157 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
159 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
161 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 struct sam4_bank_private {
167 /* DANGER: THERE ARE DRAGONS HERE.. */
168 /* NOTE: If you add more 'ghost' pointers */
169 /* be aware that you must *manually* update */
170 /* these pointers in the function sam4_GetDetails() */
171 /* See the comment "Here there be dragons" */
173 /* so we can find the chip we belong to */
174 struct sam4_chip *pChip;
175 /* so we can find the original bank pointer */
176 struct flash_bank *pBank;
177 unsigned bank_number;
178 uint32_t controller_address;
179 uint32_t base_address;
180 uint32_t flash_wait_states;
184 unsigned sector_size;
188 struct sam4_chip_details {
189 /* THERE ARE DRAGONS HERE.. */
190 /* note: If you add pointers here */
191 /* be careful about them as they */
192 /* may need to be updated inside */
193 /* the function: "sam4_GetDetails() */
194 /* which copy/overwrites the */
195 /* 'runtime' copy of this structure */
196 uint32_t chipid_cidr;
200 #define SAM4_N_NVM_BITS 3
201 unsigned gpnvm[SAM4_N_NVM_BITS];
202 unsigned total_flash_size;
203 unsigned total_sram_size;
205 #define SAM4_MAX_FLASH_BANKS 2
206 /* these are "initialized" from the global const data */
207 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
211 struct sam4_chip *next;
214 /* this is "initialized" from the global const structure */
215 struct sam4_chip_details details;
216 struct target *target;
221 struct sam4_reg_list {
222 uint32_t address; size_t struct_offset; const char *name;
223 void (*explain_func)(struct sam4_chip *pInfo);
226 static struct sam4_chip *all_sam4_chips;
228 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
231 static struct sam4_chip *p;
233 t = get_current_target(cmd_ctx);
235 command_print(cmd_ctx, "No current target?");
241 /* this should not happen */
242 /* the command is not registered until the chip is created? */
243 command_print(cmd_ctx, "No SAM4 chips exist?");
252 command_print(cmd_ctx, "Cannot find SAM4 chip?");
256 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
257 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
258 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
259 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
261 /* these are used to *initialize* the "pChip->details" structure. */
262 static const struct sam4_chip_details all_sam4_details[] = {
264 /* Start at91sam4e* series */
265 /*atsam4e16e - LQFP144/LFBGA144*/
267 .chipid_cidr = 0xA3CC0CE0,
268 .name = "at91sam4e16e",
269 .total_flash_size = 1024 * 1024,
270 .total_sram_size = 128 * 1024,
280 .base_address = FLASH_BANK_BASE_S,
281 .controller_address = 0x400e0a00,
282 .flash_wait_states = 6, /* workaround silicon bug */
284 .size_bytes = 1024 * 1024,
299 /* Start at91sam4n* series */
300 /*atsam4n8a - LQFP48/QFN48*/
302 .chipid_cidr = 0x293B0AE0,
303 .name = "at91sam4n8a",
304 .total_flash_size = 512 * 1024,
305 .total_sram_size = 64 * 1024,
315 .base_address = FLASH_BANK_BASE_S,
316 .controller_address = 0x400e0a00,
317 .flash_wait_states = 6, /* workaround silicon bug */
319 .size_bytes = 512 * 1024,
333 /*atsam4n8b - LQFP64/QFN64*/
335 .chipid_cidr = 0x294B0AE0,
336 .name = "at91sam4n8b",
337 .total_flash_size = 512 * 1024,
338 .total_sram_size = 64 * 1024,
348 .base_address = FLASH_BANK_BASE_S,
349 .controller_address = 0x400e0a00,
350 .flash_wait_states = 6, /* workaround silicon bug */
352 .size_bytes = 512 * 1024,
366 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
368 .chipid_cidr = 0x295B0AE0,
369 .name = "at91sam4n8c",
370 .total_flash_size = 512 * 1024,
371 .total_sram_size = 64 * 1024,
381 .base_address = FLASH_BANK_BASE_S,
382 .controller_address = 0x400e0a00,
383 .flash_wait_states = 6, /* workaround silicon bug */
385 .size_bytes = 512 * 1024,
399 /*atsam4n16b - LQFP64/QFN64*/
401 .chipid_cidr = 0x29460CE0,
402 .name = "at91sam4n16b",
403 .total_flash_size = 1024 * 1024,
404 .total_sram_size = 80 * 1024,
414 .base_address = FLASH_BANK_BASE_S,
415 .controller_address = 0x400e0a00,
416 .flash_wait_states = 6, /* workaround silicon bug */
418 .size_bytes = 1024 * 1024,
432 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
434 .chipid_cidr = 0x29560CE0,
435 .name = "at91sam4n16c",
436 .total_flash_size = 1024 * 1024,
437 .total_sram_size = 80 * 1024,
447 .base_address = FLASH_BANK_BASE_S,
448 .controller_address = 0x400e0a00,
449 .flash_wait_states = 6, /* workaround silicon bug */
451 .size_bytes = 1024 * 1024,
466 /* Start at91sam4s* series */
467 /*atsam4s16c - LQFP100/BGA100*/
469 .chipid_cidr = 0x28AC0CE0,
470 .name = "at91sam4s16c",
471 .total_flash_size = 1024 * 1024,
472 .total_sram_size = 128 * 1024,
482 .base_address = FLASH_BANK_BASE_S,
483 .controller_address = 0x400e0a00,
484 .flash_wait_states = 6, /* workaround silicon bug */
486 .size_bytes = 1024 * 1024,
500 /*atsam4s16b - LQFP64/QFN64*/
502 .chipid_cidr = 0x289C0CE0,
503 .name = "at91sam4s16b",
504 .total_flash_size = 1024 * 1024,
505 .total_sram_size = 128 * 1024,
515 .base_address = FLASH_BANK_BASE_S,
516 .controller_address = 0x400e0a00,
517 .flash_wait_states = 6, /* workaround silicon bug */
519 .size_bytes = 1024 * 1024,
533 /*atsam4sa16b - LQFP64/QFN64*/
535 .chipid_cidr = 0x28970CE0,
536 .name = "at91sam4sa16b",
537 .total_flash_size = 1024 * 1024,
538 .total_sram_size = 160 * 1024,
548 .base_address = FLASH_BANK_BASE_S,
549 .controller_address = 0x400e0a00,
550 .flash_wait_states = 6, /* workaround silicon bug */
552 .size_bytes = 1024 * 1024,
566 /*atsam4s16a - LQFP48/QFN48*/
568 .chipid_cidr = 0x288C0CE0,
569 .name = "at91sam4s16a",
570 .total_flash_size = 1024 * 1024,
571 .total_sram_size = 128 * 1024,
581 .base_address = FLASH_BANK_BASE_S,
582 .controller_address = 0x400e0a00,
583 .flash_wait_states = 6, /* workaround silicon bug */
585 .size_bytes = 1024 * 1024,
599 /*atsam4s8c - LQFP100/BGA100*/
601 .chipid_cidr = 0x28AC0AE0,
602 .name = "at91sam4s8c",
603 .total_flash_size = 512 * 1024,
604 .total_sram_size = 128 * 1024,
614 .base_address = FLASH_BANK_BASE_S,
615 .controller_address = 0x400e0a00,
616 .flash_wait_states = 6, /* workaround silicon bug */
618 .size_bytes = 512 * 1024,
632 /*atsam4s8b - LQFP64/BGA64*/
634 .chipid_cidr = 0x289C0AE0,
635 .name = "at91sam4s8b",
636 .total_flash_size = 512 * 1024,
637 .total_sram_size = 128 * 1024,
647 .base_address = FLASH_BANK_BASE_S,
648 .controller_address = 0x400e0a00,
649 .flash_wait_states = 6, /* workaround silicon bug */
651 .size_bytes = 512 * 1024,
665 /*atsam4s8a - LQFP48/BGA48*/
667 .chipid_cidr = 0x288C0AE0,
668 .name = "at91sam4s8a",
669 .total_flash_size = 512 * 1024,
670 .total_sram_size = 128 * 1024,
680 .base_address = FLASH_BANK_BASE_S,
681 .controller_address = 0x400e0a00,
682 .flash_wait_states = 6, /* workaround silicon bug */
684 .size_bytes = 512 * 1024,
699 /*atsam4s4a - LQFP48/BGA48*/
701 .chipid_cidr = 0x288b09e0,
702 .name = "at91sam4s4a",
703 .total_flash_size = 256 * 1024,
704 .total_sram_size = 64 * 1024,
714 .base_address = FLASH_BANK_BASE_S,
715 .controller_address = 0x400e0a00,
716 .flash_wait_states = 6, /* workaround silicon bug */
718 .size_bytes = 256 * 1024,
735 .chipid_cidr = 0x29a70ee0,
736 .name = "at91sam4sd32c",
737 .total_flash_size = 2048 * 1024,
738 .total_sram_size = 160 * 1024,
749 .base_address = FLASH_BANK0_BASE_SD,
750 .controller_address = 0x400e0a00,
751 .flash_wait_states = 6, /* workaround silicon bug */
753 .size_bytes = 1024 * 1024,
765 .base_address = FLASH_BANK1_BASE_2048K_SD,
766 .controller_address = 0x400e0c00,
767 .flash_wait_states = 6, /* workaround silicon bug */
769 .size_bytes = 1024 * 1024,
779 .chipid_cidr = 0x29a70ce0,
780 .name = "at91sam4sd16c",
781 .total_flash_size = 1024 * 1024,
782 .total_sram_size = 160 * 1024,
793 .base_address = FLASH_BANK0_BASE_SD,
794 .controller_address = 0x400e0a00,
795 .flash_wait_states = 6, /* workaround silicon bug */
797 .size_bytes = 512 * 1024,
809 .base_address = FLASH_BANK1_BASE_1024K_SD,
810 .controller_address = 0x400e0c00,
811 .flash_wait_states = 6, /* workaround silicon bug */
813 .size_bytes = 512 * 1024,
823 .chipid_cidr = 0x28a70ce0,
824 .name = "at91sam4sa16c",
825 .total_flash_size = 1024 * 1024,
826 .total_sram_size = 160 * 1024,
837 .base_address = FLASH_BANK0_BASE_SD,
838 .controller_address = 0x400e0a00,
839 .flash_wait_states = 6, /* workaround silicon bug */
841 .size_bytes = 512 * 1024,
853 .base_address = FLASH_BANK1_BASE_1024K_SD,
854 .controller_address = 0x400e0c00,
855 .flash_wait_states = 6, /* workaround silicon bug */
857 .size_bytes = 512 * 1024,
867 .chipid_cidr = 0x247e0ae0,
868 .name = "at91samg53n19",
869 .total_flash_size = 512 * 1024,
870 .total_sram_size = 96 * 1024,
881 .base_address = FLASH_BANK_BASE_S,
882 .controller_address = 0x400e0a00,
883 .flash_wait_states = 6, /* workaround silicon bug */
885 .size_bytes = 512 * 1024,
908 /***********************************************************************
909 **********************************************************************
910 **********************************************************************
911 **********************************************************************
912 **********************************************************************
913 **********************************************************************/
914 /* *ATMEL* style code - from the SAM4 driver code */
917 * Get the current status of the EEFC and
918 * the value of some status bits (LOCKE, PROGE).
919 * @param pPrivate - info about the bank
920 * @param v - result goes here
922 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
925 r = target_read_u32(pPrivate->pChip->target,
926 pPrivate->controller_address + offset_EFC_FSR,
928 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
930 ((unsigned int)((*v >> 2) & 1)),
931 ((unsigned int)((*v >> 1) & 1)),
932 ((unsigned int)((*v >> 0) & 1)));
938 * Get the result of the last executed command.
939 * @param pPrivate - info about the bank
940 * @param v - result goes here
942 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
946 r = target_read_u32(pPrivate->pChip->target,
947 pPrivate->controller_address + offset_EFC_FRR,
951 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
955 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
956 unsigned command, unsigned argument)
965 /* Check command & argument */
968 case AT91C_EFC_FCMD_WP:
969 case AT91C_EFC_FCMD_WPL:
970 case AT91C_EFC_FCMD_EWP:
971 case AT91C_EFC_FCMD_EWPL:
972 /* case AT91C_EFC_FCMD_EPL: */
973 case AT91C_EFC_FCMD_EPA:
974 case AT91C_EFC_FCMD_SLB:
975 case AT91C_EFC_FCMD_CLB:
976 n = (pPrivate->size_bytes / pPrivate->page_size);
978 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
981 case AT91C_EFC_FCMD_SFB:
982 case AT91C_EFC_FCMD_CFB:
983 if (argument >= pPrivate->pChip->details.n_gpnvms) {
984 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
985 pPrivate->pChip->details.n_gpnvms);
989 case AT91C_EFC_FCMD_GETD:
990 case AT91C_EFC_FCMD_EA:
991 case AT91C_EFC_FCMD_GLB:
992 case AT91C_EFC_FCMD_GFB:
993 case AT91C_EFC_FCMD_STUI:
994 case AT91C_EFC_FCMD_SPUI:
996 LOG_ERROR("Argument is meaningless for cmd: %d", command);
999 LOG_ERROR("Unknown command %d", command);
1003 if (command == AT91C_EFC_FCMD_SPUI) {
1004 /* this is a very special situation. */
1005 /* Situation (1) - error/retry - see below */
1006 /* And we are being called recursively */
1007 /* Situation (2) - normal, finished reading unique id */
1009 /* it should be "ready" */
1010 EFC_GetStatus(pPrivate, &v);
1012 /* then it is ready */
1016 /* we have done this before */
1017 /* the controller is not responding. */
1018 LOG_ERROR("flash controller(%d) is not ready! Error",
1019 pPrivate->bank_number);
1023 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1024 pPrivate->bank_number);
1025 /* we do that by issuing the *STOP* command */
1026 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1027 /* above is recursive, and further recursion is blocked by */
1028 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1034 v = (0x5A << 24) | (argument << 8) | command;
1035 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1036 r = target_write_u32(pPrivate->pBank->target,
1037 pPrivate->controller_address + offset_EFC_FCR, v);
1039 LOG_DEBUG("Error Write failed");
1044 * Performs the given command and wait until its completion (or an error).
1045 * @param pPrivate - info about the bank
1046 * @param command - Command to perform.
1047 * @param argument - Optional command argument.
1048 * @param status - put command status bits here
1050 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1058 long long ms_now, ms_end;
1064 r = EFC_StartCommand(pPrivate, command, argument);
1068 ms_end = 10000 + timeval_ms();
1071 r = EFC_GetStatus(pPrivate, &v);
1074 ms_now = timeval_ms();
1075 if (ms_now > ms_end) {
1077 LOG_ERROR("Command timeout");
1080 } while ((v & 1) == 0);
1084 *status = (v & 0x6);
1090 * Read the unique ID.
1091 * @param pPrivate - info about the bank
1092 * The unique ID is stored in the 'pPrivate' structure.
1094 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1100 pPrivate->pChip->cfg.unique_id[0] = 0;
1101 pPrivate->pChip->cfg.unique_id[1] = 0;
1102 pPrivate->pChip->cfg.unique_id[2] = 0;
1103 pPrivate->pChip->cfg.unique_id[3] = 0;
1106 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1110 for (x = 0; x < 4; x++) {
1111 r = target_read_u32(pPrivate->pChip->target,
1112 pPrivate->pBank->base + (x * 4),
1116 pPrivate->pChip->cfg.unique_id[x] = v;
1119 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1120 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1122 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1123 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1124 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1125 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1131 * Erases the entire flash.
1132 * @param pPrivate - the info about the bank.
1134 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1137 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1141 * Erases the entire flash.
1142 * @param pPrivate - the info about the bank.
1144 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1169 /* AT91C_EFC_FCMD_EPA
1170 * According to the datasheet FARG[15:2] defines the page from which
1171 * the erase will start.This page must be modulo 4, 8, 16 or 32
1172 * according to the number of pages to erase. FARG[1:0] defines the
1173 * number of pages to be erased. Previously (firstpage << 2) was used
1174 * to conform to this, seems it should not be shifted...
1176 return EFC_PerformCommand(pPrivate,
1177 /* send Erase Page */
1179 (firstPage) | erasePages,
1184 * Gets current GPNVM state.
1185 * @param pPrivate - info about the bank.
1186 * @param gpnvm - GPNVM bit index.
1187 * @param puthere - result stored here.
1189 /* ------------------------------------------------------------------------------ */
1190 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1196 if (pPrivate->bank_number != 0) {
1197 LOG_ERROR("GPNVM only works with Bank0");
1201 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1202 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1203 gpnvm, pPrivate->pChip->details.n_gpnvms);
1207 /* Get GPNVMs status */
1208 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1209 if (r != ERROR_OK) {
1210 LOG_ERROR("Failed");
1214 r = EFC_GetResult(pPrivate, &v);
1217 /* Check if GPNVM is set */
1218 /* get the bit and make it a 0/1 */
1219 *puthere = (v >> gpnvm) & 1;
1226 * Clears the selected GPNVM bit.
1227 * @param pPrivate info about the bank
1228 * @param gpnvm GPNVM index.
1229 * @returns 0 if successful; otherwise returns an error code.
1231 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1237 if (pPrivate->bank_number != 0) {
1238 LOG_ERROR("GPNVM only works with Bank0");
1242 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1243 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1244 gpnvm, pPrivate->pChip->details.n_gpnvms);
1248 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1249 if (r != ERROR_OK) {
1250 LOG_DEBUG("Failed: %d", r);
1253 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1254 LOG_DEBUG("End: %d", r);
1259 * Sets the selected GPNVM bit.
1260 * @param pPrivate info about the bank
1261 * @param gpnvm GPNVM index.
1263 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1268 if (pPrivate->bank_number != 0) {
1269 LOG_ERROR("GPNVM only works with Bank0");
1273 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1274 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1275 gpnvm, pPrivate->pChip->details.n_gpnvms);
1279 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1287 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1293 * Returns a bit field (at most 64) of locked regions within a page.
1294 * @param pPrivate info about the bank
1295 * @param v where to store locked bits
1297 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1301 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1302 if (r == ERROR_OK) {
1303 EFC_GetResult(pPrivate, v);
1304 EFC_GetResult(pPrivate, v);
1305 EFC_GetResult(pPrivate, v);
1306 r = EFC_GetResult(pPrivate, v);
1308 LOG_DEBUG("End: %d", r);
1313 * Unlocks all the regions in the given address range.
1314 * @param pPrivate info about the bank
1315 * @param start_sector first sector to unlock
1316 * @param end_sector last (inclusive) to unlock
1319 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1320 unsigned start_sector,
1321 unsigned end_sector)
1326 uint32_t pages_per_sector;
1328 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1330 /* Unlock all pages */
1331 while (start_sector <= end_sector) {
1332 pg = start_sector * pages_per_sector;
1334 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1345 * @param pPrivate - info about the bank
1346 * @param start_sector - first sector to lock
1347 * @param end_sector - last sector (inclusive) to lock
1349 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1350 unsigned start_sector,
1351 unsigned end_sector)
1355 uint32_t pages_per_sector;
1358 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1360 /* Lock all pages */
1361 while (start_sector <= end_sector) {
1362 pg = start_sector * pages_per_sector;
1364 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1372 /****** END SAM4 CODE ********/
1374 /* begin helpful debug code */
1375 /* print the fieldname, the field value, in dec & hex, and return field value */
1376 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1377 const char *regname,
1386 /* extract the field */
1388 v = v & ((1 << width)-1);
1397 /* show the basics */
1398 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1399 REG_NAME_WIDTH, regname,
1405 static const char _unknown[] = "unknown";
1406 static const char *const eproc_names[] = {
1410 "cortex-m3", /* 3 */
1412 "arm926ejs", /* 5 */
1413 "cortex-a5", /* 6 */
1414 "cortex-m4", /* 7 */
1425 #define nvpsize2 nvpsize /* these two tables are identical */
1426 static const char *const nvpsize[] = {
1429 "16K bytes", /* 2 */
1430 "32K bytes", /* 3 */
1432 "64K bytes", /* 5 */
1434 "128K bytes", /* 7 */
1436 "256K bytes", /* 9 */
1437 "512K bytes", /* 10 */
1439 "1024K bytes", /* 12 */
1441 "2048K bytes", /* 14 */
1445 static const char *const sramsize[] = {
1446 "48K Bytes", /* 0 */
1450 "112K Bytes", /* 4 */
1452 "80K Bytes", /* 6 */
1453 "160K Bytes", /* 7 */
1455 "16K Bytes", /* 9 */
1456 "32K Bytes", /* 10 */
1457 "64K Bytes", /* 11 */
1458 "128K Bytes", /* 12 */
1459 "256K Bytes", /* 13 */
1460 "96K Bytes", /* 14 */
1461 "512K Bytes", /* 15 */
1465 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1466 { 0x19, "AT91SAM9xx Series" },
1467 { 0x29, "AT91SAM9XExx Series" },
1468 { 0x34, "AT91x34 Series" },
1469 { 0x37, "CAP7 Series" },
1470 { 0x39, "CAP9 Series" },
1471 { 0x3B, "CAP11 Series" },
1472 { 0x3C, "ATSAM4E" },
1473 { 0x40, "AT91x40 Series" },
1474 { 0x42, "AT91x42 Series" },
1475 { 0x43, "SAMG51 Series"
1477 { 0x47, "SAMG53 Series"
1479 { 0x55, "AT91x55 Series" },
1480 { 0x60, "AT91SAM7Axx Series" },
1481 { 0x61, "AT91SAM7AQxx Series" },
1482 { 0x63, "AT91x63 Series" },
1483 { 0x70, "AT91SAM7Sxx Series" },
1484 { 0x71, "AT91SAM7XCxx Series" },
1485 { 0x72, "AT91SAM7SExx Series" },
1486 { 0x73, "AT91SAM7Lxx Series" },
1487 { 0x75, "AT91SAM7Xxx Series" },
1488 { 0x76, "AT91SAM7SLxx Series" },
1489 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1490 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1491 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1492 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1493 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1494 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1495 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1496 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1497 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1498 { 0x92, "AT91x92 Series" },
1499 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1500 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1501 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1502 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1503 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1504 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1505 { 0xA5, "ATSAM5A" },
1506 { 0xF0, "AT75Cxx Series" },
1510 static const char *const nvptype[] = {
1512 "romless or onchip flash", /* 1 */
1513 "embedded flash memory",/* 2 */
1514 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1515 "sram emulating flash", /* 4 */
1521 static const char *_yes_or_no(uint32_t v)
1529 static const char *const _rc_freq[] = {
1530 "4 MHz", "8 MHz", "12 MHz", "reserved"
1533 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
1538 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1539 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
1540 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1541 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
1542 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
1543 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
1544 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1545 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
1547 pChip->cfg.rc_freq = 0;
1551 pChip->cfg.rc_freq = 0;
1554 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1557 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1560 pChip->cfg.rc_freq = 12 * 1000 * 1000;
1565 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1566 LOG_USER("(startup clks, time= %f uSecs)",
1567 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1568 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1569 LOG_USER("(mainosc source: %s)",
1570 v ? "external xtal" : "internal RC");
1572 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1573 LOG_USER("(clock failure enabled: %s)",
1577 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
1583 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1586 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1587 LOG_USER("%s", eproc_names[v]);
1589 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1590 LOG_USER("%s", nvpsize[v]);
1592 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1593 LOG_USER("%s", nvpsize2[v]);
1595 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
1596 LOG_USER("%s", sramsize[v]);
1598 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1600 for (x = 0; archnames[x].name; x++) {
1601 if (v == archnames[x].value) {
1602 cp = archnames[x].name;
1609 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1610 LOG_USER("%s", nvptype[v]);
1612 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1613 LOG_USER("(exists: %s)", _yes_or_no(v));
1616 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
1620 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1621 LOG_USER("(main ready: %s)", _yes_or_no(v));
1623 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1625 v = (v * pChip->cfg.slow_freq) / 16;
1626 pChip->cfg.mainosc_freq = v;
1628 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
1630 (uint32_t)(pChip->cfg.slow_freq / 1000),
1631 (uint32_t)(pChip->cfg.slow_freq % 1000));
1634 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
1636 uint32_t mula, diva;
1638 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1640 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1642 pChip->cfg.plla_freq = 0;
1644 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1646 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1647 else if (diva >= 1) {
1648 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
1649 LOG_USER("\tPLLA Freq: %3.03f MHz",
1650 _tomhz(pChip->cfg.plla_freq));
1654 static void sam4_explain_mckr(struct sam4_chip *pChip)
1656 uint32_t css, pres, fin = 0;
1658 const char *cp = NULL;
1660 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1663 fin = pChip->cfg.slow_freq;
1667 fin = pChip->cfg.mainosc_freq;
1671 fin = pChip->cfg.plla_freq;
1675 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1676 fin = 480 * 1000 * 1000;
1680 cp = "upll (*ERROR* UPLL is disabled)";
1688 LOG_USER("%s (%3.03f Mhz)",
1691 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1692 switch (pres & 0x07) {
1695 cp = "selected clock";
1729 LOG_USER("(%s)", cp);
1731 /* sam4 has a *SINGLE* clock - */
1732 /* other at91 series parts have divisors for these. */
1733 pChip->cfg.cpu_freq = fin;
1734 pChip->cfg.mclk_freq = fin;
1735 pChip->cfg.fclk_freq = fin;
1736 LOG_USER("\t\tResult CPU Freq: %3.03f",
1741 static struct sam4_chip *target2sam4(struct target *pTarget)
1743 struct sam4_chip *pChip;
1745 if (pTarget == NULL)
1748 pChip = all_sam4_chips;
1750 if (pChip->target == pTarget)
1751 break; /* return below */
1753 pChip = pChip->next;
1759 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
1761 /* this function exists to help */
1762 /* keep funky offsetof() errors */
1763 /* and casting from causing bugs */
1765 /* By using prototypes - we can detect what would */
1766 /* be casting errors. */
1768 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
1772 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
1774 NAME), # NAME, FUNC }
1775 static const struct sam4_reg_list sam4_all_regs[] = {
1776 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
1777 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
1778 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
1779 SAM4_ENTRY(CKGR_UCKR, NULL),
1780 SAM4_ENTRY(PMC_FSMR, NULL),
1781 SAM4_ENTRY(PMC_FSPR, NULL),
1782 SAM4_ENTRY(PMC_IMR, NULL),
1783 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
1784 SAM4_ENTRY(PMC_PCK0, NULL),
1785 SAM4_ENTRY(PMC_PCK1, NULL),
1786 SAM4_ENTRY(PMC_PCK2, NULL),
1787 SAM4_ENTRY(PMC_PCSR, NULL),
1788 SAM4_ENTRY(PMC_SCSR, NULL),
1789 SAM4_ENTRY(PMC_SR, NULL),
1790 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
1791 SAM4_ENTRY(CHIPID_EXID, NULL),
1792 /* TERMINATE THE LIST */
1797 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
1799 return bank->driver_priv;
1803 * Given a pointer to where it goes in the structure,
1804 * determine the register name, address from the all registers table.
1806 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
1808 const struct sam4_reg_list *pReg;
1810 pReg = &(sam4_all_regs[0]);
1811 while (pReg->name) {
1812 uint32_t *pPossible;
1814 /* calculate where this one go.. */
1815 /* it is "possibly" this register. */
1817 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1819 /* well? Is it this register */
1820 if (pPossible == goes_here) {
1828 /* This is *TOTAL*PANIC* - we are totally screwed. */
1829 LOG_ERROR("INVALID SAM4 REGISTER");
1833 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
1835 const struct sam4_reg_list *pReg;
1838 pReg = sam4_GetReg(pChip, goes_here);
1842 r = target_read_u32(pChip->target, pReg->address, goes_here);
1843 if (r != ERROR_OK) {
1844 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
1845 pReg->name, (unsigned)(pReg->address), r);
1850 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
1853 const struct sam4_reg_list *pReg;
1855 pReg = &(sam4_all_regs[0]);
1856 while (pReg->name) {
1857 r = sam4_ReadThisReg(pChip,
1858 sam4_get_reg_ptr(&(pChip->cfg), pReg));
1859 if (r != ERROR_OK) {
1860 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
1861 pReg->name, ((unsigned)(pReg->address)), r);
1870 static int sam4_GetInfo(struct sam4_chip *pChip)
1872 const struct sam4_reg_list *pReg;
1875 pReg = &(sam4_all_regs[0]);
1876 while (pReg->name) {
1877 /* display all regs */
1878 LOG_DEBUG("Start: %s", pReg->name);
1879 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
1880 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
1885 if (pReg->explain_func)
1886 (*(pReg->explain_func))(pChip);
1887 LOG_DEBUG("End: %s", pReg->name);
1890 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
1891 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
1892 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
1893 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
1894 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
1896 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
1897 pChip->cfg.unique_id[0],
1898 pChip->cfg.unique_id[1],
1899 pChip->cfg.unique_id[2],
1900 pChip->cfg.unique_id[3]);
1905 static int sam4_protect_check(struct flash_bank *bank)
1908 uint32_t v[4] = {0};
1910 struct sam4_bank_private *pPrivate;
1913 if (bank->target->state != TARGET_HALTED) {
1914 LOG_ERROR("Target not halted");
1915 return ERROR_TARGET_NOT_HALTED;
1918 pPrivate = get_sam4_bank_private(bank);
1920 LOG_ERROR("no private for this bank?");
1923 if (!(pPrivate->probed))
1924 return ERROR_FLASH_BANK_NOT_PROBED;
1926 r = FLASHD_GetLockBits(pPrivate, v);
1927 if (r != ERROR_OK) {
1928 LOG_DEBUG("Failed: %d", r);
1932 for (x = 0; x < pPrivate->nsectors; x++)
1933 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
1938 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
1940 struct sam4_chip *pChip;
1942 pChip = all_sam4_chips;
1944 /* is this an existing chip? */
1946 if (pChip->target == bank->target)
1948 pChip = pChip->next;
1952 /* this is a *NEW* chip */
1953 pChip = calloc(1, sizeof(struct sam4_chip));
1955 LOG_ERROR("NO RAM!");
1958 pChip->target = bank->target;
1959 /* insert at head */
1960 pChip->next = all_sam4_chips;
1961 all_sam4_chips = pChip;
1962 pChip->target = bank->target;
1963 /* assumption is this runs at 32khz */
1964 pChip->cfg.slow_freq = 32768;
1968 switch (bank->base) {
1970 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
1971 "[at91sam4s series] )",
1972 ((unsigned int)(bank->base)),
1973 ((unsigned int)(FLASH_BANK_BASE_S)));
1977 /* at91sam4s series only has bank 0*/
1978 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
1979 case FLASH_BANK_BASE_S:
1980 bank->driver_priv = &(pChip->details.bank[0]);
1981 bank->bank_number = 0;
1982 pChip->details.bank[0].pChip = pChip;
1983 pChip->details.bank[0].pBank = bank;
1986 /* Bank 1 of at91sam4sd series */
1987 case FLASH_BANK1_BASE_1024K_SD:
1988 case FLASH_BANK1_BASE_2048K_SD:
1989 bank->driver_priv = &(pChip->details.bank[1]);
1990 bank->bank_number = 1;
1991 pChip->details.bank[1].pChip = pChip;
1992 pChip->details.bank[1].pBank = bank;
1996 /* we initialize after probing. */
2000 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2002 const struct sam4_chip_details *pDetails;
2003 struct sam4_chip *pChip;
2004 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2008 pDetails = all_sam4_details;
2009 while (pDetails->name) {
2010 /* Compare cidr without version bits */
2011 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2016 if (pDetails->name == NULL) {
2017 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2018 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2019 /* Help the victim, print details about the chip */
2020 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2021 pPrivate->pChip->cfg.CHIPID_CIDR);
2022 sam4_explain_chipid_cidr(pPrivate->pChip);
2026 /* DANGER: THERE ARE DRAGONS HERE */
2028 /* get our pChip - it is going */
2029 /* to be over-written shortly */
2030 pChip = pPrivate->pChip;
2032 /* Note that, in reality: */
2034 /* pPrivate = &(pChip->details.bank[0]) */
2035 /* or pPrivate = &(pChip->details.bank[1]) */
2038 /* save the "bank" pointers */
2039 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2040 saved_banks[x] = pChip->details.bank[x].pBank;
2042 /* Overwrite the "details" structure. */
2043 memcpy(&(pPrivate->pChip->details),
2045 sizeof(pPrivate->pChip->details));
2047 /* now fix the ghosted pointers */
2048 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2049 pChip->details.bank[x].pChip = pChip;
2050 pChip->details.bank[x].pBank = saved_banks[x];
2053 /* update the *BANK*SIZE* */
2059 static int _sam4_probe(struct flash_bank *bank, int noise)
2063 struct sam4_bank_private *pPrivate;
2066 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2067 if (bank->target->state != TARGET_HALTED) {
2068 LOG_ERROR("Target not halted");
2069 return ERROR_TARGET_NOT_HALTED;
2072 pPrivate = get_sam4_bank_private(bank);
2074 LOG_ERROR("Invalid/unknown bank number");
2078 r = sam4_ReadAllRegs(pPrivate->pChip);
2083 if (pPrivate->pChip->probed)
2084 r = sam4_GetInfo(pPrivate->pChip);
2086 r = sam4_GetDetails(pPrivate);
2090 /* update the flash bank size */
2091 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2092 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2093 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2098 if (bank->sectors == NULL) {
2099 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2100 if (bank->sectors == NULL) {
2101 LOG_ERROR("No memory!");
2104 bank->num_sectors = pPrivate->nsectors;
2106 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2107 bank->sectors[x].size = pPrivate->sector_size;
2108 bank->sectors[x].offset = x * (pPrivate->sector_size);
2109 /* mark as unknown */
2110 bank->sectors[x].is_erased = -1;
2111 bank->sectors[x].is_protected = -1;
2115 pPrivate->probed = 1;
2117 r = sam4_protect_check(bank);
2121 LOG_DEBUG("Bank = %d, nbanks = %d",
2122 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2123 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2124 /* read unique id, */
2125 /* it appears to be associated with the *last* flash bank. */
2126 FLASHD_ReadUniqueID(pPrivate);
2132 static int sam4_probe(struct flash_bank *bank)
2134 return _sam4_probe(bank, 1);
2137 static int sam4_auto_probe(struct flash_bank *bank)
2139 return _sam4_probe(bank, 0);
2142 static int sam4_erase(struct flash_bank *bank, int first, int last)
2144 struct sam4_bank_private *pPrivate;
2148 /*16 pages equals 8KB - Same size as a lock region*/
2153 if (bank->target->state != TARGET_HALTED) {
2154 LOG_ERROR("Target not halted");
2155 return ERROR_TARGET_NOT_HALTED;
2158 r = sam4_auto_probe(bank);
2159 if (r != ERROR_OK) {
2160 LOG_DEBUG("Here,r=%d", r);
2164 pPrivate = get_sam4_bank_private(bank);
2165 if (!(pPrivate->probed))
2166 return ERROR_FLASH_BANK_NOT_PROBED;
2168 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2171 return FLASHD_EraseEntireBank(pPrivate);
2173 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2174 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
2175 for (i = first; i <= last; i++) {
2176 /*16 pages equals 8KB - Same size as a lock region*/
2177 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2178 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
2180 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
2182 if (status & (1 << 2)) {
2183 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
2186 if (status & (1 << 1)) {
2187 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
2195 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
2197 struct sam4_bank_private *pPrivate;
2201 if (bank->target->state != TARGET_HALTED) {
2202 LOG_ERROR("Target not halted");
2203 return ERROR_TARGET_NOT_HALTED;
2206 pPrivate = get_sam4_bank_private(bank);
2207 if (!(pPrivate->probed))
2208 return ERROR_FLASH_BANK_NOT_PROBED;
2211 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2213 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2214 LOG_DEBUG("End: r=%d", r);
2220 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2225 adr = pagenum * pPrivate->page_size;
2226 adr = adr + pPrivate->base_address;
2228 r = target_read_memory(pPrivate->pChip->target,
2230 4, /* THIS*MUST*BE* in 32bit values */
2231 pPrivate->page_size / 4,
2234 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2235 (unsigned int)(adr));
2239 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2243 uint32_t fmr; /* EEFC Flash Mode Register */
2246 adr = pagenum * pPrivate->page_size;
2247 adr = (adr + pPrivate->base_address);
2249 /* Get flash mode register value */
2250 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2252 LOG_DEBUG("Error Read failed: read flash mode register");
2254 /* Clear flash wait state field */
2257 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2258 fmr |= (pPrivate->flash_wait_states << 8);
2260 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2261 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2263 LOG_DEBUG("Error Write failed: set flash mode register");
2265 /* 1st sector 8kBytes - page 0 - 15*/
2266 /* 2nd sector 8kBytes - page 16 - 30*/
2267 /* 3rd sector 48kBytes - page 31 - 127*/
2268 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2269 r = target_write_memory(pPrivate->pChip->target,
2271 4, /* THIS*MUST*BE* in 32bit values */
2272 pPrivate->page_size / 4,
2274 if (r != ERROR_OK) {
2275 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2276 (unsigned int)(adr));
2280 r = EFC_PerformCommand(pPrivate,
2281 /* send Erase & Write Page */
2282 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2287 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2288 (unsigned int)(adr));
2289 if (status & (1 << 2)) {
2290 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2293 if (status & (1 << 1)) {
2294 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2300 static int sam4_write(struct flash_bank *bank,
2301 const uint8_t *buffer,
2309 unsigned page_offset;
2310 struct sam4_bank_private *pPrivate;
2311 uint8_t *pagebuffer;
2313 /* incase we bail further below, set this to null */
2316 /* ignore dumb requests */
2322 if (bank->target->state != TARGET_HALTED) {
2323 LOG_ERROR("Target not halted");
2324 r = ERROR_TARGET_NOT_HALTED;
2328 pPrivate = get_sam4_bank_private(bank);
2329 if (!(pPrivate->probed)) {
2330 r = ERROR_FLASH_BANK_NOT_PROBED;
2334 if ((offset + count) > pPrivate->size_bytes) {
2335 LOG_ERROR("Flash write error - past end of bank");
2336 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2337 (unsigned int)(offset),
2338 (unsigned int)(count),
2339 (unsigned int)(pPrivate->size_bytes));
2344 pagebuffer = malloc(pPrivate->page_size);
2346 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2351 /* what page do we start & end in? */
2352 page_cur = offset / pPrivate->page_size;
2353 page_end = (offset + count - 1) / pPrivate->page_size;
2355 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2356 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2358 /* Special case: all one page */
2361 /* (1) non-aligned start */
2362 /* (2) body pages */
2363 /* (3) non-aligned end. */
2365 /* Handle special case - all one page. */
2366 if (page_cur == page_end) {
2367 LOG_DEBUG("Special case, all in one page");
2368 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2372 page_offset = (offset & (pPrivate->page_size-1));
2373 memcpy(pagebuffer + page_offset,
2377 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2384 /* non-aligned start */
2385 page_offset = offset & (pPrivate->page_size - 1);
2387 LOG_DEBUG("Not-Aligned start");
2388 /* read the partial */
2389 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2393 /* over-write with new data */
2394 n = (pPrivate->page_size - page_offset);
2395 memcpy(pagebuffer + page_offset,
2399 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2409 /* By checking that offset is correct here, we also
2410 fix a clang warning */
2411 assert(offset % pPrivate->page_size == 0);
2413 /* intermediate large pages */
2414 /* also - the final *terminal* */
2415 /* if that terminal page is a full page */
2416 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2417 (int)page_cur, (int)page_end, (unsigned int)(count));
2419 while ((page_cur < page_end) &&
2420 (count >= pPrivate->page_size)) {
2421 r = sam4_page_write(pPrivate, page_cur, buffer);
2424 count -= pPrivate->page_size;
2425 buffer += pPrivate->page_size;
2429 /* terminal partial page? */
2431 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2432 /* we have a partial page */
2433 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2436 /* data goes at start */
2437 memcpy(pagebuffer, buffer, count);
2438 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2450 COMMAND_HANDLER(sam4_handle_info_command)
2452 struct sam4_chip *pChip;
2453 pChip = get_current_sam4(CMD_CTX);
2460 /* bank0 must exist before we can do anything */
2461 if (pChip->details.bank[0].pBank == NULL) {
2464 command_print(CMD_CTX,
2465 "Please define bank %d via command: flash bank %s ... ",
2467 at91sam4_flash.name);
2471 /* if bank 0 is not probed, then probe it */
2472 if (!(pChip->details.bank[0].probed)) {
2473 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2477 /* above guarantees the "chip details" structure is valid */
2478 /* and thus, bank private areas are valid */
2479 /* and we have a SAM4 chip, what a concept! */
2481 /* auto-probe other banks, 0 done above */
2482 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
2483 /* skip banks not present */
2484 if (!(pChip->details.bank[x].present))
2487 if (pChip->details.bank[x].pBank == NULL)
2490 if (pChip->details.bank[x].probed)
2493 r = sam4_auto_probe(pChip->details.bank[x].pBank);
2498 r = sam4_GetInfo(pChip);
2499 if (r != ERROR_OK) {
2500 LOG_DEBUG("Sam4Info, Failed %d", r);
2507 COMMAND_HANDLER(sam4_handle_gpnvm_command)
2511 struct sam4_chip *pChip;
2513 pChip = get_current_sam4(CMD_CTX);
2517 if (pChip->target->state != TARGET_HALTED) {
2518 LOG_ERROR("sam4 - target not halted");
2519 return ERROR_TARGET_NOT_HALTED;
2522 if (pChip->details.bank[0].pBank == NULL) {
2523 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2524 at91sam4_flash.name);
2527 if (!pChip->details.bank[0].probed) {
2528 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2535 return ERROR_COMMAND_SYNTAX_ERROR;
2544 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
2548 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2554 if (0 == strcmp("show", CMD_ARGV[0])) {
2558 for (x = 0; x < pChip->details.n_gpnvms; x++) {
2559 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2562 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
2566 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2567 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2568 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
2571 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
2572 return ERROR_COMMAND_SYNTAX_ERROR;
2577 command_print(CMD_CTX, "Missing GPNVM number");
2578 return ERROR_COMMAND_SYNTAX_ERROR;
2581 if (0 == strcmp("set", CMD_ARGV[0]))
2582 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2583 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2584 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
2585 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2587 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
2588 r = ERROR_COMMAND_SYNTAX_ERROR;
2593 COMMAND_HANDLER(sam4_handle_slowclk_command)
2595 struct sam4_chip *pChip;
2597 pChip = get_current_sam4(CMD_CTX);
2609 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2611 /* absurd slow clock of 200Khz? */
2612 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
2613 return ERROR_COMMAND_SYNTAX_ERROR;
2615 pChip->cfg.slow_freq = v;
2620 command_print(CMD_CTX, "Too many parameters");
2621 return ERROR_COMMAND_SYNTAX_ERROR;
2624 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2625 (int)(pChip->cfg.slow_freq / 1000),
2626 (int)(pChip->cfg.slow_freq % 1000));
2630 static const struct command_registration at91sam4_exec_command_handlers[] = {
2633 .handler = sam4_handle_gpnvm_command,
2634 .mode = COMMAND_EXEC,
2635 .usage = "[('clr'|'set'|'show') bitnum]",
2636 .help = "Without arguments, shows all bits in the gpnvm "
2637 "register. Otherwise, clears, sets, or shows one "
2638 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2642 .handler = sam4_handle_info_command,
2643 .mode = COMMAND_EXEC,
2644 .help = "Print information about the current at91sam4 chip"
2645 "and its flash configuration.",
2649 .handler = sam4_handle_slowclk_command,
2650 .mode = COMMAND_EXEC,
2651 .usage = "[clock_hz]",
2652 .help = "Display or set the slowclock frequency "
2653 "(default 32768 Hz).",
2655 COMMAND_REGISTRATION_DONE
2657 static const struct command_registration at91sam4_command_handlers[] = {
2660 .mode = COMMAND_ANY,
2661 .help = "at91sam4 flash command group",
2663 .chain = at91sam4_exec_command_handlers,
2665 COMMAND_REGISTRATION_DONE
2668 struct flash_driver at91sam4_flash = {
2670 .commands = at91sam4_command_handlers,
2671 .flash_bank_command = sam4_flash_bank_command,
2672 .erase = sam4_erase,
2673 .protect = sam4_protect,
2674 .write = sam4_write,
2675 .read = default_flash_read,
2676 .probe = sam4_probe,
2677 .auto_probe = sam4_auto_probe,
2678 .erase_check = default_flash_blank_check,
2679 .protect_check = sam4_protect_check,