1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
64 #include <helper/time_support.h>
66 #define REG_NAME_WIDTH (12)
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
106 extern struct flash_driver at91sam4_flash;
108 static float _tomhz(uint32_t freq_hz)
112 f = ((float)(freq_hz)) / 1000000.0;
116 /* How the chip is configured. */
118 uint32_t unique_id[4];
122 uint32_t mainosc_freq;
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID;
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
168 struct sam4_bank_private {
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
176 /* so we can find the chip we belong to */
177 struct sam4_chip *pChip;
178 /* so we can find the original bank pointer */
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
183 uint32_t flash_wait_states;
187 unsigned sector_size;
191 struct sam4_chip_details {
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm[SAM4_N_NVM_BITS];
205 unsigned total_flash_size;
206 unsigned total_sram_size;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
214 struct sam4_chip *next;
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details;
219 struct target *target;
224 struct sam4_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam4_chip *pInfo);
229 static struct sam4_chip *all_sam4_chips;
231 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
234 static struct sam4_chip *p;
236 t = get_current_target(cmd_ctx);
238 command_print(cmd_ctx, "No current target?");
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd_ctx, "No SAM4 chips exist?");
255 command_print(cmd_ctx, "Cannot find SAM4 chip?");
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
269 .chipid_cidr = 0xA66D0EE0,
270 .name = "at91sam4c32e",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
286 .size_bytes = 1024 * 1024,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
301 .size_bytes = 1024 * 1024,
308 /* at91sam4c32c - LQFP100 */
310 .chipid_cidr = 0xA64D0EE0,
311 .name = "at91sam4c32c",
312 .total_flash_size = 2024 * 1024,
313 .total_sram_size = 256 * 1024,
323 .base_address = FLASH_BANK0_BASE_C32,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
327 .size_bytes = 1024 * 1024,
338 .base_address = FLASH_BANK1_BASE_C32,
339 .controller_address = 0x400e0c00,
340 .flash_wait_states = 5,
342 .size_bytes = 1024 * 1024,
349 /* at91sam4c16c - LQFP100 */
351 .chipid_cidr = 0xA64C0CE0,
352 .name = "at91sam4c16c",
353 .total_flash_size = 1024 * 1024,
354 .total_sram_size = 128 * 1024,
364 .base_address = FLASH_BANK_BASE_C,
365 .controller_address = 0x400e0a00,
366 .flash_wait_states = 5,
368 .size_bytes = 1024 * 1024,
382 /* at91sam4c8c - LQFP100 */
384 .chipid_cidr = 0xA64C0AE0,
385 .name = "at91sam4c8c",
386 .total_flash_size = 512 * 1024,
387 .total_sram_size = 128 * 1024,
397 .base_address = FLASH_BANK_BASE_C,
398 .controller_address = 0x400e0a00,
399 .flash_wait_states = 5,
401 .size_bytes = 512 * 1024,
415 /* at91sam4c4c (rev B) - LQFP100 */
417 .chipid_cidr = 0xA64C0CE5,
418 .name = "at91sam4c4c",
419 .total_flash_size = 256 * 1024,
420 .total_sram_size = 128 * 1024,
430 .base_address = FLASH_BANK_BASE_C,
431 .controller_address = 0x400e0a00,
432 .flash_wait_states = 5,
434 .size_bytes = 256 * 1024,
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
452 .chipid_cidr = 0xA3CC0CE0,
453 .name = "at91sam4e16e",
454 .total_flash_size = 1024 * 1024,
455 .total_sram_size = 128 * 1024,
465 .base_address = FLASH_BANK_BASE_S,
466 .controller_address = 0x400e0a00,
467 .flash_wait_states = 5,
469 .size_bytes = 1024 * 1024,
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
487 .chipid_cidr = 0x293B0AE0,
488 .name = "at91sam4n8a",
489 .total_flash_size = 512 * 1024,
490 .total_sram_size = 64 * 1024,
500 .base_address = FLASH_BANK_BASE_S,
501 .controller_address = 0x400e0a00,
502 .flash_wait_states = 5,
504 .size_bytes = 512 * 1024,
518 /*atsam4n8b - LQFP64/QFN64*/
520 .chipid_cidr = 0x294B0AE0,
521 .name = "at91sam4n8b",
522 .total_flash_size = 512 * 1024,
523 .total_sram_size = 64 * 1024,
533 .base_address = FLASH_BANK_BASE_S,
534 .controller_address = 0x400e0a00,
535 .flash_wait_states = 5,
537 .size_bytes = 512 * 1024,
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
553 .chipid_cidr = 0x295B0AE0,
554 .name = "at91sam4n8c",
555 .total_flash_size = 512 * 1024,
556 .total_sram_size = 64 * 1024,
566 .base_address = FLASH_BANK_BASE_S,
567 .controller_address = 0x400e0a00,
568 .flash_wait_states = 5,
570 .size_bytes = 512 * 1024,
584 /*atsam4n16b - LQFP64/QFN64*/
586 .chipid_cidr = 0x29460CE0,
587 .name = "at91sam4n16b",
588 .total_flash_size = 1024 * 1024,
589 .total_sram_size = 80 * 1024,
599 .base_address = FLASH_BANK_BASE_S,
600 .controller_address = 0x400e0a00,
601 .flash_wait_states = 5,
603 .size_bytes = 1024 * 1024,
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
619 .chipid_cidr = 0x29560CE0,
620 .name = "at91sam4n16c",
621 .total_flash_size = 1024 * 1024,
622 .total_sram_size = 80 * 1024,
632 .base_address = FLASH_BANK_BASE_S,
633 .controller_address = 0x400e0a00,
634 .flash_wait_states = 5,
636 .size_bytes = 1024 * 1024,
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
654 .chipid_cidr = 0x28AC0CE0,
655 .name = "at91sam4s16c",
656 .total_flash_size = 1024 * 1024,
657 .total_sram_size = 128 * 1024,
667 .base_address = FLASH_BANK_BASE_S,
668 .controller_address = 0x400e0a00,
669 .flash_wait_states = 5,
671 .size_bytes = 1024 * 1024,
685 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
687 .chipid_cidr = 0x28a70ce0,
688 .name = "at91sam4sa16c",
689 .total_flash_size = 1024 * 1024,
690 .total_sram_size = 160 * 1024,
701 .base_address = FLASH_BANK_BASE_S,
702 .controller_address = 0x400e0a00,
703 .flash_wait_states = 5,
705 .size_bytes = 1024 * 1024,
719 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
721 .chipid_cidr = 0x289C0CE0,
722 .name = "at91sam4s16b",
723 .total_flash_size = 1024 * 1024,
724 .total_sram_size = 128 * 1024,
734 .base_address = FLASH_BANK_BASE_S,
735 .controller_address = 0x400e0a00,
736 .flash_wait_states = 5,
738 .size_bytes = 1024 * 1024,
752 /*atsam4sa16b - LQFP64/QFN64*/
754 .chipid_cidr = 0x28970CE0,
755 .name = "at91sam4sa16b",
756 .total_flash_size = 1024 * 1024,
757 .total_sram_size = 160 * 1024,
767 .base_address = FLASH_BANK_BASE_S,
768 .controller_address = 0x400e0a00,
769 .flash_wait_states = 5,
771 .size_bytes = 1024 * 1024,
785 /*atsam4s16a - LQFP48/QFN48*/
787 .chipid_cidr = 0x288C0CE0,
788 .name = "at91sam4s16a",
789 .total_flash_size = 1024 * 1024,
790 .total_sram_size = 128 * 1024,
800 .base_address = FLASH_BANK_BASE_S,
801 .controller_address = 0x400e0a00,
802 .flash_wait_states = 5,
804 .size_bytes = 1024 * 1024,
818 /*atsam4s8c - LQFP100/BGA100*/
820 .chipid_cidr = 0x28AC0AE0,
821 .name = "at91sam4s8c",
822 .total_flash_size = 512 * 1024,
823 .total_sram_size = 128 * 1024,
833 .base_address = FLASH_BANK_BASE_S,
834 .controller_address = 0x400e0a00,
835 .flash_wait_states = 5,
837 .size_bytes = 512 * 1024,
851 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
853 .chipid_cidr = 0x289C0AE0,
854 .name = "at91sam4s8b",
855 .total_flash_size = 512 * 1024,
856 .total_sram_size = 128 * 1024,
866 .base_address = FLASH_BANK_BASE_S,
867 .controller_address = 0x400e0a00,
868 .flash_wait_states = 5,
870 .size_bytes = 512 * 1024,
884 /*atsam4s8a - LQFP48/BGA48*/
886 .chipid_cidr = 0x288C0AE0,
887 .name = "at91sam4s8a",
888 .total_flash_size = 512 * 1024,
889 .total_sram_size = 128 * 1024,
899 .base_address = FLASH_BANK_BASE_S,
900 .controller_address = 0x400e0a00,
901 .flash_wait_states = 5,
903 .size_bytes = 512 * 1024,
918 /*atsam4s4c - LQFP100/BGA100*/
920 .chipid_cidr = 0x28ab09e0,
921 .name = "at91sam4s4c",
922 .total_flash_size = 256 * 1024,
923 .total_sram_size = 64 * 1024,
933 .base_address = FLASH_BANK_BASE_S,
934 .controller_address = 0x400e0a00,
935 .flash_wait_states = 5,
937 .size_bytes = 256 * 1024,
952 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
954 .chipid_cidr = 0x289b09e0,
955 .name = "at91sam4s4b",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 64 * 1024,
967 .base_address = FLASH_BANK_BASE_S,
968 .controller_address = 0x400e0a00,
969 .flash_wait_states = 5,
971 .size_bytes = 256 * 1024,
986 /*atsam4s4a - LQFP48/QFN48*/
988 .chipid_cidr = 0x288b09e0,
989 .name = "at91sam4s4a",
990 .total_flash_size = 256 * 1024,
991 .total_sram_size = 64 * 1024,
1001 .base_address = FLASH_BANK_BASE_S,
1002 .controller_address = 0x400e0a00,
1003 .flash_wait_states = 5,
1005 .size_bytes = 256 * 1024,
1007 .sector_size = 8192,
1020 /*atsam4s2c - LQFP100/BGA100*/
1022 .chipid_cidr = 0x28ab07e0,
1023 .name = "at91sam4s2c",
1024 .total_flash_size = 128 * 1024,
1025 .total_sram_size = 64 * 1024,
1035 .base_address = FLASH_BANK_BASE_S,
1036 .controller_address = 0x400e0a00,
1037 .flash_wait_states = 5,
1039 .size_bytes = 128 * 1024,
1041 .sector_size = 8192,
1054 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1056 .chipid_cidr = 0x289b07e0,
1057 .name = "at91sam4s2b",
1058 .total_flash_size = 128 * 1024,
1059 .total_sram_size = 64 * 1024,
1069 .base_address = FLASH_BANK_BASE_S,
1070 .controller_address = 0x400e0a00,
1071 .flash_wait_states = 5,
1073 .size_bytes = 128 * 1024,
1075 .sector_size = 8192,
1088 /*atsam4s2a - LQFP48/QFN48*/
1090 .chipid_cidr = 0x288b07e0,
1091 .name = "at91sam4s2a",
1092 .total_flash_size = 128 * 1024,
1093 .total_sram_size = 64 * 1024,
1103 .base_address = FLASH_BANK_BASE_S,
1104 .controller_address = 0x400e0a00,
1105 .flash_wait_states = 5,
1107 .size_bytes = 128 * 1024,
1109 .sector_size = 8192,
1122 /*at91sam4sd32c - LQFP100/BGA100*/
1124 .chipid_cidr = 0x29a70ee0,
1125 .name = "at91sam4sd32c",
1126 .total_flash_size = 2048 * 1024,
1127 .total_sram_size = 160 * 1024,
1138 .base_address = FLASH_BANK0_BASE_SD,
1139 .controller_address = 0x400e0a00,
1140 .flash_wait_states = 5,
1142 .size_bytes = 1024 * 1024,
1144 .sector_size = 8192,
1154 .base_address = FLASH_BANK1_BASE_2048K_SD,
1155 .controller_address = 0x400e0c00,
1156 .flash_wait_states = 5,
1158 .size_bytes = 1024 * 1024,
1160 .sector_size = 8192,
1166 /*at91sam4sd32b - LQFP64/BGA64*/
1168 .chipid_cidr = 0x29970ee0,
1169 .name = "at91sam4sd32b",
1170 .total_flash_size = 2048 * 1024,
1171 .total_sram_size = 160 * 1024,
1182 .base_address = FLASH_BANK0_BASE_SD,
1183 .controller_address = 0x400e0a00,
1184 .flash_wait_states = 5,
1186 .size_bytes = 1024 * 1024,
1188 .sector_size = 8192,
1198 .base_address = FLASH_BANK1_BASE_2048K_SD,
1199 .controller_address = 0x400e0c00,
1200 .flash_wait_states = 5,
1202 .size_bytes = 1024 * 1024,
1204 .sector_size = 8192,
1210 /*at91sam4sd16c - LQFP100/BGA100*/
1212 .chipid_cidr = 0x29a70ce0,
1213 .name = "at91sam4sd16c",
1214 .total_flash_size = 1024 * 1024,
1215 .total_sram_size = 160 * 1024,
1226 .base_address = FLASH_BANK0_BASE_SD,
1227 .controller_address = 0x400e0a00,
1228 .flash_wait_states = 5,
1230 .size_bytes = 512 * 1024,
1232 .sector_size = 8192,
1242 .base_address = FLASH_BANK1_BASE_1024K_SD,
1243 .controller_address = 0x400e0c00,
1244 .flash_wait_states = 5,
1246 .size_bytes = 512 * 1024,
1248 .sector_size = 8192,
1254 /*at91sam4sd16b - LQFP64/BGA64*/
1256 .chipid_cidr = 0x29970ce0,
1257 .name = "at91sam4sd16b",
1258 .total_flash_size = 1024 * 1024,
1259 .total_sram_size = 160 * 1024,
1270 .base_address = FLASH_BANK0_BASE_SD,
1271 .controller_address = 0x400e0a00,
1272 .flash_wait_states = 5,
1274 .size_bytes = 512 * 1024,
1276 .sector_size = 8192,
1286 .base_address = FLASH_BANK1_BASE_1024K_SD,
1287 .controller_address = 0x400e0c00,
1288 .flash_wait_states = 5,
1290 .size_bytes = 512 * 1024,
1292 .sector_size = 8192,
1300 .chipid_cidr = 0x247e0ae0,
1301 .name = "atsamg53n19",
1302 .total_flash_size = 512 * 1024,
1303 .total_sram_size = 96 * 1024,
1314 .base_address = FLASH_BANK_BASE_S,
1315 .controller_address = 0x400e0a00,
1316 .flash_wait_states = 5,
1318 .size_bytes = 512 * 1024,
1320 .sector_size = 8192,
1335 .chipid_cidr = 0x24470ae0,
1336 .name = "atsamg55g19",
1337 .total_flash_size = 512 * 1024,
1338 .total_sram_size = 160 * 1024,
1349 .base_address = FLASH_BANK_BASE_S,
1350 .controller_address = 0x400e0a00,
1351 .flash_wait_states = 5,
1353 .size_bytes = 512 * 1024,
1355 .sector_size = 8192,
1369 .chipid_cidr = 0x24570ae0,
1370 .name = "atsamg55j19",
1371 .total_flash_size = 512 * 1024,
1372 .total_sram_size = 160 * 1024,
1383 .base_address = FLASH_BANK_BASE_S,
1384 .controller_address = 0x400e0a00,
1385 .flash_wait_states = 5,
1387 .size_bytes = 512 * 1024,
1389 .sector_size = 8192,
1409 /***********************************************************************
1410 **********************************************************************
1411 **********************************************************************
1412 **********************************************************************
1413 **********************************************************************
1414 **********************************************************************/
1415 /* *ATMEL* style code - from the SAM4 driver code */
1418 * Get the current status of the EEFC and
1419 * the value of some status bits (LOCKE, PROGE).
1420 * @param pPrivate - info about the bank
1421 * @param v - result goes here
1423 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
1426 r = target_read_u32(pPrivate->pChip->target,
1427 pPrivate->controller_address + offset_EFC_FSR,
1429 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1431 ((unsigned int)((*v >> 2) & 1)),
1432 ((unsigned int)((*v >> 1) & 1)),
1433 ((unsigned int)((*v >> 0) & 1)));
1439 * Get the result of the last executed command.
1440 * @param pPrivate - info about the bank
1441 * @param v - result goes here
1443 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
1447 r = target_read_u32(pPrivate->pChip->target,
1448 pPrivate->controller_address + offset_EFC_FRR,
1452 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1456 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
1457 unsigned command, unsigned argument)
1466 /* Check command & argument */
1469 case AT91C_EFC_FCMD_WP:
1470 case AT91C_EFC_FCMD_WPL:
1471 case AT91C_EFC_FCMD_EWP:
1472 case AT91C_EFC_FCMD_EWPL:
1473 /* case AT91C_EFC_FCMD_EPL: */
1474 case AT91C_EFC_FCMD_EPA:
1475 case AT91C_EFC_FCMD_SLB:
1476 case AT91C_EFC_FCMD_CLB:
1477 n = (pPrivate->size_bytes / pPrivate->page_size);
1479 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1482 case AT91C_EFC_FCMD_SFB:
1483 case AT91C_EFC_FCMD_CFB:
1484 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1485 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1486 pPrivate->pChip->details.n_gpnvms);
1490 case AT91C_EFC_FCMD_GETD:
1491 case AT91C_EFC_FCMD_EA:
1492 case AT91C_EFC_FCMD_GLB:
1493 case AT91C_EFC_FCMD_GFB:
1494 case AT91C_EFC_FCMD_STUI:
1495 case AT91C_EFC_FCMD_SPUI:
1497 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1500 LOG_ERROR("Unknown command %d", command);
1504 if (command == AT91C_EFC_FCMD_SPUI) {
1505 /* this is a very special situation. */
1506 /* Situation (1) - error/retry - see below */
1507 /* And we are being called recursively */
1508 /* Situation (2) - normal, finished reading unique id */
1510 /* it should be "ready" */
1511 EFC_GetStatus(pPrivate, &v);
1513 /* then it is ready */
1517 /* we have done this before */
1518 /* the controller is not responding. */
1519 LOG_ERROR("flash controller(%d) is not ready! Error",
1520 pPrivate->bank_number);
1524 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1525 pPrivate->bank_number);
1526 /* we do that by issuing the *STOP* command */
1527 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1528 /* above is recursive, and further recursion is blocked by */
1529 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1535 v = (0x5A << 24) | (argument << 8) | command;
1536 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1537 r = target_write_u32(pPrivate->pBank->target,
1538 pPrivate->controller_address + offset_EFC_FCR, v);
1540 LOG_DEBUG("Error Write failed");
1545 * Performs the given command and wait until its completion (or an error).
1546 * @param pPrivate - info about the bank
1547 * @param command - Command to perform.
1548 * @param argument - Optional command argument.
1549 * @param status - put command status bits here
1551 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1559 int64_t ms_now, ms_end;
1565 r = EFC_StartCommand(pPrivate, command, argument);
1569 ms_end = 10000 + timeval_ms();
1572 r = EFC_GetStatus(pPrivate, &v);
1575 ms_now = timeval_ms();
1576 if (ms_now > ms_end) {
1578 LOG_ERROR("Command timeout");
1581 } while ((v & 1) == 0);
1585 *status = (v & 0x6);
1591 * Read the unique ID.
1592 * @param pPrivate - info about the bank
1593 * The unique ID is stored in the 'pPrivate' structure.
1595 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1601 pPrivate->pChip->cfg.unique_id[0] = 0;
1602 pPrivate->pChip->cfg.unique_id[1] = 0;
1603 pPrivate->pChip->cfg.unique_id[2] = 0;
1604 pPrivate->pChip->cfg.unique_id[3] = 0;
1607 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1611 for (x = 0; x < 4; x++) {
1612 r = target_read_u32(pPrivate->pChip->target,
1613 pPrivate->pBank->base + (x * 4),
1617 pPrivate->pChip->cfg.unique_id[x] = v;
1620 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1621 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1623 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1624 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1625 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1626 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1632 * Erases the entire flash.
1633 * @param pPrivate - the info about the bank.
1635 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1638 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1642 * Erases the entire flash.
1643 * @param pPrivate - the info about the bank.
1645 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1670 /* AT91C_EFC_FCMD_EPA
1671 * According to the datasheet FARG[15:2] defines the page from which
1672 * the erase will start.This page must be modulo 4, 8, 16 or 32
1673 * according to the number of pages to erase. FARG[1:0] defines the
1674 * number of pages to be erased. Previously (firstpage << 2) was used
1675 * to conform to this, seems it should not be shifted...
1677 return EFC_PerformCommand(pPrivate,
1678 /* send Erase Page */
1680 (firstPage) | erasePages,
1685 * Gets current GPNVM state.
1686 * @param pPrivate - info about the bank.
1687 * @param gpnvm - GPNVM bit index.
1688 * @param puthere - result stored here.
1690 /* ------------------------------------------------------------------------------ */
1691 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1697 if (pPrivate->bank_number != 0) {
1698 LOG_ERROR("GPNVM only works with Bank0");
1702 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1703 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1704 gpnvm, pPrivate->pChip->details.n_gpnvms);
1708 /* Get GPNVMs status */
1709 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1710 if (r != ERROR_OK) {
1711 LOG_ERROR("Failed");
1715 r = EFC_GetResult(pPrivate, &v);
1718 /* Check if GPNVM is set */
1719 /* get the bit and make it a 0/1 */
1720 *puthere = (v >> gpnvm) & 1;
1727 * Clears the selected GPNVM bit.
1728 * @param pPrivate info about the bank
1729 * @param gpnvm GPNVM index.
1730 * @returns 0 if successful; otherwise returns an error code.
1732 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1738 if (pPrivate->bank_number != 0) {
1739 LOG_ERROR("GPNVM only works with Bank0");
1743 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1744 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1745 gpnvm, pPrivate->pChip->details.n_gpnvms);
1749 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1750 if (r != ERROR_OK) {
1751 LOG_DEBUG("Failed: %d", r);
1754 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1755 LOG_DEBUG("End: %d", r);
1760 * Sets the selected GPNVM bit.
1761 * @param pPrivate info about the bank
1762 * @param gpnvm GPNVM index.
1764 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1769 if (pPrivate->bank_number != 0) {
1770 LOG_ERROR("GPNVM only works with Bank0");
1774 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1775 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1776 gpnvm, pPrivate->pChip->details.n_gpnvms);
1780 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1788 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1794 * Returns a bit field (at most 64) of locked regions within a page.
1795 * @param pPrivate info about the bank
1796 * @param v where to store locked bits
1798 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1802 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1803 if (r == ERROR_OK) {
1804 EFC_GetResult(pPrivate, v);
1805 EFC_GetResult(pPrivate, v);
1806 EFC_GetResult(pPrivate, v);
1807 r = EFC_GetResult(pPrivate, v);
1809 LOG_DEBUG("End: %d", r);
1814 * Unlocks all the regions in the given address range.
1815 * @param pPrivate info about the bank
1816 * @param start_sector first sector to unlock
1817 * @param end_sector last (inclusive) to unlock
1820 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1821 unsigned start_sector,
1822 unsigned end_sector)
1827 uint32_t pages_per_sector;
1829 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1831 /* Unlock all pages */
1832 while (start_sector <= end_sector) {
1833 pg = start_sector * pages_per_sector;
1835 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1846 * @param pPrivate - info about the bank
1847 * @param start_sector - first sector to lock
1848 * @param end_sector - last sector (inclusive) to lock
1850 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1851 unsigned start_sector,
1852 unsigned end_sector)
1856 uint32_t pages_per_sector;
1859 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1861 /* Lock all pages */
1862 while (start_sector <= end_sector) {
1863 pg = start_sector * pages_per_sector;
1865 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1873 /****** END SAM4 CODE ********/
1875 /* begin helpful debug code */
1876 /* print the fieldname, the field value, in dec & hex, and return field value */
1877 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1878 const char *regname,
1887 /* extract the field */
1889 v = v & ((1 << width)-1);
1898 /* show the basics */
1899 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1900 REG_NAME_WIDTH, regname,
1906 static const char _unknown[] = "unknown";
1907 static const char *const eproc_names[] = {
1908 "Cortex-M7", /* 0 */
1911 "Cortex-M3", /* 3 */
1913 "arm926ejs", /* 5 */
1914 "Cortex-A5", /* 6 */
1915 "Cortex-M4", /* 7 */
1926 #define nvpsize2 nvpsize /* these two tables are identical */
1927 static const char *const nvpsize[] = {
1930 "16K bytes", /* 2 */
1931 "32K bytes", /* 3 */
1933 "64K bytes", /* 5 */
1935 "128K bytes", /* 7 */
1936 "160K bytes", /* 8 */
1937 "256K bytes", /* 9 */
1938 "512K bytes", /* 10 */
1940 "1024K bytes", /* 12 */
1942 "2048K bytes", /* 14 */
1946 static const char *const sramsize[] = {
1947 "48K Bytes", /* 0 */
1951 "112K Bytes", /* 4 */
1953 "80K Bytes", /* 6 */
1954 "160K Bytes", /* 7 */
1956 "16K Bytes", /* 9 */
1957 "32K Bytes", /* 10 */
1958 "64K Bytes", /* 11 */
1959 "128K Bytes", /* 12 */
1960 "256K Bytes", /* 13 */
1961 "96K Bytes", /* 14 */
1962 "512K Bytes", /* 15 */
1966 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1967 { 0x19, "AT91SAM9xx Series" },
1968 { 0x29, "AT91SAM9XExx Series" },
1969 { 0x34, "AT91x34 Series" },
1970 { 0x37, "CAP7 Series" },
1971 { 0x39, "CAP9 Series" },
1972 { 0x3B, "CAP11 Series" },
1973 { 0x3C, "ATSAM4E" },
1974 { 0x40, "AT91x40 Series" },
1975 { 0x42, "AT91x42 Series" },
1976 { 0x43, "SAMG51 Series"
1978 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
1979 { 0x45, "SAMG55 Series (64-pin)" },
1980 { 0x47, "SAMG53 Series"
1982 { 0x55, "AT91x55 Series" },
1983 { 0x60, "AT91SAM7Axx Series" },
1984 { 0x61, "AT91SAM7AQxx Series" },
1985 { 0x63, "AT91x63 Series" },
1986 { 0x64, "SAM4CxxC (100-pin version)" },
1987 { 0x66, "SAM4CxxE (144-pin version)" },
1988 { 0x70, "AT91SAM7Sxx Series" },
1989 { 0x71, "AT91SAM7XCxx Series" },
1990 { 0x72, "AT91SAM7SExx Series" },
1991 { 0x73, "AT91SAM7Lxx Series" },
1992 { 0x75, "AT91SAM7Xxx Series" },
1993 { 0x76, "AT91SAM7SLxx Series" },
1994 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1995 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1996 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1997 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1998 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1999 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2000 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2001 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2002 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2003 { 0x92, "AT91x92 Series" },
2004 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2005 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2006 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2007 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2008 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2009 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2010 { 0xA5, "ATSAM5A" },
2011 { 0xF0, "AT75Cxx Series" },
2015 static const char *const nvptype[] = {
2017 "romless or onchip flash", /* 1 */
2018 "embedded flash memory",/* 2 */
2019 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2020 "sram emulating flash", /* 4 */
2026 static const char *_yes_or_no(uint32_t v)
2034 static const char *const _rc_freq[] = {
2035 "4 MHz", "8 MHz", "12 MHz", "reserved"
2038 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
2043 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2044 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2045 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2046 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2047 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2048 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2049 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2050 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2052 pChip->cfg.rc_freq = 0;
2056 pChip->cfg.rc_freq = 0;
2059 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2062 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2065 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2070 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2071 LOG_USER("(startup clks, time= %f uSecs)",
2072 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2073 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2074 LOG_USER("(mainosc source: %s)",
2075 v ? "external xtal" : "internal RC");
2077 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2078 LOG_USER("(clock failure enabled: %s)",
2082 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
2088 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2091 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2092 LOG_USER("%s", eproc_names[v]);
2094 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2095 LOG_USER("%s", nvpsize[v]);
2097 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2098 LOG_USER("%s", nvpsize2[v]);
2100 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2101 LOG_USER("%s", sramsize[v]);
2103 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2105 for (x = 0; archnames[x].name; x++) {
2106 if (v == archnames[x].value) {
2107 cp = archnames[x].name;
2114 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2115 LOG_USER("%s", nvptype[v]);
2117 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2118 LOG_USER("(exists: %s)", _yes_or_no(v));
2121 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
2125 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2126 LOG_USER("(main ready: %s)", _yes_or_no(v));
2128 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2130 v = (v * pChip->cfg.slow_freq) / 16;
2131 pChip->cfg.mainosc_freq = v;
2133 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2135 (uint32_t)(pChip->cfg.slow_freq / 1000),
2136 (uint32_t)(pChip->cfg.slow_freq % 1000));
2139 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
2141 uint32_t mula, diva;
2143 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2145 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2147 pChip->cfg.plla_freq = 0;
2149 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2151 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2152 else if (diva >= 1) {
2153 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2154 LOG_USER("\tPLLA Freq: %3.03f MHz",
2155 _tomhz(pChip->cfg.plla_freq));
2159 static void sam4_explain_mckr(struct sam4_chip *pChip)
2161 uint32_t css, pres, fin = 0;
2163 const char *cp = NULL;
2165 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2168 fin = pChip->cfg.slow_freq;
2172 fin = pChip->cfg.mainosc_freq;
2176 fin = pChip->cfg.plla_freq;
2180 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2181 fin = 480 * 1000 * 1000;
2185 cp = "upll (*ERROR* UPLL is disabled)";
2193 LOG_USER("%s (%3.03f Mhz)",
2196 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2197 switch (pres & 0x07) {
2200 cp = "selected clock";
2234 LOG_USER("(%s)", cp);
2236 /* sam4 has a *SINGLE* clock - */
2237 /* other at91 series parts have divisors for these. */
2238 pChip->cfg.cpu_freq = fin;
2239 pChip->cfg.mclk_freq = fin;
2240 pChip->cfg.fclk_freq = fin;
2241 LOG_USER("\t\tResult CPU Freq: %3.03f",
2246 static struct sam4_chip *target2sam4(struct target *pTarget)
2248 struct sam4_chip *pChip;
2250 if (pTarget == NULL)
2253 pChip = all_sam4_chips;
2255 if (pChip->target == pTarget)
2256 break; /* return below */
2258 pChip = pChip->next;
2264 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
2266 /* this function exists to help */
2267 /* keep funky offsetof() errors */
2268 /* and casting from causing bugs */
2270 /* By using prototypes - we can detect what would */
2271 /* be casting errors. */
2273 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2277 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2279 NAME), # NAME, FUNC }
2280 static const struct sam4_reg_list sam4_all_regs[] = {
2281 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2282 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2283 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2284 SAM4_ENTRY(CKGR_UCKR, NULL),
2285 SAM4_ENTRY(PMC_FSMR, NULL),
2286 SAM4_ENTRY(PMC_FSPR, NULL),
2287 SAM4_ENTRY(PMC_IMR, NULL),
2288 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2289 SAM4_ENTRY(PMC_PCK0, NULL),
2290 SAM4_ENTRY(PMC_PCK1, NULL),
2291 SAM4_ENTRY(PMC_PCK2, NULL),
2292 SAM4_ENTRY(PMC_PCSR, NULL),
2293 SAM4_ENTRY(PMC_SCSR, NULL),
2294 SAM4_ENTRY(PMC_SR, NULL),
2295 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2296 SAM4_ENTRY(CHIPID_EXID, NULL),
2297 /* TERMINATE THE LIST */
2302 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2304 return bank->driver_priv;
2308 * Given a pointer to where it goes in the structure,
2309 * determine the register name, address from the all registers table.
2311 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
2313 const struct sam4_reg_list *pReg;
2315 pReg = &(sam4_all_regs[0]);
2316 while (pReg->name) {
2317 uint32_t *pPossible;
2319 /* calculate where this one go.. */
2320 /* it is "possibly" this register. */
2322 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2324 /* well? Is it this register */
2325 if (pPossible == goes_here) {
2333 /* This is *TOTAL*PANIC* - we are totally screwed. */
2334 LOG_ERROR("INVALID SAM4 REGISTER");
2338 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
2340 const struct sam4_reg_list *pReg;
2343 pReg = sam4_GetReg(pChip, goes_here);
2347 r = target_read_u32(pChip->target, pReg->address, goes_here);
2348 if (r != ERROR_OK) {
2349 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2350 pReg->name, (unsigned)(pReg->address), r);
2355 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
2358 const struct sam4_reg_list *pReg;
2360 pReg = &(sam4_all_regs[0]);
2361 while (pReg->name) {
2362 r = sam4_ReadThisReg(pChip,
2363 sam4_get_reg_ptr(&(pChip->cfg), pReg));
2364 if (r != ERROR_OK) {
2365 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2366 pReg->name, ((unsigned)(pReg->address)), r);
2375 static int sam4_GetInfo(struct sam4_chip *pChip)
2377 const struct sam4_reg_list *pReg;
2380 pReg = &(sam4_all_regs[0]);
2381 while (pReg->name) {
2382 /* display all regs */
2383 LOG_DEBUG("Start: %s", pReg->name);
2384 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
2385 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2390 if (pReg->explain_func)
2391 (*(pReg->explain_func))(pChip);
2392 LOG_DEBUG("End: %s", pReg->name);
2395 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2396 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2397 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2398 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2399 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2401 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2402 pChip->cfg.unique_id[0],
2403 pChip->cfg.unique_id[1],
2404 pChip->cfg.unique_id[2],
2405 pChip->cfg.unique_id[3]);
2410 static int sam4_protect_check(struct flash_bank *bank)
2413 uint32_t v[4] = {0};
2415 struct sam4_bank_private *pPrivate;
2418 if (bank->target->state != TARGET_HALTED) {
2419 LOG_ERROR("Target not halted");
2420 return ERROR_TARGET_NOT_HALTED;
2423 pPrivate = get_sam4_bank_private(bank);
2425 LOG_ERROR("no private for this bank?");
2428 if (!(pPrivate->probed))
2429 return ERROR_FLASH_BANK_NOT_PROBED;
2431 r = FLASHD_GetLockBits(pPrivate, v);
2432 if (r != ERROR_OK) {
2433 LOG_DEBUG("Failed: %d", r);
2437 for (x = 0; x < pPrivate->nsectors; x++)
2438 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2443 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2445 struct sam4_chip *pChip;
2447 pChip = all_sam4_chips;
2449 /* is this an existing chip? */
2451 if (pChip->target == bank->target)
2453 pChip = pChip->next;
2457 /* this is a *NEW* chip */
2458 pChip = calloc(1, sizeof(struct sam4_chip));
2460 LOG_ERROR("NO RAM!");
2463 pChip->target = bank->target;
2464 /* insert at head */
2465 pChip->next = all_sam4_chips;
2466 all_sam4_chips = pChip;
2467 pChip->target = bank->target;
2468 /* assumption is this runs at 32khz */
2469 pChip->cfg.slow_freq = 32768;
2473 switch (bank->base) {
2475 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2476 "[at91sam4s series] )",
2477 ((unsigned int)(bank->base)),
2478 ((unsigned int)(FLASH_BANK_BASE_S)));
2482 /* at91sam4s series only has bank 0*/
2483 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2484 case FLASH_BANK_BASE_S:
2485 case FLASH_BANK_BASE_C:
2486 bank->driver_priv = &(pChip->details.bank[0]);
2487 bank->bank_number = 0;
2488 pChip->details.bank[0].pChip = pChip;
2489 pChip->details.bank[0].pBank = bank;
2492 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2493 case FLASH_BANK1_BASE_1024K_SD:
2494 case FLASH_BANK1_BASE_2048K_SD:
2495 case FLASH_BANK1_BASE_C32:
2496 bank->driver_priv = &(pChip->details.bank[1]);
2497 bank->bank_number = 1;
2498 pChip->details.bank[1].pChip = pChip;
2499 pChip->details.bank[1].pBank = bank;
2503 /* we initialize after probing. */
2508 * Remove all chips from the internal list without distingushing which one
2509 * is owned by this bank. This simplification works only for one shot
2510 * deallocation like current flash_free_all_banks()
2512 static void sam4_free_driver_priv(struct flash_bank *bank)
2514 struct sam4_chip *chip = all_sam4_chips;
2516 struct sam4_chip *next = chip->next;
2520 all_sam4_chips = NULL;
2523 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2525 const struct sam4_chip_details *pDetails;
2526 struct sam4_chip *pChip;
2527 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2531 pDetails = all_sam4_details;
2532 while (pDetails->name) {
2533 /* Compare cidr without version bits */
2534 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2539 if (pDetails->name == NULL) {
2540 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2541 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2542 /* Help the victim, print details about the chip */
2543 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2544 pPrivate->pChip->cfg.CHIPID_CIDR);
2545 sam4_explain_chipid_cidr(pPrivate->pChip);
2548 LOG_INFO("SAM4 Found chip %s, CIDR 0x%08x", pDetails->name, pDetails->chipid_cidr);
2551 /* DANGER: THERE ARE DRAGONS HERE */
2553 /* get our pChip - it is going */
2554 /* to be over-written shortly */
2555 pChip = pPrivate->pChip;
2557 /* Note that, in reality: */
2559 /* pPrivate = &(pChip->details.bank[0]) */
2560 /* or pPrivate = &(pChip->details.bank[1]) */
2563 /* save the "bank" pointers */
2564 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2565 saved_banks[x] = pChip->details.bank[x].pBank;
2567 /* Overwrite the "details" structure. */
2568 memcpy(&(pPrivate->pChip->details),
2570 sizeof(pPrivate->pChip->details));
2572 /* now fix the ghosted pointers */
2573 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2574 pChip->details.bank[x].pChip = pChip;
2575 pChip->details.bank[x].pBank = saved_banks[x];
2578 /* update the *BANK*SIZE* */
2584 static int _sam4_probe(struct flash_bank *bank, int noise)
2588 struct sam4_bank_private *pPrivate;
2591 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2592 if (bank->target->state != TARGET_HALTED) {
2593 LOG_ERROR("Target not halted");
2594 return ERROR_TARGET_NOT_HALTED;
2597 pPrivate = get_sam4_bank_private(bank);
2599 LOG_ERROR("Invalid/unknown bank number");
2603 r = sam4_ReadAllRegs(pPrivate->pChip);
2608 if (pPrivate->pChip->probed)
2609 r = sam4_GetInfo(pPrivate->pChip);
2611 r = sam4_GetDetails(pPrivate);
2615 /* update the flash bank size */
2616 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2617 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2618 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2619 LOG_INFO("SAM4 Set flash bank to %08X - %08X, idx %d", bank->base, bank->base + bank->size, x);
2624 if (bank->sectors == NULL) {
2625 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2626 if (bank->sectors == NULL) {
2627 LOG_ERROR("No memory!");
2630 bank->num_sectors = pPrivate->nsectors;
2632 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2633 bank->sectors[x].size = pPrivate->sector_size;
2634 bank->sectors[x].offset = x * (pPrivate->sector_size);
2635 /* mark as unknown */
2636 bank->sectors[x].is_erased = -1;
2637 bank->sectors[x].is_protected = -1;
2641 pPrivate->probed = 1;
2643 r = sam4_protect_check(bank);
2647 LOG_DEBUG("Bank = %d, nbanks = %d",
2648 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2649 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2650 /* read unique id, */
2651 /* it appears to be associated with the *last* flash bank. */
2652 FLASHD_ReadUniqueID(pPrivate);
2658 static int sam4_probe(struct flash_bank *bank)
2660 return _sam4_probe(bank, 1);
2663 static int sam4_auto_probe(struct flash_bank *bank)
2665 return _sam4_probe(bank, 0);
2668 static int sam4_erase(struct flash_bank *bank, int first, int last)
2670 struct sam4_bank_private *pPrivate;
2674 /*16 pages equals 8KB - Same size as a lock region*/
2679 if (bank->target->state != TARGET_HALTED) {
2680 LOG_ERROR("Target not halted");
2681 return ERROR_TARGET_NOT_HALTED;
2684 r = sam4_auto_probe(bank);
2685 if (r != ERROR_OK) {
2686 LOG_DEBUG("Here,r=%d", r);
2690 pPrivate = get_sam4_bank_private(bank);
2691 if (!(pPrivate->probed))
2692 return ERROR_FLASH_BANK_NOT_PROBED;
2694 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2697 return FLASHD_EraseEntireBank(pPrivate);
2699 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2700 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
2701 for (i = first; i <= last; i++) {
2702 /*16 pages equals 8KB - Same size as a lock region*/
2703 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2704 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
2706 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
2708 if (status & (1 << 2)) {
2709 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
2712 if (status & (1 << 1)) {
2713 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
2721 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
2723 struct sam4_bank_private *pPrivate;
2727 if (bank->target->state != TARGET_HALTED) {
2728 LOG_ERROR("Target not halted");
2729 return ERROR_TARGET_NOT_HALTED;
2732 pPrivate = get_sam4_bank_private(bank);
2733 if (!(pPrivate->probed))
2734 return ERROR_FLASH_BANK_NOT_PROBED;
2737 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2739 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2740 LOG_DEBUG("End: r=%d", r);
2746 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2751 adr = pagenum * pPrivate->page_size;
2752 adr = adr + pPrivate->base_address;
2754 r = target_read_memory(pPrivate->pChip->target,
2756 4, /* THIS*MUST*BE* in 32bit values */
2757 pPrivate->page_size / 4,
2760 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2761 (unsigned int)(adr));
2765 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2769 uint32_t fmr; /* EEFC Flash Mode Register */
2772 adr = pagenum * pPrivate->page_size;
2773 adr = (adr + pPrivate->base_address);
2775 /* Get flash mode register value */
2776 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2778 LOG_DEBUG("Error Read failed: read flash mode register");
2780 /* Clear flash wait state field */
2783 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2784 fmr |= (pPrivate->flash_wait_states << 8);
2786 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2787 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2789 LOG_DEBUG("Error Write failed: set flash mode register");
2791 /* 1st sector 8kBytes - page 0 - 15*/
2792 /* 2nd sector 8kBytes - page 16 - 30*/
2793 /* 3rd sector 48kBytes - page 31 - 127*/
2794 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2795 r = target_write_memory(pPrivate->pChip->target,
2797 4, /* THIS*MUST*BE* in 32bit values */
2798 pPrivate->page_size / 4,
2800 if (r != ERROR_OK) {
2801 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2802 (unsigned int)(adr));
2806 r = EFC_PerformCommand(pPrivate,
2807 /* send Erase & Write Page */
2808 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2813 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2814 (unsigned int)(adr));
2815 if (status & (1 << 2)) {
2816 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2819 if (status & (1 << 1)) {
2820 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2826 static int sam4_write(struct flash_bank *bank,
2827 const uint8_t *buffer,
2835 unsigned page_offset;
2836 struct sam4_bank_private *pPrivate;
2837 uint8_t *pagebuffer;
2839 /* incase we bail further below, set this to null */
2842 /* ignore dumb requests */
2848 if (bank->target->state != TARGET_HALTED) {
2849 LOG_ERROR("Target not halted");
2850 r = ERROR_TARGET_NOT_HALTED;
2854 pPrivate = get_sam4_bank_private(bank);
2855 if (!(pPrivate->probed)) {
2856 r = ERROR_FLASH_BANK_NOT_PROBED;
2860 if ((offset + count) > pPrivate->size_bytes) {
2861 LOG_ERROR("Flash write error - past end of bank");
2862 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2863 (unsigned int)(offset),
2864 (unsigned int)(count),
2865 (unsigned int)(pPrivate->size_bytes));
2870 pagebuffer = malloc(pPrivate->page_size);
2872 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2877 /* what page do we start & end in? */
2878 page_cur = offset / pPrivate->page_size;
2879 page_end = (offset + count - 1) / pPrivate->page_size;
2881 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2882 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2884 /* Special case: all one page */
2887 /* (1) non-aligned start */
2888 /* (2) body pages */
2889 /* (3) non-aligned end. */
2891 /* Handle special case - all one page. */
2892 if (page_cur == page_end) {
2893 LOG_DEBUG("Special case, all in one page");
2894 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2898 page_offset = (offset & (pPrivate->page_size-1));
2899 memcpy(pagebuffer + page_offset,
2903 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2910 /* non-aligned start */
2911 page_offset = offset & (pPrivate->page_size - 1);
2913 LOG_DEBUG("Not-Aligned start");
2914 /* read the partial */
2915 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2919 /* over-write with new data */
2920 n = (pPrivate->page_size - page_offset);
2921 memcpy(pagebuffer + page_offset,
2925 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2935 /* By checking that offset is correct here, we also
2936 fix a clang warning */
2937 assert(offset % pPrivate->page_size == 0);
2939 /* intermediate large pages */
2940 /* also - the final *terminal* */
2941 /* if that terminal page is a full page */
2942 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2943 (int)page_cur, (int)page_end, (unsigned int)(count));
2945 while ((page_cur < page_end) &&
2946 (count >= pPrivate->page_size)) {
2947 r = sam4_page_write(pPrivate, page_cur, buffer);
2950 count -= pPrivate->page_size;
2951 buffer += pPrivate->page_size;
2955 /* terminal partial page? */
2957 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2958 /* we have a partial page */
2959 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2962 /* data goes at start */
2963 memcpy(pagebuffer, buffer, count);
2964 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2976 COMMAND_HANDLER(sam4_handle_info_command)
2978 struct sam4_chip *pChip;
2979 pChip = get_current_sam4(CMD_CTX);
2986 /* bank0 must exist before we can do anything */
2987 if (pChip->details.bank[0].pBank == NULL) {
2990 command_print(CMD_CTX,
2991 "Please define bank %d via command: flash bank %s ... ",
2993 at91sam4_flash.name);
2997 /* if bank 0 is not probed, then probe it */
2998 if (!(pChip->details.bank[0].probed)) {
2999 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3003 /* above guarantees the "chip details" structure is valid */
3004 /* and thus, bank private areas are valid */
3005 /* and we have a SAM4 chip, what a concept! */
3007 /* auto-probe other banks, 0 done above */
3008 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3009 /* skip banks not present */
3010 if (!(pChip->details.bank[x].present))
3013 if (pChip->details.bank[x].pBank == NULL)
3016 if (pChip->details.bank[x].probed)
3019 r = sam4_auto_probe(pChip->details.bank[x].pBank);
3024 r = sam4_GetInfo(pChip);
3025 if (r != ERROR_OK) {
3026 LOG_DEBUG("Sam4Info, Failed %d", r);
3033 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3037 struct sam4_chip *pChip;
3039 pChip = get_current_sam4(CMD_CTX);
3043 if (pChip->target->state != TARGET_HALTED) {
3044 LOG_ERROR("sam4 - target not halted");
3045 return ERROR_TARGET_NOT_HALTED;
3048 if (pChip->details.bank[0].pBank == NULL) {
3049 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3050 at91sam4_flash.name);
3053 if (!pChip->details.bank[0].probed) {
3054 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3061 return ERROR_COMMAND_SYNTAX_ERROR;
3070 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3074 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3080 if (0 == strcmp("show", CMD_ARGV[0])) {
3084 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3085 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3088 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
3092 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3093 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3094 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
3097 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
3098 return ERROR_COMMAND_SYNTAX_ERROR;
3103 command_print(CMD_CTX, "Missing GPNVM number");
3104 return ERROR_COMMAND_SYNTAX_ERROR;
3107 if (0 == strcmp("set", CMD_ARGV[0]))
3108 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3109 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3110 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3111 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3113 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3114 r = ERROR_COMMAND_SYNTAX_ERROR;
3119 COMMAND_HANDLER(sam4_handle_slowclk_command)
3121 struct sam4_chip *pChip;
3123 pChip = get_current_sam4(CMD_CTX);
3135 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3137 /* absurd slow clock of 200Khz? */
3138 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3139 return ERROR_COMMAND_SYNTAX_ERROR;
3141 pChip->cfg.slow_freq = v;
3146 command_print(CMD_CTX, "Too many parameters");
3147 return ERROR_COMMAND_SYNTAX_ERROR;
3150 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3151 (int)(pChip->cfg.slow_freq / 1000),
3152 (int)(pChip->cfg.slow_freq % 1000));
3156 static const struct command_registration at91sam4_exec_command_handlers[] = {
3159 .handler = sam4_handle_gpnvm_command,
3160 .mode = COMMAND_EXEC,
3161 .usage = "[('clr'|'set'|'show') bitnum]",
3162 .help = "Without arguments, shows all bits in the gpnvm "
3163 "register. Otherwise, clears, sets, or shows one "
3164 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3168 .handler = sam4_handle_info_command,
3169 .mode = COMMAND_EXEC,
3170 .help = "Print information about the current at91sam4 chip"
3171 "and its flash configuration.",
3175 .handler = sam4_handle_slowclk_command,
3176 .mode = COMMAND_EXEC,
3177 .usage = "[clock_hz]",
3178 .help = "Display or set the slowclock frequency "
3179 "(default 32768 Hz).",
3181 COMMAND_REGISTRATION_DONE
3183 static const struct command_registration at91sam4_command_handlers[] = {
3186 .mode = COMMAND_ANY,
3187 .help = "at91sam4 flash command group",
3189 .chain = at91sam4_exec_command_handlers,
3191 COMMAND_REGISTRATION_DONE
3194 struct flash_driver at91sam4_flash = {
3196 .commands = at91sam4_command_handlers,
3197 .flash_bank_command = sam4_flash_bank_command,
3198 .erase = sam4_erase,
3199 .protect = sam4_protect,
3200 .write = sam4_write,
3201 .read = default_flash_read,
3202 .probe = sam4_probe,
3203 .auto_probe = sam4_auto_probe,
3204 .erase_check = default_flash_blank_check,
3205 .protect_check = sam4_protect_check,
3206 .free_driver_priv = sam4_free_driver_priv,