1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
64 #include <helper/time_support.h>
66 #define REG_NAME_WIDTH (12)
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
106 extern struct flash_driver at91sam4_flash;
108 static float _tomhz(uint32_t freq_hz)
112 f = ((float)(freq_hz)) / 1000000.0;
116 /* How the chip is configured. */
118 uint32_t unique_id[4];
122 uint32_t mainosc_freq;
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID;
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
168 struct sam4_bank_private {
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
176 /* so we can find the chip we belong to */
177 struct sam4_chip *pChip;
178 /* so we can find the original bank pointer */
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
183 uint32_t flash_wait_states;
187 unsigned sector_size;
191 struct sam4_chip_details {
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm[SAM4_N_NVM_BITS];
205 unsigned total_flash_size;
206 unsigned total_sram_size;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
214 struct sam4_chip *next;
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details;
219 struct target *target;
224 struct sam4_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam4_chip *pInfo);
229 static struct sam4_chip *all_sam4_chips;
231 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
234 static struct sam4_chip *p;
236 t = get_current_target(cmd_ctx);
238 command_print(cmd_ctx, "No current target?");
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd_ctx, "No SAM4 chips exist?");
255 command_print(cmd_ctx, "Cannot find SAM4 chip?");
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
269 .chipid_cidr = 0xA66D0EE0,
270 .name = "at91sam4c32e",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
286 .size_bytes = 1024 * 1024,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
301 .size_bytes = 1024 * 1024,
308 /* at91sam4c32c - LQFP100 */
310 .chipid_cidr = 0xA64D0EE0,
311 .name = "at91sam4c32c",
312 .total_flash_size = 2024 * 1024,
313 .total_sram_size = 256 * 1024,
323 .base_address = FLASH_BANK0_BASE_C32,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
327 .size_bytes = 1024 * 1024,
338 .base_address = FLASH_BANK1_BASE_C32,
339 .controller_address = 0x400e0c00,
340 .flash_wait_states = 5,
342 .size_bytes = 1024 * 1024,
349 /* at91sam4c16c - LQFP100 */
351 .chipid_cidr = 0xA64C0CE0,
352 .name = "at91sam4c16c",
353 .total_flash_size = 1024 * 1024,
354 .total_sram_size = 128 * 1024,
364 .base_address = FLASH_BANK_BASE_C,
365 .controller_address = 0x400e0a00,
366 .flash_wait_states = 5,
368 .size_bytes = 1024 * 1024,
382 /* at91sam4c8c - LQFP100 */
384 .chipid_cidr = 0xA64C0AE0,
385 .name = "at91sam4c8c",
386 .total_flash_size = 512 * 1024,
387 .total_sram_size = 128 * 1024,
397 .base_address = FLASH_BANK_BASE_C,
398 .controller_address = 0x400e0a00,
399 .flash_wait_states = 5,
401 .size_bytes = 512 * 1024,
415 /* at91sam4c4c (rev B) - LQFP100 */
417 .chipid_cidr = 0xA64C0CE5,
418 .name = "at91sam4c4c",
419 .total_flash_size = 256 * 1024,
420 .total_sram_size = 128 * 1024,
430 .base_address = FLASH_BANK_BASE_C,
431 .controller_address = 0x400e0a00,
432 .flash_wait_states = 5,
434 .size_bytes = 256 * 1024,
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
452 .chipid_cidr = 0xA3CC0CE0,
453 .name = "at91sam4e16e",
454 .total_flash_size = 1024 * 1024,
455 .total_sram_size = 128 * 1024,
465 .base_address = FLASH_BANK_BASE_S,
466 .controller_address = 0x400e0a00,
467 .flash_wait_states = 5,
469 .size_bytes = 1024 * 1024,
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
487 .chipid_cidr = 0x293B0AE0,
488 .name = "at91sam4n8a",
489 .total_flash_size = 512 * 1024,
490 .total_sram_size = 64 * 1024,
500 .base_address = FLASH_BANK_BASE_S,
501 .controller_address = 0x400e0a00,
502 .flash_wait_states = 5,
504 .size_bytes = 512 * 1024,
518 /*atsam4n8b - LQFP64/QFN64*/
520 .chipid_cidr = 0x294B0AE0,
521 .name = "at91sam4n8b",
522 .total_flash_size = 512 * 1024,
523 .total_sram_size = 64 * 1024,
533 .base_address = FLASH_BANK_BASE_S,
534 .controller_address = 0x400e0a00,
535 .flash_wait_states = 5,
537 .size_bytes = 512 * 1024,
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
553 .chipid_cidr = 0x295B0AE0,
554 .name = "at91sam4n8c",
555 .total_flash_size = 512 * 1024,
556 .total_sram_size = 64 * 1024,
566 .base_address = FLASH_BANK_BASE_S,
567 .controller_address = 0x400e0a00,
568 .flash_wait_states = 5,
570 .size_bytes = 512 * 1024,
584 /*atsam4n16b - LQFP64/QFN64*/
586 .chipid_cidr = 0x29460CE0,
587 .name = "at91sam4n16b",
588 .total_flash_size = 1024 * 1024,
589 .total_sram_size = 80 * 1024,
599 .base_address = FLASH_BANK_BASE_S,
600 .controller_address = 0x400e0a00,
601 .flash_wait_states = 5,
603 .size_bytes = 1024 * 1024,
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
619 .chipid_cidr = 0x29560CE0,
620 .name = "at91sam4n16c",
621 .total_flash_size = 1024 * 1024,
622 .total_sram_size = 80 * 1024,
632 .base_address = FLASH_BANK_BASE_S,
633 .controller_address = 0x400e0a00,
634 .flash_wait_states = 5,
636 .size_bytes = 1024 * 1024,
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
654 .chipid_cidr = 0x28AC0CE0,
655 .name = "at91sam4s16c",
656 .total_flash_size = 1024 * 1024,
657 .total_sram_size = 128 * 1024,
667 .base_address = FLASH_BANK_BASE_S,
668 .controller_address = 0x400e0a00,
669 .flash_wait_states = 5,
671 .size_bytes = 1024 * 1024,
685 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
687 .chipid_cidr = 0x289C0CE0,
688 .name = "at91sam4s16b",
689 .total_flash_size = 1024 * 1024,
690 .total_sram_size = 128 * 1024,
700 .base_address = FLASH_BANK_BASE_S,
701 .controller_address = 0x400e0a00,
702 .flash_wait_states = 5,
704 .size_bytes = 1024 * 1024,
718 /*atsam4sa16b - LQFP64/QFN64*/
720 .chipid_cidr = 0x28970CE0,
721 .name = "at91sam4sa16b",
722 .total_flash_size = 1024 * 1024,
723 .total_sram_size = 160 * 1024,
733 .base_address = FLASH_BANK_BASE_S,
734 .controller_address = 0x400e0a00,
735 .flash_wait_states = 5,
737 .size_bytes = 1024 * 1024,
751 /*atsam4s16a - LQFP48/QFN48*/
753 .chipid_cidr = 0x288C0CE0,
754 .name = "at91sam4s16a",
755 .total_flash_size = 1024 * 1024,
756 .total_sram_size = 128 * 1024,
766 .base_address = FLASH_BANK_BASE_S,
767 .controller_address = 0x400e0a00,
768 .flash_wait_states = 5,
770 .size_bytes = 1024 * 1024,
784 /*atsam4s8c - LQFP100/BGA100*/
786 .chipid_cidr = 0x28AC0AE0,
787 .name = "at91sam4s8c",
788 .total_flash_size = 512 * 1024,
789 .total_sram_size = 128 * 1024,
799 .base_address = FLASH_BANK_BASE_S,
800 .controller_address = 0x400e0a00,
801 .flash_wait_states = 5,
803 .size_bytes = 512 * 1024,
817 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
819 .chipid_cidr = 0x289C0AE0,
820 .name = "at91sam4s8b",
821 .total_flash_size = 512 * 1024,
822 .total_sram_size = 128 * 1024,
832 .base_address = FLASH_BANK_BASE_S,
833 .controller_address = 0x400e0a00,
834 .flash_wait_states = 5,
836 .size_bytes = 512 * 1024,
850 /*atsam4s8a - LQFP48/BGA48*/
852 .chipid_cidr = 0x288C0AE0,
853 .name = "at91sam4s8a",
854 .total_flash_size = 512 * 1024,
855 .total_sram_size = 128 * 1024,
865 .base_address = FLASH_BANK_BASE_S,
866 .controller_address = 0x400e0a00,
867 .flash_wait_states = 5,
869 .size_bytes = 512 * 1024,
884 /*atsam4s4c - LQFP100/BGA100*/
886 .chipid_cidr = 0x28ab09e0,
887 .name = "at91sam4s4c",
888 .total_flash_size = 256 * 1024,
889 .total_sram_size = 64 * 1024,
899 .base_address = FLASH_BANK_BASE_S,
900 .controller_address = 0x400e0a00,
901 .flash_wait_states = 5,
903 .size_bytes = 256 * 1024,
918 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
920 .chipid_cidr = 0x289b09e0,
921 .name = "at91sam4s4b",
922 .total_flash_size = 256 * 1024,
923 .total_sram_size = 64 * 1024,
933 .base_address = FLASH_BANK_BASE_S,
934 .controller_address = 0x400e0a00,
935 .flash_wait_states = 5,
937 .size_bytes = 256 * 1024,
952 /*atsam4s4a - LQFP48/QFN48*/
954 .chipid_cidr = 0x288b09e0,
955 .name = "at91sam4s4a",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 64 * 1024,
967 .base_address = FLASH_BANK_BASE_S,
968 .controller_address = 0x400e0a00,
969 .flash_wait_states = 5,
971 .size_bytes = 256 * 1024,
986 /*atsam4s2c - LQFP100/BGA100*/
988 .chipid_cidr = 0x28ab07e0,
989 .name = "at91sam4s2c",
990 .total_flash_size = 128 * 1024,
991 .total_sram_size = 64 * 1024,
1001 .base_address = FLASH_BANK_BASE_S,
1002 .controller_address = 0x400e0a00,
1003 .flash_wait_states = 5,
1005 .size_bytes = 128 * 1024,
1007 .sector_size = 8192,
1020 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1022 .chipid_cidr = 0x289b07e0,
1023 .name = "at91sam4s2b",
1024 .total_flash_size = 128 * 1024,
1025 .total_sram_size = 64 * 1024,
1035 .base_address = FLASH_BANK_BASE_S,
1036 .controller_address = 0x400e0a00,
1037 .flash_wait_states = 5,
1039 .size_bytes = 128 * 1024,
1041 .sector_size = 8192,
1054 /*atsam4s2a - LQFP48/QFN48*/
1056 .chipid_cidr = 0x288b07e0,
1057 .name = "at91sam4s2a",
1058 .total_flash_size = 128 * 1024,
1059 .total_sram_size = 64 * 1024,
1069 .base_address = FLASH_BANK_BASE_S,
1070 .controller_address = 0x400e0a00,
1071 .flash_wait_states = 5,
1073 .size_bytes = 128 * 1024,
1075 .sector_size = 8192,
1088 /*at91sam4sd32c - LQFP100/BGA100*/
1090 .chipid_cidr = 0x29a70ee0,
1091 .name = "at91sam4sd32c",
1092 .total_flash_size = 2048 * 1024,
1093 .total_sram_size = 160 * 1024,
1104 .base_address = FLASH_BANK0_BASE_SD,
1105 .controller_address = 0x400e0a00,
1106 .flash_wait_states = 5,
1108 .size_bytes = 1024 * 1024,
1110 .sector_size = 8192,
1120 .base_address = FLASH_BANK1_BASE_2048K_SD,
1121 .controller_address = 0x400e0c00,
1122 .flash_wait_states = 5,
1124 .size_bytes = 1024 * 1024,
1126 .sector_size = 8192,
1132 /*at91sam4sd32b - LQFP64/BGA64*/
1134 .chipid_cidr = 0x29970ee0,
1135 .name = "at91sam4sd32b",
1136 .total_flash_size = 2048 * 1024,
1137 .total_sram_size = 160 * 1024,
1148 .base_address = FLASH_BANK0_BASE_SD,
1149 .controller_address = 0x400e0a00,
1150 .flash_wait_states = 5,
1152 .size_bytes = 1024 * 1024,
1154 .sector_size = 8192,
1164 .base_address = FLASH_BANK1_BASE_2048K_SD,
1165 .controller_address = 0x400e0c00,
1166 .flash_wait_states = 5,
1168 .size_bytes = 1024 * 1024,
1170 .sector_size = 8192,
1176 /*at91sam4sd16c - LQFP100/BGA100*/
1178 .chipid_cidr = 0x29a70ce0,
1179 .name = "at91sam4sd16c",
1180 .total_flash_size = 1024 * 1024,
1181 .total_sram_size = 160 * 1024,
1192 .base_address = FLASH_BANK0_BASE_SD,
1193 .controller_address = 0x400e0a00,
1194 .flash_wait_states = 5,
1196 .size_bytes = 512 * 1024,
1198 .sector_size = 8192,
1208 .base_address = FLASH_BANK1_BASE_1024K_SD,
1209 .controller_address = 0x400e0c00,
1210 .flash_wait_states = 5,
1212 .size_bytes = 512 * 1024,
1214 .sector_size = 8192,
1220 /*at91sam4sd16b - LQFP64/BGA64*/
1222 .chipid_cidr = 0x29970ce0,
1223 .name = "at91sam4sd16b",
1224 .total_flash_size = 1024 * 1024,
1225 .total_sram_size = 160 * 1024,
1236 .base_address = FLASH_BANK0_BASE_SD,
1237 .controller_address = 0x400e0a00,
1238 .flash_wait_states = 5,
1240 .size_bytes = 512 * 1024,
1242 .sector_size = 8192,
1252 .base_address = FLASH_BANK1_BASE_1024K_SD,
1253 .controller_address = 0x400e0c00,
1254 .flash_wait_states = 5,
1256 .size_bytes = 512 * 1024,
1258 .sector_size = 8192,
1266 .chipid_cidr = 0x28a70ce0,
1267 .name = "at91sam4sa16c",
1268 .total_flash_size = 1024 * 1024,
1269 .total_sram_size = 160 * 1024,
1280 .base_address = FLASH_BANK0_BASE_SD,
1281 .controller_address = 0x400e0a00,
1282 .flash_wait_states = 5,
1284 .size_bytes = 512 * 1024,
1286 .sector_size = 8192,
1296 .base_address = FLASH_BANK1_BASE_1024K_SD,
1297 .controller_address = 0x400e0c00,
1298 .flash_wait_states = 5,
1300 .size_bytes = 512 * 1024,
1302 .sector_size = 8192,
1310 .chipid_cidr = 0x247e0ae0,
1311 .name = "atsamg53n19",
1312 .total_flash_size = 512 * 1024,
1313 .total_sram_size = 96 * 1024,
1324 .base_address = FLASH_BANK_BASE_S,
1325 .controller_address = 0x400e0a00,
1326 .flash_wait_states = 5,
1328 .size_bytes = 512 * 1024,
1330 .sector_size = 8192,
1345 .chipid_cidr = 0x24470ae0,
1346 .name = "atsamg55g19",
1347 .total_flash_size = 512 * 1024,
1348 .total_sram_size = 160 * 1024,
1359 .base_address = FLASH_BANK_BASE_S,
1360 .controller_address = 0x400e0a00,
1361 .flash_wait_states = 5,
1363 .size_bytes = 512 * 1024,
1365 .sector_size = 8192,
1379 .chipid_cidr = 0x24570ae0,
1380 .name = "atsamg55j19",
1381 .total_flash_size = 512 * 1024,
1382 .total_sram_size = 160 * 1024,
1393 .base_address = FLASH_BANK_BASE_S,
1394 .controller_address = 0x400e0a00,
1395 .flash_wait_states = 5,
1397 .size_bytes = 512 * 1024,
1399 .sector_size = 8192,
1419 /***********************************************************************
1420 **********************************************************************
1421 **********************************************************************
1422 **********************************************************************
1423 **********************************************************************
1424 **********************************************************************/
1425 /* *ATMEL* style code - from the SAM4 driver code */
1428 * Get the current status of the EEFC and
1429 * the value of some status bits (LOCKE, PROGE).
1430 * @param pPrivate - info about the bank
1431 * @param v - result goes here
1433 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
1436 r = target_read_u32(pPrivate->pChip->target,
1437 pPrivate->controller_address + offset_EFC_FSR,
1439 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1441 ((unsigned int)((*v >> 2) & 1)),
1442 ((unsigned int)((*v >> 1) & 1)),
1443 ((unsigned int)((*v >> 0) & 1)));
1449 * Get the result of the last executed command.
1450 * @param pPrivate - info about the bank
1451 * @param v - result goes here
1453 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
1457 r = target_read_u32(pPrivate->pChip->target,
1458 pPrivate->controller_address + offset_EFC_FRR,
1462 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1466 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
1467 unsigned command, unsigned argument)
1476 /* Check command & argument */
1479 case AT91C_EFC_FCMD_WP:
1480 case AT91C_EFC_FCMD_WPL:
1481 case AT91C_EFC_FCMD_EWP:
1482 case AT91C_EFC_FCMD_EWPL:
1483 /* case AT91C_EFC_FCMD_EPL: */
1484 case AT91C_EFC_FCMD_EPA:
1485 case AT91C_EFC_FCMD_SLB:
1486 case AT91C_EFC_FCMD_CLB:
1487 n = (pPrivate->size_bytes / pPrivate->page_size);
1489 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1492 case AT91C_EFC_FCMD_SFB:
1493 case AT91C_EFC_FCMD_CFB:
1494 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1495 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1496 pPrivate->pChip->details.n_gpnvms);
1500 case AT91C_EFC_FCMD_GETD:
1501 case AT91C_EFC_FCMD_EA:
1502 case AT91C_EFC_FCMD_GLB:
1503 case AT91C_EFC_FCMD_GFB:
1504 case AT91C_EFC_FCMD_STUI:
1505 case AT91C_EFC_FCMD_SPUI:
1507 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1510 LOG_ERROR("Unknown command %d", command);
1514 if (command == AT91C_EFC_FCMD_SPUI) {
1515 /* this is a very special situation. */
1516 /* Situation (1) - error/retry - see below */
1517 /* And we are being called recursively */
1518 /* Situation (2) - normal, finished reading unique id */
1520 /* it should be "ready" */
1521 EFC_GetStatus(pPrivate, &v);
1523 /* then it is ready */
1527 /* we have done this before */
1528 /* the controller is not responding. */
1529 LOG_ERROR("flash controller(%d) is not ready! Error",
1530 pPrivate->bank_number);
1534 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1535 pPrivate->bank_number);
1536 /* we do that by issuing the *STOP* command */
1537 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1538 /* above is recursive, and further recursion is blocked by */
1539 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1545 v = (0x5A << 24) | (argument << 8) | command;
1546 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1547 r = target_write_u32(pPrivate->pBank->target,
1548 pPrivate->controller_address + offset_EFC_FCR, v);
1550 LOG_DEBUG("Error Write failed");
1555 * Performs the given command and wait until its completion (or an error).
1556 * @param pPrivate - info about the bank
1557 * @param command - Command to perform.
1558 * @param argument - Optional command argument.
1559 * @param status - put command status bits here
1561 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1569 int64_t ms_now, ms_end;
1575 r = EFC_StartCommand(pPrivate, command, argument);
1579 ms_end = 10000 + timeval_ms();
1582 r = EFC_GetStatus(pPrivate, &v);
1585 ms_now = timeval_ms();
1586 if (ms_now > ms_end) {
1588 LOG_ERROR("Command timeout");
1591 } while ((v & 1) == 0);
1595 *status = (v & 0x6);
1601 * Read the unique ID.
1602 * @param pPrivate - info about the bank
1603 * The unique ID is stored in the 'pPrivate' structure.
1605 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1611 pPrivate->pChip->cfg.unique_id[0] = 0;
1612 pPrivate->pChip->cfg.unique_id[1] = 0;
1613 pPrivate->pChip->cfg.unique_id[2] = 0;
1614 pPrivate->pChip->cfg.unique_id[3] = 0;
1617 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1621 for (x = 0; x < 4; x++) {
1622 r = target_read_u32(pPrivate->pChip->target,
1623 pPrivate->pBank->base + (x * 4),
1627 pPrivate->pChip->cfg.unique_id[x] = v;
1630 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1631 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1633 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1634 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1635 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1636 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1642 * Erases the entire flash.
1643 * @param pPrivate - the info about the bank.
1645 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1648 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1652 * Erases the entire flash.
1653 * @param pPrivate - the info about the bank.
1655 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1680 /* AT91C_EFC_FCMD_EPA
1681 * According to the datasheet FARG[15:2] defines the page from which
1682 * the erase will start.This page must be modulo 4, 8, 16 or 32
1683 * according to the number of pages to erase. FARG[1:0] defines the
1684 * number of pages to be erased. Previously (firstpage << 2) was used
1685 * to conform to this, seems it should not be shifted...
1687 return EFC_PerformCommand(pPrivate,
1688 /* send Erase Page */
1690 (firstPage) | erasePages,
1695 * Gets current GPNVM state.
1696 * @param pPrivate - info about the bank.
1697 * @param gpnvm - GPNVM bit index.
1698 * @param puthere - result stored here.
1700 /* ------------------------------------------------------------------------------ */
1701 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1707 if (pPrivate->bank_number != 0) {
1708 LOG_ERROR("GPNVM only works with Bank0");
1712 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1713 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1714 gpnvm, pPrivate->pChip->details.n_gpnvms);
1718 /* Get GPNVMs status */
1719 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1720 if (r != ERROR_OK) {
1721 LOG_ERROR("Failed");
1725 r = EFC_GetResult(pPrivate, &v);
1728 /* Check if GPNVM is set */
1729 /* get the bit and make it a 0/1 */
1730 *puthere = (v >> gpnvm) & 1;
1737 * Clears the selected GPNVM bit.
1738 * @param pPrivate info about the bank
1739 * @param gpnvm GPNVM index.
1740 * @returns 0 if successful; otherwise returns an error code.
1742 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1748 if (pPrivate->bank_number != 0) {
1749 LOG_ERROR("GPNVM only works with Bank0");
1753 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1754 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1755 gpnvm, pPrivate->pChip->details.n_gpnvms);
1759 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1760 if (r != ERROR_OK) {
1761 LOG_DEBUG("Failed: %d", r);
1764 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1765 LOG_DEBUG("End: %d", r);
1770 * Sets the selected GPNVM bit.
1771 * @param pPrivate info about the bank
1772 * @param gpnvm GPNVM index.
1774 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1779 if (pPrivate->bank_number != 0) {
1780 LOG_ERROR("GPNVM only works with Bank0");
1784 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1785 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1786 gpnvm, pPrivate->pChip->details.n_gpnvms);
1790 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1798 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1804 * Returns a bit field (at most 64) of locked regions within a page.
1805 * @param pPrivate info about the bank
1806 * @param v where to store locked bits
1808 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1812 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1813 if (r == ERROR_OK) {
1814 EFC_GetResult(pPrivate, v);
1815 EFC_GetResult(pPrivate, v);
1816 EFC_GetResult(pPrivate, v);
1817 r = EFC_GetResult(pPrivate, v);
1819 LOG_DEBUG("End: %d", r);
1824 * Unlocks all the regions in the given address range.
1825 * @param pPrivate info about the bank
1826 * @param start_sector first sector to unlock
1827 * @param end_sector last (inclusive) to unlock
1830 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1831 unsigned start_sector,
1832 unsigned end_sector)
1837 uint32_t pages_per_sector;
1839 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1841 /* Unlock all pages */
1842 while (start_sector <= end_sector) {
1843 pg = start_sector * pages_per_sector;
1845 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1856 * @param pPrivate - info about the bank
1857 * @param start_sector - first sector to lock
1858 * @param end_sector - last sector (inclusive) to lock
1860 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1861 unsigned start_sector,
1862 unsigned end_sector)
1866 uint32_t pages_per_sector;
1869 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1871 /* Lock all pages */
1872 while (start_sector <= end_sector) {
1873 pg = start_sector * pages_per_sector;
1875 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1883 /****** END SAM4 CODE ********/
1885 /* begin helpful debug code */
1886 /* print the fieldname, the field value, in dec & hex, and return field value */
1887 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1888 const char *regname,
1897 /* extract the field */
1899 v = v & ((1 << width)-1);
1908 /* show the basics */
1909 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1910 REG_NAME_WIDTH, regname,
1916 static const char _unknown[] = "unknown";
1917 static const char *const eproc_names[] = {
1918 "Cortex-M7", /* 0 */
1921 "Cortex-M3", /* 3 */
1923 "arm926ejs", /* 5 */
1924 "Cortex-A5", /* 6 */
1925 "Cortex-M4", /* 7 */
1936 #define nvpsize2 nvpsize /* these two tables are identical */
1937 static const char *const nvpsize[] = {
1940 "16K bytes", /* 2 */
1941 "32K bytes", /* 3 */
1943 "64K bytes", /* 5 */
1945 "128K bytes", /* 7 */
1946 "160K bytes", /* 8 */
1947 "256K bytes", /* 9 */
1948 "512K bytes", /* 10 */
1950 "1024K bytes", /* 12 */
1952 "2048K bytes", /* 14 */
1956 static const char *const sramsize[] = {
1957 "48K Bytes", /* 0 */
1961 "112K Bytes", /* 4 */
1963 "80K Bytes", /* 6 */
1964 "160K Bytes", /* 7 */
1966 "16K Bytes", /* 9 */
1967 "32K Bytes", /* 10 */
1968 "64K Bytes", /* 11 */
1969 "128K Bytes", /* 12 */
1970 "256K Bytes", /* 13 */
1971 "96K Bytes", /* 14 */
1972 "512K Bytes", /* 15 */
1976 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1977 { 0x19, "AT91SAM9xx Series" },
1978 { 0x29, "AT91SAM9XExx Series" },
1979 { 0x34, "AT91x34 Series" },
1980 { 0x37, "CAP7 Series" },
1981 { 0x39, "CAP9 Series" },
1982 { 0x3B, "CAP11 Series" },
1983 { 0x3C, "ATSAM4E" },
1984 { 0x40, "AT91x40 Series" },
1985 { 0x42, "AT91x42 Series" },
1986 { 0x43, "SAMG51 Series"
1988 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
1989 { 0x45, "SAMG55 Series (64-pin)" },
1990 { 0x47, "SAMG53 Series"
1992 { 0x55, "AT91x55 Series" },
1993 { 0x60, "AT91SAM7Axx Series" },
1994 { 0x61, "AT91SAM7AQxx Series" },
1995 { 0x63, "AT91x63 Series" },
1996 { 0x64, "SAM4CxxC (100-pin version)" },
1997 { 0x66, "SAM4CxxE (144-pin version)" },
1998 { 0x70, "AT91SAM7Sxx Series" },
1999 { 0x71, "AT91SAM7XCxx Series" },
2000 { 0x72, "AT91SAM7SExx Series" },
2001 { 0x73, "AT91SAM7Lxx Series" },
2002 { 0x75, "AT91SAM7Xxx Series" },
2003 { 0x76, "AT91SAM7SLxx Series" },
2004 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2005 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2006 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2007 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2008 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2009 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2010 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2011 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2012 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2013 { 0x92, "AT91x92 Series" },
2014 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2015 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2016 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2017 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2018 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2019 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2020 { 0xA5, "ATSAM5A" },
2021 { 0xF0, "AT75Cxx Series" },
2025 static const char *const nvptype[] = {
2027 "romless or onchip flash", /* 1 */
2028 "embedded flash memory",/* 2 */
2029 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2030 "sram emulating flash", /* 4 */
2036 static const char *_yes_or_no(uint32_t v)
2044 static const char *const _rc_freq[] = {
2045 "4 MHz", "8 MHz", "12 MHz", "reserved"
2048 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
2053 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2054 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2055 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2056 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2057 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2058 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2059 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2060 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2062 pChip->cfg.rc_freq = 0;
2066 pChip->cfg.rc_freq = 0;
2069 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2072 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2075 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2080 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2081 LOG_USER("(startup clks, time= %f uSecs)",
2082 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2083 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2084 LOG_USER("(mainosc source: %s)",
2085 v ? "external xtal" : "internal RC");
2087 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2088 LOG_USER("(clock failure enabled: %s)",
2092 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
2098 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2101 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2102 LOG_USER("%s", eproc_names[v]);
2104 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2105 LOG_USER("%s", nvpsize[v]);
2107 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2108 LOG_USER("%s", nvpsize2[v]);
2110 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2111 LOG_USER("%s", sramsize[v]);
2113 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2115 for (x = 0; archnames[x].name; x++) {
2116 if (v == archnames[x].value) {
2117 cp = archnames[x].name;
2124 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2125 LOG_USER("%s", nvptype[v]);
2127 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2128 LOG_USER("(exists: %s)", _yes_or_no(v));
2131 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
2135 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2136 LOG_USER("(main ready: %s)", _yes_or_no(v));
2138 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2140 v = (v * pChip->cfg.slow_freq) / 16;
2141 pChip->cfg.mainosc_freq = v;
2143 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2145 (uint32_t)(pChip->cfg.slow_freq / 1000),
2146 (uint32_t)(pChip->cfg.slow_freq % 1000));
2149 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
2151 uint32_t mula, diva;
2153 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2155 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2157 pChip->cfg.plla_freq = 0;
2159 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2161 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2162 else if (diva >= 1) {
2163 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2164 LOG_USER("\tPLLA Freq: %3.03f MHz",
2165 _tomhz(pChip->cfg.plla_freq));
2169 static void sam4_explain_mckr(struct sam4_chip *pChip)
2171 uint32_t css, pres, fin = 0;
2173 const char *cp = NULL;
2175 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2178 fin = pChip->cfg.slow_freq;
2182 fin = pChip->cfg.mainosc_freq;
2186 fin = pChip->cfg.plla_freq;
2190 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2191 fin = 480 * 1000 * 1000;
2195 cp = "upll (*ERROR* UPLL is disabled)";
2203 LOG_USER("%s (%3.03f Mhz)",
2206 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2207 switch (pres & 0x07) {
2210 cp = "selected clock";
2244 LOG_USER("(%s)", cp);
2246 /* sam4 has a *SINGLE* clock - */
2247 /* other at91 series parts have divisors for these. */
2248 pChip->cfg.cpu_freq = fin;
2249 pChip->cfg.mclk_freq = fin;
2250 pChip->cfg.fclk_freq = fin;
2251 LOG_USER("\t\tResult CPU Freq: %3.03f",
2256 static struct sam4_chip *target2sam4(struct target *pTarget)
2258 struct sam4_chip *pChip;
2260 if (pTarget == NULL)
2263 pChip = all_sam4_chips;
2265 if (pChip->target == pTarget)
2266 break; /* return below */
2268 pChip = pChip->next;
2274 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
2276 /* this function exists to help */
2277 /* keep funky offsetof() errors */
2278 /* and casting from causing bugs */
2280 /* By using prototypes - we can detect what would */
2281 /* be casting errors. */
2283 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2287 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2289 NAME), # NAME, FUNC }
2290 static const struct sam4_reg_list sam4_all_regs[] = {
2291 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2292 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2293 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2294 SAM4_ENTRY(CKGR_UCKR, NULL),
2295 SAM4_ENTRY(PMC_FSMR, NULL),
2296 SAM4_ENTRY(PMC_FSPR, NULL),
2297 SAM4_ENTRY(PMC_IMR, NULL),
2298 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2299 SAM4_ENTRY(PMC_PCK0, NULL),
2300 SAM4_ENTRY(PMC_PCK1, NULL),
2301 SAM4_ENTRY(PMC_PCK2, NULL),
2302 SAM4_ENTRY(PMC_PCSR, NULL),
2303 SAM4_ENTRY(PMC_SCSR, NULL),
2304 SAM4_ENTRY(PMC_SR, NULL),
2305 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2306 SAM4_ENTRY(CHIPID_EXID, NULL),
2307 /* TERMINATE THE LIST */
2312 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2314 return bank->driver_priv;
2318 * Given a pointer to where it goes in the structure,
2319 * determine the register name, address from the all registers table.
2321 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
2323 const struct sam4_reg_list *pReg;
2325 pReg = &(sam4_all_regs[0]);
2326 while (pReg->name) {
2327 uint32_t *pPossible;
2329 /* calculate where this one go.. */
2330 /* it is "possibly" this register. */
2332 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2334 /* well? Is it this register */
2335 if (pPossible == goes_here) {
2343 /* This is *TOTAL*PANIC* - we are totally screwed. */
2344 LOG_ERROR("INVALID SAM4 REGISTER");
2348 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
2350 const struct sam4_reg_list *pReg;
2353 pReg = sam4_GetReg(pChip, goes_here);
2357 r = target_read_u32(pChip->target, pReg->address, goes_here);
2358 if (r != ERROR_OK) {
2359 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2360 pReg->name, (unsigned)(pReg->address), r);
2365 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
2368 const struct sam4_reg_list *pReg;
2370 pReg = &(sam4_all_regs[0]);
2371 while (pReg->name) {
2372 r = sam4_ReadThisReg(pChip,
2373 sam4_get_reg_ptr(&(pChip->cfg), pReg));
2374 if (r != ERROR_OK) {
2375 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2376 pReg->name, ((unsigned)(pReg->address)), r);
2385 static int sam4_GetInfo(struct sam4_chip *pChip)
2387 const struct sam4_reg_list *pReg;
2390 pReg = &(sam4_all_regs[0]);
2391 while (pReg->name) {
2392 /* display all regs */
2393 LOG_DEBUG("Start: %s", pReg->name);
2394 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
2395 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2400 if (pReg->explain_func)
2401 (*(pReg->explain_func))(pChip);
2402 LOG_DEBUG("End: %s", pReg->name);
2405 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2406 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2407 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2408 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2409 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2411 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2412 pChip->cfg.unique_id[0],
2413 pChip->cfg.unique_id[1],
2414 pChip->cfg.unique_id[2],
2415 pChip->cfg.unique_id[3]);
2420 static int sam4_protect_check(struct flash_bank *bank)
2423 uint32_t v[4] = {0};
2425 struct sam4_bank_private *pPrivate;
2428 if (bank->target->state != TARGET_HALTED) {
2429 LOG_ERROR("Target not halted");
2430 return ERROR_TARGET_NOT_HALTED;
2433 pPrivate = get_sam4_bank_private(bank);
2435 LOG_ERROR("no private for this bank?");
2438 if (!(pPrivate->probed))
2439 return ERROR_FLASH_BANK_NOT_PROBED;
2441 r = FLASHD_GetLockBits(pPrivate, v);
2442 if (r != ERROR_OK) {
2443 LOG_DEBUG("Failed: %d", r);
2447 for (x = 0; x < pPrivate->nsectors; x++)
2448 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2453 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2455 struct sam4_chip *pChip;
2457 pChip = all_sam4_chips;
2459 /* is this an existing chip? */
2461 if (pChip->target == bank->target)
2463 pChip = pChip->next;
2467 /* this is a *NEW* chip */
2468 pChip = calloc(1, sizeof(struct sam4_chip));
2470 LOG_ERROR("NO RAM!");
2473 pChip->target = bank->target;
2474 /* insert at head */
2475 pChip->next = all_sam4_chips;
2476 all_sam4_chips = pChip;
2477 pChip->target = bank->target;
2478 /* assumption is this runs at 32khz */
2479 pChip->cfg.slow_freq = 32768;
2483 switch (bank->base) {
2485 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2486 "[at91sam4s series] )",
2487 ((unsigned int)(bank->base)),
2488 ((unsigned int)(FLASH_BANK_BASE_S)));
2492 /* at91sam4s series only has bank 0*/
2493 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2494 case FLASH_BANK_BASE_S:
2495 case FLASH_BANK_BASE_C:
2496 bank->driver_priv = &(pChip->details.bank[0]);
2497 bank->bank_number = 0;
2498 pChip->details.bank[0].pChip = pChip;
2499 pChip->details.bank[0].pBank = bank;
2502 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2503 case FLASH_BANK1_BASE_1024K_SD:
2504 case FLASH_BANK1_BASE_2048K_SD:
2505 case FLASH_BANK1_BASE_C32:
2506 bank->driver_priv = &(pChip->details.bank[1]);
2507 bank->bank_number = 1;
2508 pChip->details.bank[1].pChip = pChip;
2509 pChip->details.bank[1].pBank = bank;
2513 /* we initialize after probing. */
2518 * Remove all chips from the internal list without distingushing which one
2519 * is owned by this bank. This simplification works only for one shot
2520 * deallocation like current flash_free_all_banks()
2522 static void sam4_free_driver_priv(struct flash_bank *bank)
2524 struct sam4_chip *chip = all_sam4_chips;
2526 struct sam4_chip *next = chip->next;
2530 all_sam4_chips = NULL;
2533 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2535 const struct sam4_chip_details *pDetails;
2536 struct sam4_chip *pChip;
2537 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2541 pDetails = all_sam4_details;
2542 while (pDetails->name) {
2543 /* Compare cidr without version bits */
2544 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2549 if (pDetails->name == NULL) {
2550 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2551 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2552 /* Help the victim, print details about the chip */
2553 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2554 pPrivate->pChip->cfg.CHIPID_CIDR);
2555 sam4_explain_chipid_cidr(pPrivate->pChip);
2559 /* DANGER: THERE ARE DRAGONS HERE */
2561 /* get our pChip - it is going */
2562 /* to be over-written shortly */
2563 pChip = pPrivate->pChip;
2565 /* Note that, in reality: */
2567 /* pPrivate = &(pChip->details.bank[0]) */
2568 /* or pPrivate = &(pChip->details.bank[1]) */
2571 /* save the "bank" pointers */
2572 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2573 saved_banks[x] = pChip->details.bank[x].pBank;
2575 /* Overwrite the "details" structure. */
2576 memcpy(&(pPrivate->pChip->details),
2578 sizeof(pPrivate->pChip->details));
2580 /* now fix the ghosted pointers */
2581 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2582 pChip->details.bank[x].pChip = pChip;
2583 pChip->details.bank[x].pBank = saved_banks[x];
2586 /* update the *BANK*SIZE* */
2592 static int _sam4_probe(struct flash_bank *bank, int noise)
2596 struct sam4_bank_private *pPrivate;
2599 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2600 if (bank->target->state != TARGET_HALTED) {
2601 LOG_ERROR("Target not halted");
2602 return ERROR_TARGET_NOT_HALTED;
2605 pPrivate = get_sam4_bank_private(bank);
2607 LOG_ERROR("Invalid/unknown bank number");
2611 r = sam4_ReadAllRegs(pPrivate->pChip);
2616 if (pPrivate->pChip->probed)
2617 r = sam4_GetInfo(pPrivate->pChip);
2619 r = sam4_GetDetails(pPrivate);
2623 /* update the flash bank size */
2624 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2625 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2626 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2631 if (bank->sectors == NULL) {
2632 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2633 if (bank->sectors == NULL) {
2634 LOG_ERROR("No memory!");
2637 bank->num_sectors = pPrivate->nsectors;
2639 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2640 bank->sectors[x].size = pPrivate->sector_size;
2641 bank->sectors[x].offset = x * (pPrivate->sector_size);
2642 /* mark as unknown */
2643 bank->sectors[x].is_erased = -1;
2644 bank->sectors[x].is_protected = -1;
2648 pPrivate->probed = 1;
2650 r = sam4_protect_check(bank);
2654 LOG_DEBUG("Bank = %d, nbanks = %d",
2655 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2656 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2657 /* read unique id, */
2658 /* it appears to be associated with the *last* flash bank. */
2659 FLASHD_ReadUniqueID(pPrivate);
2665 static int sam4_probe(struct flash_bank *bank)
2667 return _sam4_probe(bank, 1);
2670 static int sam4_auto_probe(struct flash_bank *bank)
2672 return _sam4_probe(bank, 0);
2675 static int sam4_erase(struct flash_bank *bank, int first, int last)
2677 struct sam4_bank_private *pPrivate;
2681 /*16 pages equals 8KB - Same size as a lock region*/
2686 if (bank->target->state != TARGET_HALTED) {
2687 LOG_ERROR("Target not halted");
2688 return ERROR_TARGET_NOT_HALTED;
2691 r = sam4_auto_probe(bank);
2692 if (r != ERROR_OK) {
2693 LOG_DEBUG("Here,r=%d", r);
2697 pPrivate = get_sam4_bank_private(bank);
2698 if (!(pPrivate->probed))
2699 return ERROR_FLASH_BANK_NOT_PROBED;
2701 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2704 return FLASHD_EraseEntireBank(pPrivate);
2706 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2707 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
2708 for (i = first; i <= last; i++) {
2709 /*16 pages equals 8KB - Same size as a lock region*/
2710 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2711 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
2713 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
2715 if (status & (1 << 2)) {
2716 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
2719 if (status & (1 << 1)) {
2720 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
2728 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
2730 struct sam4_bank_private *pPrivate;
2734 if (bank->target->state != TARGET_HALTED) {
2735 LOG_ERROR("Target not halted");
2736 return ERROR_TARGET_NOT_HALTED;
2739 pPrivate = get_sam4_bank_private(bank);
2740 if (!(pPrivate->probed))
2741 return ERROR_FLASH_BANK_NOT_PROBED;
2744 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2746 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2747 LOG_DEBUG("End: r=%d", r);
2753 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2758 adr = pagenum * pPrivate->page_size;
2759 adr = adr + pPrivate->base_address;
2761 r = target_read_memory(pPrivate->pChip->target,
2763 4, /* THIS*MUST*BE* in 32bit values */
2764 pPrivate->page_size / 4,
2767 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2768 (unsigned int)(adr));
2772 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2776 uint32_t fmr; /* EEFC Flash Mode Register */
2779 adr = pagenum * pPrivate->page_size;
2780 adr = (adr + pPrivate->base_address);
2782 /* Get flash mode register value */
2783 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2785 LOG_DEBUG("Error Read failed: read flash mode register");
2787 /* Clear flash wait state field */
2790 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2791 fmr |= (pPrivate->flash_wait_states << 8);
2793 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2794 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2796 LOG_DEBUG("Error Write failed: set flash mode register");
2798 /* 1st sector 8kBytes - page 0 - 15*/
2799 /* 2nd sector 8kBytes - page 16 - 30*/
2800 /* 3rd sector 48kBytes - page 31 - 127*/
2801 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2802 r = target_write_memory(pPrivate->pChip->target,
2804 4, /* THIS*MUST*BE* in 32bit values */
2805 pPrivate->page_size / 4,
2807 if (r != ERROR_OK) {
2808 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2809 (unsigned int)(adr));
2813 r = EFC_PerformCommand(pPrivate,
2814 /* send Erase & Write Page */
2815 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2820 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2821 (unsigned int)(adr));
2822 if (status & (1 << 2)) {
2823 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2826 if (status & (1 << 1)) {
2827 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2833 static int sam4_write(struct flash_bank *bank,
2834 const uint8_t *buffer,
2842 unsigned page_offset;
2843 struct sam4_bank_private *pPrivate;
2844 uint8_t *pagebuffer;
2846 /* incase we bail further below, set this to null */
2849 /* ignore dumb requests */
2855 if (bank->target->state != TARGET_HALTED) {
2856 LOG_ERROR("Target not halted");
2857 r = ERROR_TARGET_NOT_HALTED;
2861 pPrivate = get_sam4_bank_private(bank);
2862 if (!(pPrivate->probed)) {
2863 r = ERROR_FLASH_BANK_NOT_PROBED;
2867 if ((offset + count) > pPrivate->size_bytes) {
2868 LOG_ERROR("Flash write error - past end of bank");
2869 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2870 (unsigned int)(offset),
2871 (unsigned int)(count),
2872 (unsigned int)(pPrivate->size_bytes));
2877 pagebuffer = malloc(pPrivate->page_size);
2879 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2884 /* what page do we start & end in? */
2885 page_cur = offset / pPrivate->page_size;
2886 page_end = (offset + count - 1) / pPrivate->page_size;
2888 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2889 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2891 /* Special case: all one page */
2894 /* (1) non-aligned start */
2895 /* (2) body pages */
2896 /* (3) non-aligned end. */
2898 /* Handle special case - all one page. */
2899 if (page_cur == page_end) {
2900 LOG_DEBUG("Special case, all in one page");
2901 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2905 page_offset = (offset & (pPrivate->page_size-1));
2906 memcpy(pagebuffer + page_offset,
2910 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2917 /* non-aligned start */
2918 page_offset = offset & (pPrivate->page_size - 1);
2920 LOG_DEBUG("Not-Aligned start");
2921 /* read the partial */
2922 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2926 /* over-write with new data */
2927 n = (pPrivate->page_size - page_offset);
2928 memcpy(pagebuffer + page_offset,
2932 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2942 /* By checking that offset is correct here, we also
2943 fix a clang warning */
2944 assert(offset % pPrivate->page_size == 0);
2946 /* intermediate large pages */
2947 /* also - the final *terminal* */
2948 /* if that terminal page is a full page */
2949 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2950 (int)page_cur, (int)page_end, (unsigned int)(count));
2952 while ((page_cur < page_end) &&
2953 (count >= pPrivate->page_size)) {
2954 r = sam4_page_write(pPrivate, page_cur, buffer);
2957 count -= pPrivate->page_size;
2958 buffer += pPrivate->page_size;
2962 /* terminal partial page? */
2964 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2965 /* we have a partial page */
2966 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2969 /* data goes at start */
2970 memcpy(pagebuffer, buffer, count);
2971 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2983 COMMAND_HANDLER(sam4_handle_info_command)
2985 struct sam4_chip *pChip;
2986 pChip = get_current_sam4(CMD_CTX);
2993 /* bank0 must exist before we can do anything */
2994 if (pChip->details.bank[0].pBank == NULL) {
2997 command_print(CMD_CTX,
2998 "Please define bank %d via command: flash bank %s ... ",
3000 at91sam4_flash.name);
3004 /* if bank 0 is not probed, then probe it */
3005 if (!(pChip->details.bank[0].probed)) {
3006 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3010 /* above guarantees the "chip details" structure is valid */
3011 /* and thus, bank private areas are valid */
3012 /* and we have a SAM4 chip, what a concept! */
3014 /* auto-probe other banks, 0 done above */
3015 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3016 /* skip banks not present */
3017 if (!(pChip->details.bank[x].present))
3020 if (pChip->details.bank[x].pBank == NULL)
3023 if (pChip->details.bank[x].probed)
3026 r = sam4_auto_probe(pChip->details.bank[x].pBank);
3031 r = sam4_GetInfo(pChip);
3032 if (r != ERROR_OK) {
3033 LOG_DEBUG("Sam4Info, Failed %d", r);
3040 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3044 struct sam4_chip *pChip;
3046 pChip = get_current_sam4(CMD_CTX);
3050 if (pChip->target->state != TARGET_HALTED) {
3051 LOG_ERROR("sam4 - target not halted");
3052 return ERROR_TARGET_NOT_HALTED;
3055 if (pChip->details.bank[0].pBank == NULL) {
3056 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3057 at91sam4_flash.name);
3060 if (!pChip->details.bank[0].probed) {
3061 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3068 return ERROR_COMMAND_SYNTAX_ERROR;
3077 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3081 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3087 if (0 == strcmp("show", CMD_ARGV[0])) {
3091 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3092 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3095 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
3099 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3100 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3101 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
3104 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
3105 return ERROR_COMMAND_SYNTAX_ERROR;
3110 command_print(CMD_CTX, "Missing GPNVM number");
3111 return ERROR_COMMAND_SYNTAX_ERROR;
3114 if (0 == strcmp("set", CMD_ARGV[0]))
3115 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3116 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3117 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3118 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3120 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3121 r = ERROR_COMMAND_SYNTAX_ERROR;
3126 COMMAND_HANDLER(sam4_handle_slowclk_command)
3128 struct sam4_chip *pChip;
3130 pChip = get_current_sam4(CMD_CTX);
3142 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3144 /* absurd slow clock of 200Khz? */
3145 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3146 return ERROR_COMMAND_SYNTAX_ERROR;
3148 pChip->cfg.slow_freq = v;
3153 command_print(CMD_CTX, "Too many parameters");
3154 return ERROR_COMMAND_SYNTAX_ERROR;
3157 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3158 (int)(pChip->cfg.slow_freq / 1000),
3159 (int)(pChip->cfg.slow_freq % 1000));
3163 static const struct command_registration at91sam4_exec_command_handlers[] = {
3166 .handler = sam4_handle_gpnvm_command,
3167 .mode = COMMAND_EXEC,
3168 .usage = "[('clr'|'set'|'show') bitnum]",
3169 .help = "Without arguments, shows all bits in the gpnvm "
3170 "register. Otherwise, clears, sets, or shows one "
3171 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3175 .handler = sam4_handle_info_command,
3176 .mode = COMMAND_EXEC,
3177 .help = "Print information about the current at91sam4 chip"
3178 "and its flash configuration.",
3182 .handler = sam4_handle_slowclk_command,
3183 .mode = COMMAND_EXEC,
3184 .usage = "[clock_hz]",
3185 .help = "Display or set the slowclock frequency "
3186 "(default 32768 Hz).",
3188 COMMAND_REGISTRATION_DONE
3190 static const struct command_registration at91sam4_command_handlers[] = {
3193 .mode = COMMAND_ANY,
3194 .help = "at91sam4 flash command group",
3196 .chain = at91sam4_exec_command_handlers,
3198 COMMAND_REGISTRATION_DONE
3201 struct flash_driver at91sam4_flash = {
3203 .commands = at91sam4_command_handlers,
3204 .flash_bank_command = sam4_flash_bank_command,
3205 .erase = sam4_erase,
3206 .protect = sam4_protect,
3207 .write = sam4_write,
3208 .read = default_flash_read,
3209 .probe = sam4_probe,
3210 .auto_probe = sam4_auto_probe,
3211 .erase_check = default_flash_blank_check,
3212 .protect_check = sam4_protect_check,
3213 .free_driver_priv = sam4_free_driver_priv,