1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include "helper/binarybuffer.h"
26 #include <target/cortex_m.h>
28 #define SAMD_NUM_PROT_BLOCKS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
39 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
41 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
42 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
43 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
44 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
45 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
46 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
47 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
49 #define SAMD_CMDEX_KEY 0xA5UL
50 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
52 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
53 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
54 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
55 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
56 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
57 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
58 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
59 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
60 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
61 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
62 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
63 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
66 #define SAMD_NVM_CTRLB_MANW 0x80
68 /* Known identifiers */
69 #define SAMD_PROCESSOR_M0 0x01
70 #define SAMD_FAMILY_D 0x00
71 #define SAMD_FAMILY_L 0x01
72 #define SAMD_FAMILY_C 0x02
73 #define SAMD_SERIES_20 0x00
74 #define SAMD_SERIES_21 0x01
75 #define SAMD_SERIES_22 0x02
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
78 #define SAMD_SERIES_09 0x04
80 /* Device ID macros */
81 #define SAMD_GET_PROCESSOR(id) (id >> 28)
82 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
83 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
84 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
93 /* Known SAMD09 parts. DID reset values missing in RM, see
94 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
95 static const struct samd_part samd09_parts[] = {
96 { 0x0, "SAMD09D14A", 16, 4 },
97 { 0x7, "SAMD09C13A", 8, 4 },
100 /* Known SAMD10 parts */
101 static const struct samd_part samd10_parts[] = {
102 { 0x0, "SAMD10D14AMU", 16, 4 },
103 { 0x1, "SAMD10D13AMU", 8, 4 },
104 { 0x2, "SAMD10D12AMU", 4, 4 },
105 { 0x3, "SAMD10D14ASU", 16, 4 },
106 { 0x4, "SAMD10D13ASU", 8, 4 },
107 { 0x5, "SAMD10D12ASU", 4, 4 },
108 { 0x6, "SAMD10C14A", 16, 4 },
109 { 0x7, "SAMD10C13A", 8, 4 },
110 { 0x8, "SAMD10C12A", 4, 4 },
113 /* Known SAMD11 parts */
114 static const struct samd_part samd11_parts[] = {
115 { 0x0, "SAMD11D14AMU", 16, 4 },
116 { 0x1, "SAMD11D13AMU", 8, 4 },
117 { 0x2, "SAMD11D12AMU", 4, 4 },
118 { 0x3, "SAMD11D14ASU", 16, 4 },
119 { 0x4, "SAMD11D13ASU", 8, 4 },
120 { 0x5, "SAMD11D12ASU", 4, 4 },
121 { 0x6, "SAMD11C14A", 16, 4 },
122 { 0x7, "SAMD11C13A", 8, 4 },
123 { 0x8, "SAMD11C12A", 4, 4 },
126 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
127 static const struct samd_part samd20_parts[] = {
128 { 0x0, "SAMD20J18A", 256, 32 },
129 { 0x1, "SAMD20J17A", 128, 16 },
130 { 0x2, "SAMD20J16A", 64, 8 },
131 { 0x3, "SAMD20J15A", 32, 4 },
132 { 0x4, "SAMD20J14A", 16, 2 },
133 { 0x5, "SAMD20G18A", 256, 32 },
134 { 0x6, "SAMD20G17A", 128, 16 },
135 { 0x7, "SAMD20G16A", 64, 8 },
136 { 0x8, "SAMD20G15A", 32, 4 },
137 { 0x9, "SAMD20G14A", 16, 2 },
138 { 0xA, "SAMD20E18A", 256, 32 },
139 { 0xB, "SAMD20E17A", 128, 16 },
140 { 0xC, "SAMD20E16A", 64, 8 },
141 { 0xD, "SAMD20E15A", 32, 4 },
142 { 0xE, "SAMD20E14A", 16, 2 },
145 /* Known SAMD21 parts. */
146 static const struct samd_part samd21_parts[] = {
147 { 0x0, "SAMD21J18A", 256, 32 },
148 { 0x1, "SAMD21J17A", 128, 16 },
149 { 0x2, "SAMD21J16A", 64, 8 },
150 { 0x3, "SAMD21J15A", 32, 4 },
151 { 0x4, "SAMD21J14A", 16, 2 },
152 { 0x5, "SAMD21G18A", 256, 32 },
153 { 0x6, "SAMD21G17A", 128, 16 },
154 { 0x7, "SAMD21G16A", 64, 8 },
155 { 0x8, "SAMD21G15A", 32, 4 },
156 { 0x9, "SAMD21G14A", 16, 2 },
157 { 0xA, "SAMD21E18A", 256, 32 },
158 { 0xB, "SAMD21E17A", 128, 16 },
159 { 0xC, "SAMD21E16A", 64, 8 },
160 { 0xD, "SAMD21E15A", 32, 4 },
161 { 0xE, "SAMD21E14A", 16, 2 },
163 /* SAMR21 parts have integrated SAMD21 with a radio */
164 { 0x19, "SAMR21G18A", 256, 32 },
165 { 0x1A, "SAMR21G17A", 128, 32 },
166 { 0x1B, "SAMR21G16A", 64, 32 },
167 { 0x1C, "SAMR21E18A", 256, 32 },
168 { 0x1D, "SAMR21E17A", 128, 32 },
169 { 0x1E, "SAMR21E16A", 64, 32 },
171 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
172 { 0x20, "SAMD21J16B", 64, 8 },
173 { 0x21, "SAMD21J15B", 32, 4 },
174 { 0x23, "SAMD21G16B", 64, 8 },
175 { 0x24, "SAMD21G15B", 32, 4 },
176 { 0x26, "SAMD21E16B", 64, 8 },
177 { 0x27, "SAMD21E15B", 32, 4 },
180 /* Known SAML21 parts. */
181 static const struct samd_part saml21_parts[] = {
182 { 0x00, "SAML21J18A", 256, 32 },
183 { 0x01, "SAML21J17A", 128, 16 },
184 { 0x02, "SAML21J16A", 64, 8 },
185 { 0x05, "SAML21G18A", 256, 32 },
186 { 0x06, "SAML21G17A", 128, 16 },
187 { 0x07, "SAML21G16A", 64, 8 },
188 { 0x0A, "SAML21E18A", 256, 32 },
189 { 0x0B, "SAML21E17A", 128, 16 },
190 { 0x0C, "SAML21E16A", 64, 8 },
191 { 0x0D, "SAML21E15A", 32, 4 },
192 { 0x0F, "SAML21J18B", 256, 32 },
193 { 0x10, "SAML21J17B", 128, 16 },
194 { 0x11, "SAML21J16B", 64, 8 },
195 { 0x14, "SAML21G18B", 256, 32 },
196 { 0x15, "SAML21G17B", 128, 16 },
197 { 0x16, "SAML21G16B", 64, 8 },
198 { 0x19, "SAML21E18B", 256, 32 },
199 { 0x1A, "SAML21E17B", 128, 16 },
200 { 0x1B, "SAML21E16B", 64, 8 },
201 { 0x1C, "SAML21E15B", 32, 4 },
203 /* SAMR30 parts have integrated SAML21 with a radio */
204 { 0x1E, "SAMR30G18A", 256, 32 },
205 { 0x1F, "SAMR30E18A", 256, 32 },
208 /* Known SAML22 parts. */
209 static const struct samd_part saml22_parts[] = {
210 { 0x00, "SAML22N18A", 256, 32 },
211 { 0x01, "SAML22N17A", 128, 16 },
212 { 0x02, "SAML22N16A", 64, 8 },
213 { 0x05, "SAML22J18A", 256, 32 },
214 { 0x06, "SAML22J17A", 128, 16 },
215 { 0x07, "SAML22J16A", 64, 8 },
216 { 0x0A, "SAML22G18A", 256, 32 },
217 { 0x0B, "SAML22G17A", 128, 16 },
218 { 0x0C, "SAML22G16A", 64, 8 },
221 /* Known SAMC20 parts. */
222 static const struct samd_part samc20_parts[] = {
223 { 0x00, "SAMC20J18A", 256, 32 },
224 { 0x01, "SAMC20J17A", 128, 16 },
225 { 0x02, "SAMC20J16A", 64, 8 },
226 { 0x03, "SAMC20J15A", 32, 4 },
227 { 0x05, "SAMC20G18A", 256, 32 },
228 { 0x06, "SAMC20G17A", 128, 16 },
229 { 0x07, "SAMC20G16A", 64, 8 },
230 { 0x08, "SAMC20G15A", 32, 4 },
231 { 0x0A, "SAMC20E18A", 256, 32 },
232 { 0x0B, "SAMC20E17A", 128, 16 },
233 { 0x0C, "SAMC20E16A", 64, 8 },
234 { 0x0D, "SAMC20E15A", 32, 4 },
237 /* Known SAMC21 parts. */
238 static const struct samd_part samc21_parts[] = {
239 { 0x00, "SAMC21J18A", 256, 32 },
240 { 0x01, "SAMC21J17A", 128, 16 },
241 { 0x02, "SAMC21J16A", 64, 8 },
242 { 0x03, "SAMC21J15A", 32, 4 },
243 { 0x05, "SAMC21G18A", 256, 32 },
244 { 0x06, "SAMC21G17A", 128, 16 },
245 { 0x07, "SAMC21G16A", 64, 8 },
246 { 0x08, "SAMC21G15A", 32, 4 },
247 { 0x0A, "SAMC21E18A", 256, 32 },
248 { 0x0B, "SAMC21E17A", 128, 16 },
249 { 0x0C, "SAMC21E16A", 64, 8 },
250 { 0x0D, "SAMC21E15A", 32, 4 },
253 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
254 * processor ID, family ID, and series ID are used to determine which exact
255 * family this is and then we can use the corresponding table. */
260 const struct samd_part *parts;
264 /* Known SAMD families */
265 static const struct samd_family samd_families[] = {
266 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
267 samd20_parts, ARRAY_SIZE(samd20_parts) },
268 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
269 samd21_parts, ARRAY_SIZE(samd21_parts) },
270 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
271 samd09_parts, ARRAY_SIZE(samd09_parts) },
272 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
273 samd10_parts, ARRAY_SIZE(samd10_parts) },
274 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
275 samd11_parts, ARRAY_SIZE(samd11_parts) },
276 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
277 saml21_parts, ARRAY_SIZE(saml21_parts) },
278 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
279 saml22_parts, ARRAY_SIZE(saml22_parts) },
280 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
281 samc20_parts, ARRAY_SIZE(samc20_parts) },
282 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
283 samc21_parts, ARRAY_SIZE(samc21_parts) },
293 struct target *target;
294 struct samd_info *next;
297 static struct samd_info *samd_chips;
301 static const struct samd_part *samd_find_part(uint32_t id)
303 uint8_t processor = SAMD_GET_PROCESSOR(id);
304 uint8_t family = SAMD_GET_FAMILY(id);
305 uint8_t series = SAMD_GET_SERIES(id);
306 uint8_t devsel = SAMD_GET_DEVSEL(id);
308 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
309 if (samd_families[i].processor == processor &&
310 samd_families[i].series == series &&
311 samd_families[i].family == family) {
312 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
313 if (samd_families[i].parts[j].id == devsel)
314 return &samd_families[i].parts[j];
322 static int samd_protect_check(struct flash_bank *bank)
327 res = target_read_u16(bank->target,
328 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
332 /* Lock bits are active-low */
333 for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
334 bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
339 static int samd_get_flash_page_info(struct target *target,
340 uint32_t *sizep, int *nump)
345 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
346 if (res == ERROR_OK) {
347 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
348 * so 0 is 8KB and 7 is 1024KB. */
350 *sizep = (8 << ((param >> 16) & 0x7));
351 /* The NVMP field (bits 15:0) indicates the total number of pages */
353 *nump = param & 0xFFFF;
355 LOG_ERROR("Couldn't read NVM Parameters register");
361 static int samd_probe(struct flash_bank *bank)
365 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
366 const struct samd_part *part;
371 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
372 if (res != ERROR_OK) {
373 LOG_ERROR("Couldn't read Device ID register");
377 part = samd_find_part(id);
379 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
383 bank->size = part->flash_kb * 1024;
385 res = samd_get_flash_page_info(bank->target, &chip->page_size,
387 if (res != ERROR_OK) {
388 LOG_ERROR("Couldn't determine Flash page size");
392 /* Sanity check: the total flash size in the DSU should match the page size
393 * multiplied by the number of pages. */
394 if (bank->size != chip->num_pages * chip->page_size) {
395 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
396 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
397 part->flash_kb, chip->num_pages, chip->page_size);
400 /* Erase granularity = 1 row = 4 pages */
401 chip->sector_size = chip->page_size * 4;
403 /* Allocate the sector table */
404 bank->num_sectors = chip->num_pages / 4;
405 bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
409 /* 16 protection blocks per device */
410 chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;
412 /* Allocate the table of protection blocks */
413 bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
414 bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
415 if (!bank->prot_blocks)
418 samd_protect_check(bank);
423 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
424 part->flash_kb, part->ram_kb);
429 static int samd_check_error(struct target *target)
434 ret = target_read_u16(target,
435 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
436 if (ret != ERROR_OK) {
437 LOG_ERROR("Can't read NVM status");
441 if ((status & 0x001C) == 0)
444 if (status & (1 << 4)) { /* NVME */
445 LOG_ERROR("SAMD: NVM Error");
446 ret = ERROR_FLASH_OPERATION_FAILED;
449 if (status & (1 << 3)) { /* LOCKE */
450 LOG_ERROR("SAMD: NVM lock error");
451 ret = ERROR_FLASH_PROTECTED;
454 if (status & (1 << 2)) { /* PROGE */
455 LOG_ERROR("SAMD: NVM programming error");
456 ret = ERROR_FLASH_OPER_UNSUPPORTED;
459 /* Clear the error conditions by writing a one to them */
460 ret2 = target_write_u16(target,
461 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
462 if (ret2 != ERROR_OK)
463 LOG_ERROR("Can't clear NVM error conditions");
468 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
472 if (target->state != TARGET_HALTED) {
473 LOG_ERROR("Target not halted");
474 return ERROR_TARGET_NOT_HALTED;
477 /* Issue the NVM command */
478 res = target_write_u16(target,
479 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
483 /* Check to see if the NVM command resulted in an error condition. */
484 return samd_check_error(target);
487 static int samd_erase_row(struct target *target, uint32_t address)
491 /* Set an address contained in the row to be erased */
492 res = target_write_u32(target,
493 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
495 /* Issue the Erase Row command to erase that row. */
497 res = samd_issue_nvmctrl_command(target,
498 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
500 if (res != ERROR_OK) {
501 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
508 static bool is_user_row_reserved_bit(uint8_t bit)
510 /* See Table 9-3 in the SAMD20 datasheet for more information. */
515 /* Voltage regulator internal configuration with default value of 0x70,
516 * may not be changed. */
518 /* 41 is voltage regulator internal configuration and must not be
519 * changed. 42 through 47 are reserved. */
529 /* Modify the contents of the User Row in Flash. These are described in Table
530 * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
531 * and contains a combination of "fuses" and calibration data in bits 24:17.
532 * We therefore try not to erase the row's contents unless we absolutely have
533 * to and we don't permit modifying reserved bits. */
534 static int samd_modify_user_row(struct target *target, uint32_t value,
535 uint8_t startb, uint8_t endb)
539 bool manual_wp = true;
541 if (is_user_row_reserved_bit(startb) || is_user_row_reserved_bit(endb)) {
542 LOG_ERROR("Can't modify bits in the requested range");
546 /* Check if we need to do manual page write commands */
547 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
549 manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
551 /* Retrieve the MCU's page size, in bytes. This is also the size of the
552 * entire User Row. */
554 res = samd_get_flash_page_info(target, &page_size, NULL);
555 if (res != ERROR_OK) {
556 LOG_ERROR("Couldn't determine Flash page size");
560 /* Make sure the size is sane before we allocate. */
561 assert(page_size > 0 && page_size <= SAMD_PAGE_SIZE_MAX);
563 /* Make sure we're within the single page that comprises the User Row. */
564 if (startb >= (page_size * 8) || endb >= (page_size * 8)) {
565 LOG_ERROR("Can't modify bits outside the User Row page range");
569 uint8_t *buf = malloc(page_size);
573 /* Read the user row (comprising one page) by words. */
574 res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
578 /* We will need to erase before writing if the new value needs a '1' in any
579 * position for which the current value had a '0'. Otherwise we can avoid
581 uint32_t cur = buf_get_u32(buf, startb, endb - startb + 1);
582 if ((~cur) & value) {
583 res = samd_erase_row(target, SAMD_USER_ROW);
584 if (res != ERROR_OK) {
585 LOG_ERROR("Couldn't erase user row");
591 buf_set_u32(buf, startb, endb - startb + 1, value);
593 /* Write the page buffer back out to the target. */
594 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
599 /* Trigger flash write */
600 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
602 res = samd_check_error(target);
611 static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
616 /* We can issue lock/unlock region commands with the target running but
617 * the settings won't persist unless we're able to modify the LOCK regions
618 * and that requires the target to be halted. */
619 if (bank->target->state != TARGET_HALTED) {
620 LOG_ERROR("Target not halted");
621 return ERROR_TARGET_NOT_HALTED;
624 for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
625 if (set != bank->prot_blocks[prot_block].is_protected) {
626 /* Load an address that is within this protection block (we use offset 0) */
627 res = target_write_u32(bank->target,
628 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
629 bank->prot_blocks[prot_block].offset >> 1);
633 /* Tell the controller to lock that block */
634 res = samd_issue_nvmctrl_command(bank->target,
635 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
641 /* We've now applied our changes, however they will be undone by the next
642 * reset unless we also apply them to the LOCK bits in the User Page. The
643 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
644 * corresponding to Sector 15. A '1' means unlocked and a '0' means
645 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
647 res = samd_modify_user_row(bank->target, set ? 0x0000 : 0xFFFF,
648 48 + first_prot_bl, 48 + last_prot_bl);
650 LOG_WARNING("SAMD: protect settings were not made persistent!");
655 samd_protect_check(bank);
660 static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
663 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
665 if (bank->target->state != TARGET_HALTED) {
666 LOG_ERROR("Target not halted");
668 return ERROR_TARGET_NOT_HALTED;
672 if (samd_probe(bank) != ERROR_OK)
673 return ERROR_FLASH_BANK_NOT_PROBED;
676 /* For each sector to be erased */
677 for (s = first_sect; s <= last_sect; s++) {
678 res = samd_erase_row(bank->target, bank->sectors[s].offset);
679 if (res != ERROR_OK) {
680 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
689 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
690 uint32_t offset, uint32_t count)
698 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
702 if (bank->target->state != TARGET_HALTED) {
703 LOG_ERROR("Target not halted");
704 return ERROR_TARGET_NOT_HALTED;
708 if (samd_probe(bank) != ERROR_OK)
709 return ERROR_FLASH_BANK_NOT_PROBED;
712 /* Check if we need to do manual page write commands */
713 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
718 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
723 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
724 if (res != ERROR_OK) {
725 LOG_ERROR("%s: %d", __func__, __LINE__);
730 nb = chip->page_size - offset % chip->page_size;
734 address = bank->base + offset;
735 pg_offset = offset % chip->page_size;
737 if (offset % 4 || (offset + nb) % 4) {
738 /* Either start or end of write is not word aligned */
740 pb = malloc(chip->page_size);
745 /* Set temporary page buffer to 0xff and overwrite the relevant part */
746 memset(pb, 0xff, chip->page_size);
747 memcpy(pb + pg_offset, buffer, nb);
749 /* Align start address to a word boundary */
750 address -= offset % 4;
751 pg_offset -= offset % 4;
752 assert(pg_offset % 4 == 0);
754 /* Extend length to whole words */
755 nw = (nb + offset % 4 + 3) / 4;
756 assert(pg_offset + 4 * nw <= chip->page_size);
758 /* Now we have original data extended by 0xff bytes
759 * to the nearest word boundary on both start and end */
760 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
764 assert(pg_offset + 4 * nw <= chip->page_size);
766 /* Word aligned data, use direct write from buffer */
767 res = target_write_memory(bank->target, address, 4, nw, buffer);
769 if (res != ERROR_OK) {
770 LOG_ERROR("%s: %d", __func__, __LINE__);
774 /* Devices with errata 13134 have automatic page write enabled by default
775 * For other devices issue a write page CMD to the NVM
776 * If the page has not been written up to the last word
777 * then issue CMD_WP always */
778 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
779 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
781 /* Access through AHB is stalled while flash is being programmed */
784 res = samd_check_error(bank->target);
787 if (res != ERROR_OK) {
788 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
792 /* We're done with the page contents */
805 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
807 struct samd_info *chip = samd_chips;
810 if (chip->target == bank->target)
816 /* Create a new chip */
817 chip = calloc(1, sizeof(*chip));
821 chip->target = bank->target;
822 chip->probed = false;
824 bank->driver_priv = chip;
826 /* Insert it into the chips list (at head) */
827 chip->next = samd_chips;
831 if (bank->base != SAMD_FLASH) {
832 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
833 "[at91samd series] )",
834 bank->base, SAMD_FLASH);
841 COMMAND_HANDLER(samd_handle_info_command)
846 COMMAND_HANDLER(samd_handle_chip_erase_command)
848 struct target *target = get_current_target(CMD_CTX);
849 int res = ERROR_FAIL;
852 /* Enable access to the DSU by disabling the write protect bit */
853 target_write_u32(target, SAMD_PAC1, (1<<1));
854 /* intentionally without error checking - not accessible on secured chip */
856 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
857 * perform the erase. */
858 res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
860 command_print(CMD_CTX, "chip erase started");
862 command_print(CMD_CTX, "write to DSU CTRL failed");
868 COMMAND_HANDLER(samd_handle_set_security_command)
871 struct target *target = get_current_target(CMD_CTX);
873 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
874 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
875 return ERROR_COMMAND_SYNTAX_ERROR;
879 if (target->state != TARGET_HALTED) {
880 LOG_ERROR("Target not halted");
881 return ERROR_TARGET_NOT_HALTED;
884 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
886 /* Check (and clear) error conditions */
888 command_print(CMD_CTX, "chip secured on next power-cycle");
890 command_print(CMD_CTX, "failed to secure chip");
896 COMMAND_HANDLER(samd_handle_eeprom_command)
899 struct target *target = get_current_target(CMD_CTX);
902 if (target->state != TARGET_HALTED) {
903 LOG_ERROR("Target not halted");
904 return ERROR_TARGET_NOT_HALTED;
908 int val = atoi(CMD_ARGV[0]);
914 /* Try to match size in bytes with corresponding size code */
915 for (code = 0; code <= 6; code++) {
916 if (val == (2 << (13 - code)))
921 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
922 "datasheet for a list valid sizes.");
923 return ERROR_COMMAND_SYNTAX_ERROR;
927 res = samd_modify_user_row(target, code, 4, 6);
930 res = target_read_u16(target, SAMD_USER_ROW, &val);
931 if (res == ERROR_OK) {
932 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
935 command_print(CMD_CTX, "EEPROM is disabled");
937 /* Otherwise, 6 is 256B, 0 is 16KB */
938 command_print(CMD_CTX, "EEPROM size is %u bytes",
948 COMMAND_HANDLER(samd_handle_bootloader_command)
951 struct target *target = get_current_target(CMD_CTX);
954 if (target->state != TARGET_HALTED) {
955 LOG_ERROR("Target not halted");
956 return ERROR_TARGET_NOT_HALTED;
959 /* Retrieve the MCU's page size, in bytes. */
961 res = samd_get_flash_page_info(target, &page_size, NULL);
962 if (res != ERROR_OK) {
963 LOG_ERROR("Couldn't determine Flash page size");
968 int val = atoi(CMD_ARGV[0]);
974 /* Try to match size in bytes with corresponding size code */
975 for (code = 0; code <= 6; code++) {
976 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
981 command_print(CMD_CTX, "Invalid bootloader size. Please "
982 "see datasheet for a list valid sizes.");
983 return ERROR_COMMAND_SYNTAX_ERROR;
988 res = samd_modify_user_row(target, code, 0, 2);
991 res = target_read_u16(target, SAMD_USER_ROW, &val);
992 if (res == ERROR_OK) {
993 uint32_t size = (val & 0x7); /* grab size code */
999 nb = (2 << (8 - size)) * page_size;
1001 /* There are 4 pages per row */
1002 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
1003 nb, (uint32_t)(nb / (page_size * 4)));
1013 COMMAND_HANDLER(samd_handle_reset_deassert)
1015 struct target *target = get_current_target(CMD_CTX);
1016 int retval = ERROR_OK;
1017 enum reset_types jtag_reset_config = jtag_get_reset_config();
1019 /* If the target has been unresponsive before, try to re-establish
1020 * communication now - CPU is held in reset by DSU, DAP is working */
1021 if (!target_was_examined(target))
1022 target_examine_one(target);
1023 target_poll(target);
1025 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1026 * so we just release reset held by DSU
1028 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1030 * After vectreset DSU release is not needed however makes no harm
1032 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1033 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1034 if (retval == ERROR_OK)
1035 retval = target_write_u32(target, DCB_DEMCR,
1036 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1037 /* do not return on error here, releasing DSU reset is more important */
1040 /* clear CPU Reset Phase Extension bit */
1041 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1042 if (retval2 != ERROR_OK)
1048 static const struct command_registration at91samd_exec_command_handlers[] = {
1050 .name = "dsu_reset_deassert",
1051 .handler = samd_handle_reset_deassert,
1052 .mode = COMMAND_EXEC,
1053 .help = "deasert internal reset held by DSU"
1057 .handler = samd_handle_info_command,
1058 .mode = COMMAND_EXEC,
1059 .help = "Print information about the current at91samd chip"
1060 "and its flash configuration.",
1063 .name = "chip-erase",
1064 .handler = samd_handle_chip_erase_command,
1065 .mode = COMMAND_EXEC,
1066 .help = "Erase the entire Flash by using the Chip"
1067 "Erase feature in the Device Service Unit (DSU).",
1070 .name = "set-security",
1071 .handler = samd_handle_set_security_command,
1072 .mode = COMMAND_EXEC,
1073 .help = "Secure the chip's Flash by setting the Security Bit."
1074 "This makes it impossible to read the Flash contents."
1075 "The only way to undo this is to issue the chip-erase"
1080 .usage = "[size_in_bytes]",
1081 .handler = samd_handle_eeprom_command,
1082 .mode = COMMAND_EXEC,
1083 .help = "Show or set the EEPROM size setting, stored in the User Row."
1084 "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
1085 "Changes are stored immediately but take affect after the MCU is"
1089 .name = "bootloader",
1090 .usage = "[size_in_bytes]",
1091 .handler = samd_handle_bootloader_command,
1092 .mode = COMMAND_EXEC,
1093 .help = "Show or set the bootloader size, stored in the User Row."
1094 "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
1095 "Changes are stored immediately but take affect after the MCU is"
1098 COMMAND_REGISTRATION_DONE
1101 static const struct command_registration at91samd_command_handlers[] = {
1104 .mode = COMMAND_ANY,
1105 .help = "at91samd flash command group",
1107 .chain = at91samd_exec_command_handlers,
1109 COMMAND_REGISTRATION_DONE
1112 struct flash_driver at91samd_flash = {
1114 .commands = at91samd_command_handlers,
1115 .flash_bank_command = samd_flash_bank_command,
1116 .erase = samd_erase,
1117 .protect = samd_protect,
1118 .write = samd_write,
1119 .read = default_flash_read,
1120 .probe = samd_probe,
1121 .auto_probe = samd_probe,
1122 .erase_check = default_flash_blank_check,
1123 .protect_check = samd_protect_check,