git.sur5r.net Git - openocd/blob - src/flash/nor/avrf.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Simon Qian                                      *
   3  *   SimonQian@SimonQian.com                                               *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "imp.h"
  25 #include "avrf.h"
  26 #include <target/avrt.h>
  27
  28
  29 /* AVR_JTAG_Instructions */
  30 #define AVR_JTAG_INS_LEN                                                        4
  31 // Public Instructions:
  32 #define AVR_JTAG_INS_EXTEST                                                     0x00
  33 #define AVR_JTAG_INS_IDCODE                                                     0x01
  34 #define AVR_JTAG_INS_SAMPLE_PRELOAD                                     0x02
  35 #define AVR_JTAG_INS_BYPASS                                                     0x0F
  36 // AVR Specified Public Instructions:
  37 #define AVR_JTAG_INS_AVR_RESET                                          0x0C
  38 #define AVR_JTAG_INS_PROG_ENABLE                                        0x04
  39 #define AVR_JTAG_INS_PROG_COMMANDS                                      0x05
  40 #define AVR_JTAG_INS_PROG_PAGELOAD                                      0x06
  41 #define AVR_JTAG_INS_PROG_PAGEREAD                                      0x07
  42
  43 // Data Registers:
  44 #define AVR_JTAG_REG_Bypass_Len                                         1
  45 #define AVR_JTAG_REG_DeviceID_Len                                       32
  46
  47 #define AVR_JTAG_REG_Reset_Len                                          1
  48 #define AVR_JTAG_REG_JTAGID_Len                                         32
  49 #define AVR_JTAG_REG_ProgrammingEnable_Len                      16
  50 #define AVR_JTAG_REG_ProgrammingCommand_Len                     15
  51 #define AVR_JTAG_REG_FlashDataByte_Len                          16
  52
  53 static struct avrf_type avft_chips_info[] =
  54 {
  55 /*      name, chip_id,  flash_page_size, flash_page_num,
  56  *                      eeprom_page_size, eeprom_page_num
  57  */
  58         {"atmega128",   0x9702, 256, 512, 8, 512},
  59         {"at90can128",  0x9781, 256, 512, 8, 512},
  60 };
  61
  62 /* avr program functions */
  63 static int avr_jtag_reset(struct avr_common *avr, uint32_t reset)
  64 {
  65         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
  66         avr_jtag_senddat(avr->jtag_info.tap, NULL, reset ,AVR_JTAG_REG_Reset_Len);
  67
  68         return ERROR_OK;
  69 }
  70
  71 static int avr_jtag_read_jtagid(struct avr_common *avr, uint32_t *id)
  72 {
  73         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
  74         avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
  75
  76         return ERROR_OK;
  77 }
  78
  79 static int avr_jtagprg_enterprogmode(struct avr_common *avr)
  80 {
  81         avr_jtag_reset(avr, 1);
  82
  83         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
  84         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
  85
  86         return ERROR_OK;
  87 }
  88
  89 static int avr_jtagprg_leaveprogmode(struct avr_common *avr)
  90 {
  91         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
  92         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
  93         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
  94
  95         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
  96         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
  97
  98         avr_jtag_reset(avr, 0);
  99
 100         return ERROR_OK;
 101 }
 102
 103 static int avr_jtagprg_chiperase(struct avr_common *avr)
 104 {
 105         uint32_t poll_value;
 106
 107         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
 108         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
 109         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
 110         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
 111         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
 112
 113         do {
 114                 poll_value = 0;
 115                 avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
 116                 if (ERROR_OK != mcu_execute_queue())
 117                 {
 118                         return ERROR_FAIL;
 119                 }
 120                 LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
 121         } while (!(poll_value & 0x0200));
 122
 123         return ERROR_OK;
 124 }
 125
 126 static int avr_jtagprg_writeflashpage(struct avr_common *avr, uint8_t *page_buf, uint32_t buf_size, uint32_t addr, uint32_t page_size)
 127 {
 128         uint32_t i, poll_value;
 129
 130         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
 131         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
 132
 133         // load addr high byte
 134         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 9) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
 135
 136         // load addr low byte
 137         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | ((addr >> 1) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
 138
 139         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
 140
 141         for (i = 0; i < page_size; i++)
 142         {
 143                 if (i < buf_size)
 144                 {
 145                         avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
 146                 }
 147                 else
 148                 {
 149                         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
 150                 }
 151         }
 152
 153         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
 154
 155         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
 156         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
 157         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
 158         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
 159
 160         do {
 161                 poll_value = 0;
 162                 avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
 163                 if (ERROR_OK != mcu_execute_queue())
 164                 {
 165                         return ERROR_FAIL;
 166                 }
 167                 LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
 168         } while (!(poll_value & 0x0200));
 169
 170         return ERROR_OK;
 171 }
 172
 173 FLASH_BANK_COMMAND_HANDLER(avrf_flash_bank_command)
 174 {
 175         struct avrf_flash_bank *avrf_info;
 176
 177         if (CMD_ARGC < 6)
 178         {
 179                 LOG_WARNING("incomplete flash_bank avr configuration");
 180                 return ERROR_FLASH_BANK_INVALID;
 181         }
 182
 183         avrf_info = malloc(sizeof(struct avrf_flash_bank));
 184         bank->driver_priv = avrf_info;
 185
 186         avrf_info->probed = 0;
 187
 188         return ERROR_OK;
 189 }
 190
 191 static int avrf_erase(struct flash_bank *bank, int first, int last)
 192 {
 193         struct target *target = bank->target;
 194         struct avr_common *avr = target->arch_info;
 195         int status;
 196
 197         LOG_DEBUG("%s", __FUNCTION__);
 198
 199         if (target->state != TARGET_HALTED)
 200         {
 201                 LOG_ERROR("Target not halted");
 202                 return ERROR_TARGET_NOT_HALTED;
 203         }
 204
 205         status = avr_jtagprg_enterprogmode(avr);
 206         if (status != ERROR_OK)
 207                 return status;
 208
 209         status = avr_jtagprg_chiperase(avr);
 210         if (status != ERROR_OK)
 211                 return status;
 212
 213         return avr_jtagprg_leaveprogmode(avr);
 214 }
 215
 216 static int avrf_protect(struct flash_bank *bank, int set, int first, int last)
 217 {
 218         LOG_INFO("%s", __FUNCTION__);
 219         return ERROR_OK;
 220 }
 221
 222 static int avrf_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
 223 {
 224         struct target *target = bank->target;
 225         struct avr_common *avr = target->arch_info;
 226         uint32_t cur_size, cur_buffer_size, page_size;
 227
 228         if (bank->target->state != TARGET_HALTED)
 229         {
 230                 LOG_ERROR("Target not halted");
 231                 return ERROR_TARGET_NOT_HALTED;
 232         }
 233
 234         page_size = bank->sectors[0].size;
 235         if ((offset % page_size) != 0)
 236         {
 237                 LOG_WARNING("offset 0x%" PRIx32 " breaks required %" PRIu32 "-byte alignment", offset, page_size);
 238                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 239         }
 240
 241         LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
 242         LOG_DEBUG("count is %" PRId32 "", count);
 243
 244         if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
 245         {
 246                 return ERROR_FAIL;
 247         }
 248
 249         cur_size = 0;
 250         while (count > 0)
 251         {
 252                 if (count > page_size)
 253                 {
 254                         cur_buffer_size = page_size;
 255                 }
 256                 else
 257                 {
 258                         cur_buffer_size = count;
 259                 }
 260                 avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
 261                 count -= cur_buffer_size;
 262                 cur_size += cur_buffer_size;
 263
 264                 keep_alive();
 265         }
 266
 267         return avr_jtagprg_leaveprogmode(avr);
 268 }
 269
 270 #define EXTRACT_MFG(X)  (((X) & 0xffe) >> 1)
 271 #define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
 272 #define EXTRACT_VER(X)  (((X) & 0xf0000000) >> 28)
 273 static int avrf_probe(struct flash_bank *bank)
 274 {
 275         struct target *target = bank->target;
 276         struct avrf_flash_bank *avrf_info = bank->driver_priv;
 277         struct avr_common *avr = target->arch_info;
 278         struct avrf_type *avr_info = NULL;
 279         int i;
 280         uint32_t device_id;
 281
 282         if (bank->target->state != TARGET_HALTED)
 283         {
 284                 LOG_ERROR("Target not halted");
 285                 return ERROR_TARGET_NOT_HALTED;
 286         }
 287
 288         avrf_info->probed = 0;
 289
 290         avr_jtag_read_jtagid(avr, &device_id);
 291         if (ERROR_OK != mcu_execute_queue())
 292         {
 293                 return ERROR_FAIL;
 294         }
 295
 296         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 297         if (EXTRACT_MFG(device_id) != 0x1F)
 298         {
 299                 LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
 300         }
 301
 302         for (i = 0; i < (int)ARRAY_SIZE(avft_chips_info); i++)
 303         {
 304                 if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
 305                 {
 306                         avr_info = &avft_chips_info[i];
 307                         LOG_INFO("target device is %s", avr_info->name);
 308                         break;
 309                 }
 310         }
 311
 312         if (avr_info != NULL)
 313         {
 314                 if (bank->sectors)
 315                 {
 316                         free(bank->sectors);
 317                         bank->sectors = NULL;
 318                 }
 319
 320                 // chip found
 321                 bank->base = 0x00000000;
 322                 bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
 323                 bank->num_sectors = avr_info->flash_page_num;
 324                 bank->sectors = malloc(sizeof(struct flash_sector) * avr_info->flash_page_num);
 325
 326                 for (i = 0; i < avr_info->flash_page_num; i++)
 327                 {
 328                         bank->sectors[i].offset = i * avr_info->flash_page_size;
 329                         bank->sectors[i].size = avr_info->flash_page_size;
 330                         bank->sectors[i].is_erased = -1;
 331                         bank->sectors[i].is_protected = 1;
 332                 }
 333
 334                 avrf_info->probed = 1;
 335                 return ERROR_OK;
 336         }
 337         else
 338         {
 339                 // chip not supported
 340                 LOG_ERROR("0x%" PRIx32 " is not support for avr", EXTRACT_PART(device_id));
 341
 342                 avrf_info->probed = 1;
 343                 return ERROR_FAIL;
 344         }
 345 }
 346
 347 static int avrf_auto_probe(struct flash_bank *bank)
 348 {
 349         struct avrf_flash_bank *avrf_info = bank->driver_priv;
 350         if (avrf_info->probed)
 351                 return ERROR_OK;
 352         return avrf_probe(bank);
 353 }
 354
 355 static int avrf_protect_check(struct flash_bank *bank)
 356 {
 357         LOG_INFO("%s", __FUNCTION__);
 358         return ERROR_OK;
 359 }
 360
 361 static int avrf_info(struct flash_bank *bank, char *buf, int buf_size)
 362 {
 363         struct target *target = bank->target;
 364         struct avr_common *avr = target->arch_info;
 365         struct avrf_type *avr_info = NULL;
 366         int i;
 367         uint32_t device_id;
 368
 369         if (bank->target->state != TARGET_HALTED)
 370         {
 371                 LOG_ERROR("Target not halted");
 372                 return ERROR_TARGET_NOT_HALTED;
 373         }
 374
 375         avr_jtag_read_jtagid(avr, &device_id);
 376         if (ERROR_OK != mcu_execute_queue())
 377         {
 378                 return ERROR_FAIL;
 379         }
 380
 381         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 382         if (EXTRACT_MFG(device_id) != 0x1F)
 383         {
 384                 LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
 385         }
 386
 387         for (i = 0; i < (int)ARRAY_SIZE(avft_chips_info); i++)
 388         {
 389                 if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
 390                 {
 391                         avr_info = &avft_chips_info[i];
 392                         LOG_INFO("target device is %s", avr_info->name);
 393
 394                         break;
 395                 }
 396         }
 397
 398         if (avr_info != NULL)
 399         {
 400                 // chip found
 401                 snprintf(buf, buf_size, "%s - Rev: 0x%" PRIx32 "", avr_info->name, EXTRACT_VER(device_id));
 402                 return ERROR_OK;
 403         }
 404         else
 405         {
 406                 // chip not supported
 407                 snprintf(buf, buf_size, "Cannot identify target as a avr\n");
 408                 return ERROR_FLASH_OPERATION_FAILED;
 409         }
 410 }
 411
 412 static int avrf_mass_erase(struct flash_bank *bank)
 413 {
 414         struct target *target = bank->target;
 415         struct avr_common *avr = target->arch_info;
 416
 417         if (target->state != TARGET_HALTED)
 418         {
 419                 LOG_ERROR("Target not halted");
 420                 return ERROR_TARGET_NOT_HALTED;
 421         }
 422
 423         if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
 424                 || (ERROR_OK != avr_jtagprg_chiperase(avr))
 425                 || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
 426         {
 427                 return ERROR_FAIL;
 428         }
 429
 430         return ERROR_OK;
 431 }
 432
 433 COMMAND_HANDLER(avrf_handle_mass_erase_command)
 434 {
 435         int i;
 436
 437         if (CMD_ARGC < 1)
 438         {
 439                 command_print(CMD_CTX, "avr mass_erase <bank>");
 440                 return ERROR_OK;
 441         }
 442
 443         struct flash_bank *bank;
 444         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 445         if (ERROR_OK != retval)
 446                 return retval;
 447
 448         if (avrf_mass_erase(bank) == ERROR_OK)
 449         {
 450                 /* set all sectors as erased */
 451                 for (i = 0; i < bank->num_sectors; i++)
 452                 {
 453                         bank->sectors[i].is_erased = 1;
 454                 }
 455
 456                 command_print(CMD_CTX, "avr mass erase complete");
 457         }
 458         else
 459         {
 460                 command_print(CMD_CTX, "avr mass erase failed");
 461         }
 462
 463         LOG_DEBUG("%s", __FUNCTION__);
 464         return ERROR_OK;
 465 }
 466
 467 static const struct command_registration avrf_exec_command_handlers[] = {
 468         {
 469                 .name = "mass_erase",
 470                 .handler = avrf_handle_mass_erase_command,
 471                 .mode = COMMAND_EXEC,
 472                 .help = "erase entire device",
 473         },
 474         COMMAND_REGISTRATION_DONE
 475 };
 476 static const struct command_registration avrf_command_handlers[] = {
 477         {
 478                 .name = "avrf",
 479                 .mode = COMMAND_ANY,
 480                 .help = "AVR flash command group",
 481                 .chain = avrf_exec_command_handlers,
 482         },
 483         COMMAND_REGISTRATION_DONE
 484 };
 485
 486 struct flash_driver avr_flash = {
 487         .name = "avr",
 488         .commands = avrf_command_handlers,
 489         .flash_bank_command = avrf_flash_bank_command,
 490         .erase = avrf_erase,
 491         .protect = avrf_protect,
 492         .write = avrf_write,
 493         .read = default_flash_read,
 494         .probe = avrf_probe,
 495         .auto_probe = avrf_auto_probe,
 496         .erase_check = default_flash_mem_blank_check,
 497         .protect_check = avrf_protect_check,
 498         .info = avrf_info,
 499 };