git.sur5r.net Git - openocd/blob - src/flash/nor/kinetis.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Mathias Kuester                                 *
   3  *   kesmtp@freenet.de                                                     *
   4  *                                                                         *
   5  *   Copyright (C) 2011 sleep(5) ltd                                       *
   6  *   tomas@sleepfive.com                                                   *
   7  *                                                                         *
   8  *   Copyright (C) 2012 by Christopher D. Kilgour                          *
   9  *   techie at whiterocker.com                                             *
  10  *                                                                         *
  11  *   Copyright (C) 2013 Nemui Trinomius                                    *
  12  *   nemuisan_kawausogasuki@live.jp                                        *
  13  *                                                                         *
  14  *   Copyright (C) 2015 Tomas Vanek                                        *
  15  *   vanekt@fbl.cz                                                         *
  16  *                                                                         *
  17  *   This program is free software; you can redistribute it and/or modify  *
  18  *   it under the terms of the GNU General Public License as published by  *
  19  *   the Free Software Foundation; either version 2 of the License, or     *
  20  *   (at your option) any later version.                                   *
  21  *                                                                         *
  22  *   This program is distributed in the hope that it will be useful,       *
  23  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  24  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  25  *   GNU General Public License for more details.                          *
  26  *                                                                         *
  27  *   You should have received a copy of the GNU General Public License     *
  28  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  29  ***************************************************************************/
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include "jtag/interface.h"
  36 #include "imp.h"
  37 #include <helper/binarybuffer.h>
  38 #include <helper/time_support.h>
  39 #include <target/target_type.h>
  40 #include <target/algorithm.h>
  41 #include <target/armv7m.h>
  42 #include <target/cortex_m.h>
  43
  44 /*
  45  * Implementation Notes
  46  *
  47  * The persistent memories in the Kinetis chip families K10 through
  48  * K70 are all manipulated with the Flash Memory Module.  Some
  49  * variants call this module the FTFE, others call it the FTFL.  To
  50  * indicate that both are considered here, we use FTFX.
  51  *
  52  * Within the module, according to the chip variant, the persistent
  53  * memory is divided into what Freescale terms Program Flash, FlexNVM,
  54  * and FlexRAM.  All chip variants have Program Flash.  Some chip
  55  * variants also have FlexNVM and FlexRAM, which always appear
  56  * together.
  57  *
  58  * A given Kinetis chip may have 1, 2 or 4 blocks of flash.  Here we map
  59  * each block to a separate bank.  Each block size varies by chip and
  60  * may be determined by the read-only SIM_FCFG1 register.  The sector
  61  * size within each bank/block varies by chip, and may be 1, 2 or 4k.
  62  * The sector size may be different for flash and FlexNVM.
  63  *
  64  * The first half of the flash (1 or 2 blocks) is always Program Flash
  65  * and always starts at address 0x00000000.  The "PFLSH" flag, bit 23
  66  * of the read-only SIM_FCFG2 register, determines whether the second
  67  * half of the flash is also Program Flash or FlexNVM+FlexRAM.  When
  68  * PFLSH is set, the second from the first half.  When PFLSH is clear,
  69  * the second half of flash is FlexNVM and always starts at address
  70  * 0x10000000.  FlexRAM, which is also present when PFLSH is clear,
  71  * always starts at address 0x14000000.
  72  *
  73  * The Flash Memory Module provides a register set where flash
  74  * commands are loaded to perform flash operations like erase and
  75  * program.  Different commands are available depending on whether
  76  * Program Flash or FlexNVM/FlexRAM is being manipulated.  Although
  77  * the commands used are quite consistent between flash blocks, the
  78  * parameters they accept differ according to the flash sector size.
  79  *
  80  */
  81
  82 /* Addressess */
  83 #define FCF_ADDRESS     0x00000400
  84 #define FCF_FPROT       0x8
  85 #define FCF_FSEC        0xc
  86 #define FCF_FOPT        0xd
  87 #define FCF_FDPROT      0xf
  88 #define FCF_SIZE        0x10
  89
  90 #define FLEXRAM         0x14000000
  91
  92 #define MSCM_OCMDR0     0x40001400
  93 #define FMC_PFB01CR     0x4001f004
  94 #define FTFx_FSTAT      0x40020000
  95 #define FTFx_FCNFG      0x40020001
  96 #define FTFx_FCCOB3     0x40020004
  97 #define FTFx_FPROT3     0x40020010
  98 #define FTFx_FDPROT     0x40020017
  99 #define SIM_BASE        0x40047000
 100 #define SIM_BASE_KL28   0x40074000
 101 #define SIM_COPC        0x40048100
 102         /* SIM_COPC does not exist on devices with changed SIM_BASE */
 103 #define WDOG_BASE       0x40052000
 104 #define WDOG32_KE1X     0x40052000
 105 #define WDOG32_KL28     0x40076000
 106 #define SMC_PMCTRL      0x4007E001
 107 #define SMC_PMSTAT      0x4007E003
 108 #define SMC32_PMCTRL    0x4007E00C
 109 #define SMC32_PMSTAT    0x4007E014
 110 #define MCM_PLACR       0xF000300C
 111
 112 /* Offsets */
 113 #define SIM_SOPT1_OFFSET    0x0000
 114 #define SIM_SDID_OFFSET     0x1024
 115 #define SIM_FCFG1_OFFSET    0x104c
 116 #define SIM_FCFG2_OFFSET    0x1050
 117
 118 #define WDOG_STCTRLH_OFFSET      0
 119 #define WDOG32_CS_OFFSET         0
 120
 121 /* Values */
 122 #define PM_STAT_RUN             0x01
 123 #define PM_STAT_VLPR            0x04
 124 #define PM_CTRL_RUNM_RUN        0x00
 125
 126 /* Commands */
 127 #define FTFx_CMD_BLOCKSTAT  0x00
 128 #define FTFx_CMD_SECTSTAT   0x01
 129 #define FTFx_CMD_LWORDPROG  0x06
 130 #define FTFx_CMD_SECTERASE  0x09
 131 #define FTFx_CMD_SECTWRITE  0x0b
 132 #define FTFx_CMD_MASSERASE  0x44
 133 #define FTFx_CMD_PGMPART    0x80
 134 #define FTFx_CMD_SETFLEXRAM 0x81
 135
 136 /* The older Kinetis K series uses the following SDID layout :
 137  * Bit 31-16 : 0
 138  * Bit 15-12 : REVID
 139  * Bit 11-7  : DIEID
 140  * Bit 6-4   : FAMID
 141  * Bit 3-0   : PINID
 142  *
 143  * The newer Kinetis series uses the following SDID layout :
 144  * Bit 31-28 : FAMID
 145  * Bit 27-24 : SUBFAMID
 146  * Bit 23-20 : SERIESID
 147  * Bit 19-16 : SRAMSIZE
 148  * Bit 15-12 : REVID
 149  * Bit 6-4   : Reserved (0)
 150  * Bit 3-0   : PINID
 151  *
 152  * We assume that if bits 31-16 are 0 then it's an older
 153  * K-series MCU.
 154  */
 155
 156 #define KINETIS_SOPT1_RAMSIZE_MASK  0x0000F000
 157 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
 158
 159 #define KINETIS_SDID_K_SERIES_MASK  0x0000FFFF
 160
 161 #define KINETIS_SDID_DIEID_MASK 0x00000F80
 162
 163 #define KINETIS_SDID_DIEID_K22FN128     0x00000680 /* smaller pflash with FTFA */
 164 #define KINETIS_SDID_DIEID_K22FN256     0x00000A80
 165 #define KINETIS_SDID_DIEID_K22FN512     0x00000E80
 166 #define KINETIS_SDID_DIEID_K24FN256     0x00000700
 167
 168 #define KINETIS_SDID_DIEID_K24FN1M      0x00000300 /* Detect Errata 7534 */
 169
 170 /* We can't rely solely on the FAMID field to determine the MCU
 171  * type since some FAMID values identify multiple MCUs with
 172  * different flash sector sizes (K20 and K22 for instance).
 173  * Therefore we combine it with the DIEID bits which may possibly
 174  * break if Freescale bumps the DIEID for a particular MCU. */
 175 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
 176 #define KINETIS_K_SDID_K10_M50   0x00000000
 177 #define KINETIS_K_SDID_K10_M72   0x00000080
 178 #define KINETIS_K_SDID_K10_M100  0x00000100
 179 #define KINETIS_K_SDID_K10_M120  0x00000180
 180 #define KINETIS_K_SDID_K11               0x00000220
 181 #define KINETIS_K_SDID_K12               0x00000200
 182 #define KINETIS_K_SDID_K20_M50   0x00000010
 183 #define KINETIS_K_SDID_K20_M72   0x00000090
 184 #define KINETIS_K_SDID_K20_M100  0x00000110
 185 #define KINETIS_K_SDID_K20_M120  0x00000190
 186 #define KINETIS_K_SDID_K21_M50   0x00000230
 187 #define KINETIS_K_SDID_K21_M120  0x00000330
 188 #define KINETIS_K_SDID_K22_M50   0x00000210
 189 #define KINETIS_K_SDID_K22_M120  0x00000310
 190 #define KINETIS_K_SDID_K30_M72   0x000000A0
 191 #define KINETIS_K_SDID_K30_M100  0x00000120
 192 #define KINETIS_K_SDID_K40_M72   0x000000B0
 193 #define KINETIS_K_SDID_K40_M100  0x00000130
 194 #define KINETIS_K_SDID_K50_M72   0x000000E0
 195 #define KINETIS_K_SDID_K51_M72   0x000000F0
 196 #define KINETIS_K_SDID_K53               0x00000170
 197 #define KINETIS_K_SDID_K60_M100  0x00000140
 198 #define KINETIS_K_SDID_K60_M150  0x000001C0
 199 #define KINETIS_K_SDID_K70_M150  0x000001D0
 200
 201 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
 202 #define KINETIS_SDID_SERIESID_K   0x00000000
 203 #define KINETIS_SDID_SERIESID_KL   0x00100000
 204 #define KINETIS_SDID_SERIESID_KE   0x00200000
 205 #define KINETIS_SDID_SERIESID_KW   0x00500000
 206 #define KINETIS_SDID_SERIESID_KV   0x00600000
 207
 208 #define KINETIS_SDID_SUBFAMID_SHIFT 24
 209 #define KINETIS_SDID_SUBFAMID_MASK  0x0F000000
 210 #define KINETIS_SDID_SUBFAMID_KX0   0x00000000
 211 #define KINETIS_SDID_SUBFAMID_KX1   0x01000000
 212 #define KINETIS_SDID_SUBFAMID_KX2   0x02000000
 213 #define KINETIS_SDID_SUBFAMID_KX3   0x03000000
 214 #define KINETIS_SDID_SUBFAMID_KX4   0x04000000
 215 #define KINETIS_SDID_SUBFAMID_KX5   0x05000000
 216 #define KINETIS_SDID_SUBFAMID_KX6   0x06000000
 217 #define KINETIS_SDID_SUBFAMID_KX7   0x07000000
 218 #define KINETIS_SDID_SUBFAMID_KX8   0x08000000
 219
 220 #define KINETIS_SDID_FAMILYID_SHIFT 28
 221 #define KINETIS_SDID_FAMILYID_MASK  0xF0000000
 222 #define KINETIS_SDID_FAMILYID_K0X   0x00000000
 223 #define KINETIS_SDID_FAMILYID_K1X   0x10000000
 224 #define KINETIS_SDID_FAMILYID_K2X   0x20000000
 225 #define KINETIS_SDID_FAMILYID_K3X   0x30000000
 226 #define KINETIS_SDID_FAMILYID_K4X   0x40000000
 227 #define KINETIS_SDID_FAMILYID_K5X   0x50000000
 228 #define KINETIS_SDID_FAMILYID_K6X   0x60000000
 229 #define KINETIS_SDID_FAMILYID_K7X   0x70000000
 230 #define KINETIS_SDID_FAMILYID_K8X   0x80000000
 231 #define KINETIS_SDID_FAMILYID_KL8X  0x90000000
 232
 233 /* The field originally named DIEID has new name/meaning on KE1x */
 234 #define KINETIS_SDID_PROJECTID_MASK  KINETIS_SDID_DIEID_MASK
 235 #define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
 236 #define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
 237
 238 struct kinetis_flash_bank {
 239         struct kinetis_chip *k_chip;
 240         bool probed;
 241         unsigned bank_number;           /* bank number in particular chip */
 242         struct flash_bank *bank;
 243
 244         uint32_t sector_size;
 245         uint32_t protection_size;
 246         uint32_t prog_base;             /* base address for FTFx operations */
 247                                         /* usually same as bank->base for pflash, differs for FlexNVM */
 248         uint32_t protection_block;      /* number of first protection block in this bank */
 249
 250         enum {
 251                 FC_AUTO = 0,
 252                 FC_PFLASH,
 253                 FC_FLEX_NVM,
 254                 FC_FLEX_RAM,
 255         } flash_class;
 256 };
 257
 258 #define KINETIS_MAX_BANKS 4u
 259
 260 struct kinetis_chip {
 261         struct target *target;
 262         bool probed;
 263
 264         uint32_t sim_sdid;
 265         uint32_t sim_fcfg1;
 266         uint32_t sim_fcfg2;
 267         uint32_t fcfg2_maxaddr0_shifted;
 268         uint32_t fcfg2_maxaddr1_shifted;
 269
 270         unsigned num_pflash_blocks, num_nvm_blocks;
 271         unsigned pflash_sector_size, nvm_sector_size;
 272         unsigned max_flash_prog_size;
 273
 274         uint32_t pflash_base;
 275         uint32_t pflash_size;
 276         uint32_t nvm_base;
 277         uint32_t nvm_size;              /* whole FlexNVM */
 278         uint32_t dflash_size;           /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
 279
 280         uint32_t progr_accel_ram;
 281         uint32_t sim_base;
 282
 283         enum {
 284                 FS_PROGRAM_SECTOR = 1,
 285                 FS_PROGRAM_LONGWORD = 2,
 286                 FS_PROGRAM_PHRASE = 4,          /* Unsupported */
 287
 288                 FS_NO_CMD_BLOCKSTAT = 0x40,
 289                 FS_WIDTH_256BIT = 0x80,
 290                 FS_ECC = 0x100,
 291         } flash_support;
 292
 293         enum {
 294                 KINETIS_CACHE_NONE,
 295                 KINETIS_CACHE_K,        /* invalidate using FMC->PFB0CR/PFB01CR */
 296                 KINETIS_CACHE_L,        /* invalidate using MCM->PLACR */
 297                 KINETIS_CACHE_MSCM,     /* devices like KE1xF, invalidate MSCM->OCMDR0 */
 298         } cache_type;
 299
 300         enum {
 301                 KINETIS_WDOG_NONE,
 302                 KINETIS_WDOG_K,
 303                 KINETIS_WDOG_COP,
 304                 KINETIS_WDOG32_KE1X,
 305                 KINETIS_WDOG32_KL28,
 306         } watchdog_type;
 307
 308         enum {
 309                 KINETIS_SMC,
 310                 KINETIS_SMC32,
 311         } sysmodectrlr_type;
 312
 313         char name[40];
 314
 315         unsigned num_banks;
 316         struct kinetis_flash_bank banks[KINETIS_MAX_BANKS];
 317 };
 318
 319 struct kinetis_type {
 320         uint32_t sdid;
 321         char *name;
 322 };
 323
 324 static const struct kinetis_type kinetis_types_old[] = {
 325         { KINETIS_K_SDID_K10_M50,  "MK10D%s5" },
 326         { KINETIS_K_SDID_K10_M72,  "MK10D%s7" },
 327         { KINETIS_K_SDID_K10_M100, "MK10D%s10" },
 328         { KINETIS_K_SDID_K10_M120, "MK10F%s12" },
 329         { KINETIS_K_SDID_K11,      "MK11D%s5" },
 330         { KINETIS_K_SDID_K12,      "MK12D%s5" },
 331
 332         { KINETIS_K_SDID_K20_M50,  "MK20D%s5" },
 333         { KINETIS_K_SDID_K20_M72,  "MK20D%s7" },
 334         { KINETIS_K_SDID_K20_M100, "MK20D%s10" },
 335         { KINETIS_K_SDID_K20_M120, "MK20F%s12" },
 336         { KINETIS_K_SDID_K21_M50,  "MK21D%s5" },
 337         { KINETIS_K_SDID_K21_M120, "MK21F%s12" },
 338         { KINETIS_K_SDID_K22_M50,  "MK22D%s5" },
 339         { KINETIS_K_SDID_K22_M120, "MK22F%s12" },
 340
 341         { KINETIS_K_SDID_K30_M72,  "MK30D%s7" },
 342         { KINETIS_K_SDID_K30_M100, "MK30D%s10" },
 343
 344         { KINETIS_K_SDID_K40_M72,  "MK40D%s7" },
 345         { KINETIS_K_SDID_K40_M100, "MK40D%s10" },
 346
 347         { KINETIS_K_SDID_K50_M72,  "MK50D%s7" },
 348         { KINETIS_K_SDID_K51_M72,  "MK51D%s7" },
 349         { KINETIS_K_SDID_K53,      "MK53D%s10" },
 350
 351         { KINETIS_K_SDID_K60_M100, "MK60D%s10" },
 352         { KINETIS_K_SDID_K60_M150, "MK60F%s15" },
 353
 354         { KINETIS_K_SDID_K70_M150, "MK70F%s15" },
 355 };
 356
 357
 358 #define MDM_AP                  1
 359
 360 #define MDM_REG_STAT            0x00
 361 #define MDM_REG_CTRL            0x04
 362 #define MDM_REG_ID              0xfc
 363
 364 #define MDM_STAT_FMEACK         (1<<0)
 365 #define MDM_STAT_FREADY         (1<<1)
 366 #define MDM_STAT_SYSSEC         (1<<2)
 367 #define MDM_STAT_SYSRES         (1<<3)
 368 #define MDM_STAT_FMEEN          (1<<5)
 369 #define MDM_STAT_BACKDOOREN     (1<<6)
 370 #define MDM_STAT_LPEN           (1<<7)
 371 #define MDM_STAT_VLPEN          (1<<8)
 372 #define MDM_STAT_LLSMODEXIT     (1<<9)
 373 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 374 #define MDM_STAT_CORE_HALTED    (1<<16)
 375 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 376 #define MDM_STAT_CORESLEEPING   (1<<18)
 377
 378 #define MDM_CTRL_FMEIP          (1<<0)
 379 #define MDM_CTRL_DBG_DIS        (1<<1)
 380 #define MDM_CTRL_DBG_REQ        (1<<2)
 381 #define MDM_CTRL_SYS_RES_REQ    (1<<3)
 382 #define MDM_CTRL_CORE_HOLD_RES  (1<<4)
 383 #define MDM_CTRL_VLLSX_DBG_REQ  (1<<5)
 384 #define MDM_CTRL_VLLSX_DBG_ACK  (1<<6)
 385 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
 386
 387 #define MDM_ACCESS_TIMEOUT      500 /* msec */
 388
 389
 390 static bool allow_fcf_writes;
 391 static uint8_t fcf_fopt = 0xff;
 392 static bool fcf_fopt_configured;
 393 static bool create_banks;
 394
 395
 396 struct flash_driver kinetis_flash;
 397 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
 398                         uint32_t offset, uint32_t count);
 399 static int kinetis_probe_chip(struct kinetis_chip *k_chip);
 400 static int kinetis_auto_probe(struct flash_bank *bank);
 401
 402
 403 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
 404 {
 405         int retval;
 406         LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
 407
 408         retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
 409         if (retval != ERROR_OK) {
 410                 LOG_DEBUG("MDM: failed to queue a write request");
 411                 return retval;
 412         }
 413
 414         retval = dap_run(dap);
 415         if (retval != ERROR_OK) {
 416                 LOG_DEBUG("MDM: dap_run failed");
 417                 return retval;
 418         }
 419
 420
 421         return ERROR_OK;
 422 }
 423
 424 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
 425 {
 426         int retval;
 427
 428         retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
 429         if (retval != ERROR_OK) {
 430                 LOG_DEBUG("MDM: failed to queue a read request");
 431                 return retval;
 432         }
 433
 434         retval = dap_run(dap);
 435         if (retval != ERROR_OK) {
 436                 LOG_DEBUG("MDM: dap_run failed");
 437                 return retval;
 438         }
 439
 440         LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
 441         return ERROR_OK;
 442 }
 443
 444 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg,
 445                         uint32_t mask, uint32_t value, uint32_t timeout_ms)
 446 {
 447         uint32_t val;
 448         int retval;
 449         int64_t ms_timeout = timeval_ms() + timeout_ms;
 450
 451         do {
 452                 retval = kinetis_mdm_read_register(dap, reg, &val);
 453                 if (retval != ERROR_OK || (val & mask) == value)
 454                         return retval;
 455
 456                 alive_sleep(1);
 457         } while (timeval_ms() < ms_timeout);
 458
 459         LOG_DEBUG("MDM: polling timed out");
 460         return ERROR_FAIL;
 461 }
 462
 463 /*
 464  * This command can be used to break a watchdog reset loop when
 465  * connecting to an unsecured target. Unlike other commands, halt will
 466  * automatically retry as it does not know how far into the boot process
 467  * it is when the command is called.
 468  */
 469 COMMAND_HANDLER(kinetis_mdm_halt)
 470 {
 471         struct target *target = get_current_target(CMD_CTX);
 472         struct cortex_m_common *cortex_m = target_to_cm(target);
 473         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 474         int retval;
 475         int tries = 0;
 476         uint32_t stat;
 477         int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
 478
 479         if (!dap) {
 480                 LOG_ERROR("Cannot perform halt with a high-level adapter");
 481                 return ERROR_FAIL;
 482         }
 483
 484         while (true) {
 485                 tries++;
 486
 487                 kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_CORE_HOLD_RES);
 488
 489                 alive_sleep(1);
 490
 491                 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
 492                 if (retval != ERROR_OK) {
 493                         LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
 494                         continue;
 495                 }
 496
 497                 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
 498                  * reset with flash ready and without security
 499                  */
 500                 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSSEC | MDM_STAT_SYSRES))
 501                                 == (MDM_STAT_FREADY | MDM_STAT_SYSRES))
 502                         break;
 503
 504                 if (timeval_ms() >= ms_timeout) {
 505                         LOG_ERROR("MDM: halt timed out");
 506                         return ERROR_FAIL;
 507                 }
 508         }
 509
 510         LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
 511
 512         target_poll(target);
 513         /* enable polling in case kinetis_check_flash_security_status disabled it */
 514         jtag_poll_set_enabled(true);
 515
 516         alive_sleep(100);
 517
 518         target->reset_halt = true;
 519         target->type->assert_reset(target);
 520
 521         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 522         if (retval != ERROR_OK) {
 523                 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
 524                 return retval;
 525         }
 526
 527         target->type->deassert_reset(target);
 528
 529         return ERROR_OK;
 530 }
 531
 532 COMMAND_HANDLER(kinetis_mdm_reset)
 533 {
 534         struct target *target = get_current_target(CMD_CTX);
 535         struct cortex_m_common *cortex_m = target_to_cm(target);
 536         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 537         int retval;
 538
 539         if (!dap) {
 540                 LOG_ERROR("Cannot perform reset with a high-level adapter");
 541                 return ERROR_FAIL;
 542         }
 543
 544         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
 545         if (retval != ERROR_OK) {
 546                 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
 547                 return retval;
 548         }
 549
 550         retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT, MDM_STAT_SYSRES, 0, 500);
 551         if (retval != ERROR_OK) {
 552                 LOG_ERROR("MDM: failed to assert reset");
 553                 return retval;
 554         }
 555
 556         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 557         if (retval != ERROR_OK) {
 558                 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
 559                 return retval;
 560         }
 561
 562         return ERROR_OK;
 563 }
 564
 565 /*
 566  * This function implements the procedure to mass erase the flash via
 567  * SWD/JTAG on Kinetis K and L series of devices as it is described in
 568  * AN4835 "Production Flash Programming Best Practices for Kinetis K-
 569  * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
 570  * the core remains halted after this function completes as suggested
 571  * by the application note.
 572  */
 573 COMMAND_HANDLER(kinetis_mdm_mass_erase)
 574 {
 575         struct target *target = get_current_target(CMD_CTX);
 576         struct cortex_m_common *cortex_m = target_to_cm(target);
 577         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 578
 579         if (!dap) {
 580                 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
 581                 return ERROR_FAIL;
 582         }
 583
 584         int retval;
 585
 586         /*
 587          * ... Power on the processor, or if power has already been
 588          * applied, assert the RESET pin to reset the processor. For
 589          * devices that do not have a RESET pin, write the System
 590          * Reset Request bit in the MDM-AP control register after
 591          * establishing communication...
 592          */
 593
 594         /* assert SRST if configured */
 595         bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
 596         if (has_srst)
 597                 adapter_assert_reset();
 598
 599         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
 600         if (retval != ERROR_OK && !has_srst) {
 601                 LOG_ERROR("MDM: failed to assert reset");
 602                 goto deassert_reset_and_exit;
 603         }
 604
 605         /*
 606          * ... Read the MDM-AP status register repeatedly and wait for
 607          * stable conditions suitable for mass erase:
 608          * - mass erase is enabled
 609          * - flash is ready
 610          * - reset is finished
 611          *
 612          * Mass erase is started as soon as all conditions are met in 32
 613          * subsequent status reads.
 614          *
 615          * In case of not stable conditions (RESET/WDOG loop in secured device)
 616          * the user is asked for manual pressing of RESET button
 617          * as a last resort.
 618          */
 619         int cnt_mass_erase_disabled = 0;
 620         int cnt_ready = 0;
 621         int64_t ms_start = timeval_ms();
 622         bool man_reset_requested = false;
 623
 624         do {
 625                 uint32_t stat = 0;
 626                 int64_t ms_elapsed = timeval_ms() - ms_start;
 627
 628                 if (!man_reset_requested && ms_elapsed > 100) {
 629                         LOG_INFO("MDM: Press RESET button now if possible.");
 630                         man_reset_requested = true;
 631                 }
 632
 633                 if (ms_elapsed > 3000) {
 634                         LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
 635                         LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
 636                         LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
 637                         goto deassert_reset_and_exit;
 638                 }
 639                 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
 640                 if (retval != ERROR_OK) {
 641                         cnt_ready = 0;
 642                         continue;
 643                 }
 644
 645                 if (!(stat & MDM_STAT_FMEEN)) {
 646                         cnt_ready = 0;
 647                         cnt_mass_erase_disabled++;
 648                         if (cnt_mass_erase_disabled > 10) {
 649                                 LOG_ERROR("MDM: mass erase is disabled");
 650                                 goto deassert_reset_and_exit;
 651                         }
 652                         continue;
 653                 }
 654
 655                 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
 656                         cnt_ready++;
 657                 else
 658                         cnt_ready = 0;
 659
 660         } while (cnt_ready < 32);
 661
 662         /*
 663          * ... Write the MDM-AP control register to set the Flash Mass
 664          * Erase in Progress bit. This will start the mass erase
 665          * process...
 666          */
 667         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ | MDM_CTRL_FMEIP);
 668         if (retval != ERROR_OK) {
 669                 LOG_ERROR("MDM: failed to start mass erase");
 670                 goto deassert_reset_and_exit;
 671         }
 672
 673         /*
 674          * ... Read the MDM-AP control register until the Flash Mass
 675          * Erase in Progress bit clears...
 676          * Data sheed defines erase time <3.6 sec/512kB flash block.
 677          * The biggest device has 4 pflash blocks => timeout 16 sec.
 678          */
 679         retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
 680         if (retval != ERROR_OK) {
 681                 LOG_ERROR("MDM: mass erase timeout");
 682                 goto deassert_reset_and_exit;
 683         }
 684
 685         target_poll(target);
 686         /* enable polling in case kinetis_check_flash_security_status disabled it */
 687         jtag_poll_set_enabled(true);
 688
 689         alive_sleep(100);
 690
 691         target->reset_halt = true;
 692         target->type->assert_reset(target);
 693
 694         /*
 695          * ... Negate the RESET signal or clear the System Reset Request
 696          * bit in the MDM-AP control register.
 697          */
 698         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 699         if (retval != ERROR_OK)
 700                 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
 701
 702         target->type->deassert_reset(target);
 703
 704         return retval;
 705
 706 deassert_reset_and_exit:
 707         kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 708         if (has_srst)
 709                 adapter_deassert_reset();
 710         return retval;
 711 }
 712
 713 static const uint32_t kinetis_known_mdm_ids[] = {
 714         0x001C0000,     /* Kinetis-K Series */
 715         0x001C0020,     /* Kinetis-L/M/V/E Series */
 716         0x001C0030,     /* Kinetis with a Cortex-M7, in time of writing KV58 */
 717 };
 718
 719 /*
 720  * This function implements the procedure to connect to
 721  * SWD/JTAG on Kinetis K and L series of devices as it is described in
 722  * AN4835 "Production Flash Programming Best Practices for Kinetis K-
 723  * and L-series MCUs" Section 4.1.1
 724  */
 725 COMMAND_HANDLER(kinetis_check_flash_security_status)
 726 {
 727         struct target *target = get_current_target(CMD_CTX);
 728         struct cortex_m_common *cortex_m = target_to_cm(target);
 729         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 730
 731         if (!dap) {
 732                 LOG_WARNING("Cannot check flash security status with a high-level adapter");
 733                 return ERROR_OK;
 734         }
 735
 736         if (!dap->ops)
 737                 return ERROR_OK;        /* too early to check, in JTAG mode ops may not be initialised */
 738
 739         uint32_t val;
 740         int retval;
 741
 742         /*
 743          * ... The MDM-AP ID register can be read to verify that the
 744          * connection is working correctly...
 745          */
 746         retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
 747         if (retval != ERROR_OK) {
 748                 LOG_ERROR("MDM: failed to read ID register");
 749                 return ERROR_OK;
 750         }
 751
 752         if (val == 0)
 753                 return ERROR_OK;        /* dap not yet initialised */
 754
 755         bool found = false;
 756         for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
 757                 if (val == kinetis_known_mdm_ids[i]) {
 758                         found = true;
 759                         break;
 760                 }
 761         }
 762
 763         if (!found)
 764                 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
 765
 766         /*
 767          * ... Read the System Security bit to determine if security is enabled.
 768          * If System Security = 0, then proceed. If System Security = 1, then
 769          * communication with the internals of the processor, including the
 770          * flash, will not be possible without issuing a mass erase command or
 771          * unsecuring the part through other means (backdoor key unlock)...
 772          */
 773         retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
 774         if (retval != ERROR_OK) {
 775                 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
 776                 return ERROR_OK;
 777         }
 778
 779         /*
 780          * System Security bit is also active for short time during reset.
 781          * If a MCU has blank flash and runs in RESET/WDOG loop,
 782          * System Security bit is active most of time!
 783          * We should observe Flash Ready bit and read status several times
 784          * to avoid false detection of secured MCU
 785          */
 786         int secured_score = 0, flash_not_ready_score = 0;
 787
 788         if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
 789                 uint32_t stats[32];
 790                 int i;
 791
 792                 for (i = 0; i < 32; i++) {
 793                         stats[i] = MDM_STAT_FREADY;
 794                         dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
 795                 }
 796                 retval = dap_run(dap);
 797                 if (retval != ERROR_OK) {
 798                         LOG_DEBUG("MDM: dap_run failed when validating secured state");
 799                         return ERROR_OK;
 800                 }
 801                 for (i = 0; i < 32; i++) {
 802                         if (stats[i] & MDM_STAT_SYSSEC)
 803                                 secured_score++;
 804                         if (!(stats[i] & MDM_STAT_FREADY))
 805                                 flash_not_ready_score++;
 806                 }
 807         }
 808
 809         if (flash_not_ready_score <= 8 && secured_score > 24) {
 810                 jtag_poll_set_enabled(false);
 811
 812                 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
 813                 LOG_WARNING("****                                                          ****");
 814                 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that,  ****");
 815                 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD    ****");
 816                 LOG_WARNING("**** interface will NOT work. In order to restore its         ****");
 817                 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase'      ****");
 818                 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD.        ****");
 819                 LOG_WARNING("****                                                          ****");
 820                 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
 821
 822         } else if (flash_not_ready_score > 24) {
 823                 jtag_poll_set_enabled(false);
 824                 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
 825                 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector).  ****");
 826                 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected   ****");
 827                 LOG_WARNING("**** and configured, use 'reset halt'                           ****");
 828                 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running  ****");
 829                 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase'         ****");
 830
 831         } else {
 832                 LOG_INFO("MDM: Chip is unsecured. Continuing.");
 833                 jtag_poll_set_enabled(true);
 834         }
 835
 836         return ERROR_OK;
 837 }
 838
 839
 840 static struct kinetis_chip *kinetis_get_chip(struct target *target)
 841 {
 842         struct flash_bank *bank_iter;
 843         struct kinetis_flash_bank *k_bank;
 844
 845         /* iterate over all kinetis banks */
 846         for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
 847                 if (bank_iter->driver != &kinetis_flash
 848                     || bank_iter->target != target)
 849                         continue;
 850
 851                 k_bank = bank_iter->driver_priv;
 852                 if (!k_bank)
 853                         continue;
 854
 855                 if (k_bank->k_chip)
 856                         return k_bank->k_chip;
 857         }
 858         return NULL;
 859 }
 860
 861 static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
 862 {
 863         int i;
 864         for (i = 0; i < argc; i++) {
 865                 if (strcmp(argv[i], "-sim-base") == 0) {
 866                         if (i + 1 < argc)
 867                                 k_chip->sim_base = strtoul(argv[++i], NULL, 0);
 868                 } else
 869                         LOG_ERROR("Unsupported flash bank option %s", argv[i]);
 870         }
 871         return ERROR_OK;
 872 }
 873
 874 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
 875 {
 876         struct target *target = bank->target;
 877         struct kinetis_chip *k_chip;
 878         struct kinetis_flash_bank *k_bank;
 879         int retval;
 880
 881         if (CMD_ARGC < 6)
 882                 return ERROR_COMMAND_SYNTAX_ERROR;
 883
 884         LOG_INFO("add flash_bank kinetis %s", bank->name);
 885
 886         k_chip = kinetis_get_chip(target);
 887
 888         if (k_chip == NULL) {
 889                 k_chip = calloc(sizeof(struct kinetis_chip), 1);
 890                 if (k_chip == NULL) {
 891                         LOG_ERROR("No memory");
 892                         return ERROR_FAIL;
 893                 }
 894
 895                 k_chip->target = target;
 896
 897                 /* only the first defined bank can define chip options */
 898                 retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV + 6);
 899                 if (retval != ERROR_OK)
 900                         return retval;
 901         }
 902
 903         if (k_chip->num_banks >= KINETIS_MAX_BANKS) {
 904                 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
 905                 return ERROR_FAIL;
 906         }
 907
 908         bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
 909         k_bank->k_chip = k_chip;
 910         k_bank->bank_number = k_chip->num_banks;
 911         k_bank->bank = bank;
 912         k_chip->num_banks++;
 913
 914         return ERROR_OK;
 915 }
 916
 917
 918 static void kinetis_free_driver_priv(struct flash_bank *bank)
 919 {
 920         struct kinetis_flash_bank *k_bank = bank->driver_priv;
 921         if (k_bank == NULL)
 922                 return;
 923
 924         struct kinetis_chip *k_chip = k_bank->k_chip;
 925         if (k_chip == NULL)
 926                 return;
 927
 928         k_chip->num_banks--;
 929         if (k_chip->num_banks == 0)
 930                 free(k_chip);
 931 }
 932
 933
 934 static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
 935 {
 936         unsigned bank_idx;
 937         unsigned num_blocks;
 938         struct kinetis_flash_bank *k_bank;
 939         struct flash_bank *bank;
 940         char base_name[80], name[80], num[4];
 941         char *class, *p;
 942
 943         num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
 944         if (num_blocks > KINETIS_MAX_BANKS) {
 945                 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
 946                 return ERROR_FAIL;
 947         }
 948
 949         bank = k_chip->banks[0].bank;
 950         if (bank && bank->name) {
 951                 strncpy(base_name, bank->name, sizeof(base_name));
 952                 p = strstr(base_name, ".pflash");
 953                 if (p) {
 954                         *p = '\0';
 955                         if (k_chip->num_pflash_blocks > 1) {
 956                                 /* rename first bank if numbering is needed */
 957                                 snprintf(name, sizeof(name), "%s.pflash0", base_name);
 958                                 free(bank->name);
 959                                 bank->name = strdup(name);
 960                         }
 961                 }
 962         } else {
 963                 strncpy(base_name, target_name(k_chip->target), sizeof(base_name));
 964                 p = strstr(base_name, ".cpu");
 965                 if (p)
 966                         *p = '\0';
 967         }
 968
 969         for (bank_idx = 1; bank_idx < num_blocks; bank_idx++) {
 970                 k_bank = &(k_chip->banks[bank_idx]);
 971                 bank = k_bank->bank;
 972
 973                 if (bank)
 974                         continue;
 975
 976                 num[0] = '\0';
 977
 978                 if (bank_idx < k_chip->num_pflash_blocks) {
 979                         class = "pflash";
 980                         if (k_chip->num_pflash_blocks > 1)
 981                                 snprintf(num, sizeof(num), "%u", bank_idx);
 982                 } else {
 983                         class = "flexnvm";
 984                         if (k_chip->num_nvm_blocks > 1)
 985                                 snprintf(num, sizeof(num), "%u",
 986                                          bank_idx - k_chip->num_pflash_blocks);
 987                 }
 988
 989                 bank = calloc(sizeof(struct flash_bank), 1);
 990                 if (bank == NULL)
 991                         return ERROR_FAIL;
 992
 993                 bank->target = k_chip->target;
 994                 bank->driver = &kinetis_flash;
 995                 bank->default_padded_value = bank->erased_value = 0xff;
 996
 997                 snprintf(name, sizeof(name), "%s.%s%s",
 998                          base_name, class, num);
 999                 bank->name = strdup(name);
1000
1001                 bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
1002                 k_bank->k_chip = k_chip;
1003                 k_bank->bank_number = bank_idx;
1004                 k_bank->bank = bank;
1005                 if (k_chip->num_banks <= bank_idx)
1006                         k_chip->num_banks = bank_idx + 1;
1007
1008                 flash_bank_add(bank);
1009         }
1010         return ERROR_OK;
1011 }
1012
1013
1014 static int kinetis_disable_wdog_algo(struct target *target, size_t code_size, const uint8_t *code, uint32_t wdog_base)
1015 {
1016         struct working_area *wdog_algorithm;
1017         struct armv7m_algorithm armv7m_info;
1018         struct reg_param reg_params[1];
1019         int retval;
1020
1021         if (target->state != TARGET_HALTED) {
1022                 LOG_ERROR("Target not halted");
1023                 return ERROR_TARGET_NOT_HALTED;
1024         }
1025
1026         retval = target_alloc_working_area(target, code_size, &wdog_algorithm);
1027         if (retval != ERROR_OK)
1028                 return retval;
1029
1030         retval = target_write_buffer(target, wdog_algorithm->address,
1031                         code_size, code);
1032         if (retval == ERROR_OK) {
1033                 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1034                 armv7m_info.core_mode = ARM_MODE_THREAD;
1035
1036                 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
1037                 buf_set_u32(reg_params[0].value, 0, 32, wdog_base);
1038
1039                 retval = target_run_algorithm(target, 0, NULL, 1, reg_params,
1040                         wdog_algorithm->address,
1041                         wdog_algorithm->address + code_size - 2,
1042                         500, &armv7m_info);
1043
1044                 destroy_reg_param(&reg_params[0]);
1045
1046                 if (retval != ERROR_OK)
1047                         LOG_ERROR("Error executing Kinetis WDOG unlock algorithm");
1048         }
1049
1050         target_free_working_area(target, wdog_algorithm);
1051
1052         return retval;
1053 }
1054
1055 /* Disable the watchdog on Kinetis devices
1056  * Standard Kx WDOG peripheral checks timing and therefore requires to run algo.
1057  */
1058 static int kinetis_disable_wdog_kx(struct target *target)
1059 {
1060         const uint32_t wdog_base = WDOG_BASE;
1061         uint16_t wdog;
1062         int retval;
1063
1064         static const uint8_t kinetis_unlock_wdog_code[] = {
1065 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
1066         };
1067
1068         retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1069         if (retval != ERROR_OK)
1070                 return retval;
1071
1072         if ((wdog & 0x1) == 0) {
1073                 /* watchdog already disabled */
1074                 return ERROR_OK;
1075         }
1076         LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%04" PRIx16 ")", wdog);
1077
1078         retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1079         if (retval != ERROR_OK)
1080                 return retval;
1081
1082         retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1083         if (retval != ERROR_OK)
1084                 return retval;
1085
1086         LOG_INFO("WDOG_STCTRLH = 0x%04" PRIx16, wdog);
1087         return (wdog & 0x1) ? ERROR_FAIL : ERROR_OK;
1088 }
1089
1090 static int kinetis_disable_wdog32(struct target *target, uint32_t wdog_base)
1091 {
1092         uint32_t wdog_cs;
1093         int retval;
1094
1095         static const uint8_t kinetis_unlock_wdog_code[] = {
1096 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog32.inc"
1097         };
1098
1099         retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1100         if (retval != ERROR_OK)
1101                 return retval;
1102
1103         if ((wdog_cs & 0x80) == 0)
1104                 return ERROR_OK; /* watchdog already disabled */
1105
1106         LOG_INFO("Disabling Kinetis watchdog (initial WDOG_CS 0x%08" PRIx32 ")", wdog_cs);
1107
1108         retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1109         if (retval != ERROR_OK)
1110                 return retval;
1111
1112         retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1113         if (retval != ERROR_OK)
1114                 return retval;
1115
1116         if ((wdog_cs & 0x80) == 0)
1117                 return ERROR_OK; /* watchdog disabled successfully */
1118
1119         LOG_ERROR("Cannot disable Kinetis watchdog (WDOG_CS 0x%08" PRIx32 "), issue 'reset init'", wdog_cs);
1120         return ERROR_FAIL;
1121 }
1122
1123 static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
1124 {
1125         struct target *target = k_chip->target;
1126         uint8_t sim_copc;
1127         int retval;
1128
1129         if (!k_chip->probed) {
1130                 retval = kinetis_probe_chip(k_chip);
1131                 if (retval != ERROR_OK)
1132                         return retval;
1133         }
1134
1135         switch (k_chip->watchdog_type) {
1136         case KINETIS_WDOG_K:
1137                 return kinetis_disable_wdog_kx(target);
1138
1139         case KINETIS_WDOG_COP:
1140                 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1141                 if (retval != ERROR_OK)
1142                         return retval;
1143
1144                 if ((sim_copc & 0xc) == 0)
1145                         return ERROR_OK; /* watchdog already disabled */
1146
1147                 LOG_INFO("Disabling Kinetis watchdog (initial SIM_COPC 0x%02" PRIx8 ")", sim_copc);
1148                 retval = target_write_u8(target, SIM_COPC, sim_copc & ~0xc);
1149                 if (retval != ERROR_OK)
1150                         return retval;
1151
1152                 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1153                 if (retval != ERROR_OK)
1154                         return retval;
1155
1156                 if ((sim_copc & 0xc) == 0)
1157                         return ERROR_OK; /* watchdog disabled successfully */
1158
1159                 LOG_ERROR("Cannot disable Kinetis watchdog (SIM_COPC 0x%02" PRIx8 "), issue 'reset init'", sim_copc);
1160                 return ERROR_FAIL;
1161
1162         case KINETIS_WDOG32_KE1X:
1163                 return kinetis_disable_wdog32(target, WDOG32_KE1X);
1164
1165         case KINETIS_WDOG32_KL28:
1166                 return kinetis_disable_wdog32(target, WDOG32_KL28);
1167
1168         default:
1169                 return ERROR_OK;
1170         }
1171 }
1172
1173 COMMAND_HANDLER(kinetis_disable_wdog_handler)
1174 {
1175         int result;
1176         struct target *target = get_current_target(CMD_CTX);
1177         struct kinetis_chip *k_chip = kinetis_get_chip(target);
1178
1179         if (k_chip == NULL)
1180                 return ERROR_FAIL;
1181
1182         if (CMD_ARGC > 0)
1183                 return ERROR_COMMAND_SYNTAX_ERROR;
1184
1185         result = kinetis_disable_wdog(k_chip);
1186         return result;
1187 }
1188
1189
1190 static int kinetis_ftfx_decode_error(uint8_t fstat)
1191 {
1192         if (fstat & 0x20) {
1193                 LOG_ERROR("Flash operation failed, illegal command");
1194                 return ERROR_FLASH_OPER_UNSUPPORTED;
1195
1196         } else if (fstat & 0x10)
1197                 LOG_ERROR("Flash operation failed, protection violated");
1198
1199         else if (fstat & 0x40)
1200                 LOG_ERROR("Flash operation failed, read collision");
1201
1202         else if (fstat & 0x80)
1203                 return ERROR_OK;
1204
1205         else
1206                 LOG_ERROR("Flash operation timed out");
1207
1208         return ERROR_FLASH_OPERATION_FAILED;
1209 }
1210
1211 static int kinetis_ftfx_clear_error(struct target *target)
1212 {
1213         /* reset error flags */
1214         return target_write_u8(target, FTFx_FSTAT, 0x70);
1215 }
1216
1217
1218 static int kinetis_ftfx_prepare(struct target *target)
1219 {
1220         int result, i;
1221         uint8_t fstat;
1222
1223         /* wait until busy */
1224         for (i = 0; i < 50; i++) {
1225                 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1226                 if (result != ERROR_OK)
1227                         return result;
1228
1229                 if (fstat & 0x80)
1230                         break;
1231         }
1232
1233         if ((fstat & 0x80) == 0) {
1234                 LOG_ERROR("Flash controller is busy");
1235                 return ERROR_FLASH_OPERATION_FAILED;
1236         }
1237         if (fstat != 0x80) {
1238                 /* reset error flags */
1239                 result = kinetis_ftfx_clear_error(target);
1240         }
1241         return result;
1242 }
1243
1244 /* Kinetis Program-LongWord Microcodes */
1245 static const uint8_t kinetis_flash_write_code[] = {
1246 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
1247 };
1248
1249 /* Program LongWord Block Write */
1250 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
1251                 uint32_t offset, uint32_t wcount)
1252 {
1253         struct target *target = bank->target;
1254         uint32_t buffer_size = 2048;            /* Default minimum value */
1255         struct working_area *write_algorithm;
1256         struct working_area *source;
1257         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1258         uint32_t address = k_bank->prog_base + offset;
1259         uint32_t end_address;
1260         struct reg_param reg_params[5];
1261         struct armv7m_algorithm armv7m_info;
1262         int retval;
1263         uint8_t fstat;
1264
1265         /* Increase buffer_size if needed */
1266         if (buffer_size < (target->working_area_size/2))
1267                 buffer_size = (target->working_area_size/2);
1268
1269         /* allocate working area with flash programming code */
1270         if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
1271                         &write_algorithm) != ERROR_OK) {
1272                 LOG_WARNING("no working area available, can't do block memory writes");
1273                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274         }
1275
1276         retval = target_write_buffer(target, write_algorithm->address,
1277                 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
1278         if (retval != ERROR_OK)
1279                 return retval;
1280
1281         /* memory buffer */
1282         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
1283                 buffer_size /= 4;
1284                 if (buffer_size <= 256) {
1285                         /* free working area, write algorithm already allocated */
1286                         target_free_working_area(target, write_algorithm);
1287
1288                         LOG_WARNING("No large enough working area available, can't do block memory writes");
1289                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1290                 }
1291         }
1292
1293         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1294         armv7m_info.core_mode = ARM_MODE_THREAD;
1295
1296         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* address */
1297         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* word count */
1298         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1299         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1300         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1301
1302         buf_set_u32(reg_params[0].value, 0, 32, address);
1303         buf_set_u32(reg_params[1].value, 0, 32, wcount);
1304         buf_set_u32(reg_params[2].value, 0, 32, source->address);
1305         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
1306         buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
1307
1308         retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
1309                                                 0, NULL,
1310                                                 5, reg_params,
1311                                                 source->address, source->size,
1312                                                 write_algorithm->address, 0,
1313                                                 &armv7m_info);
1314
1315         if (retval == ERROR_FLASH_OPERATION_FAILED) {
1316                 end_address = buf_get_u32(reg_params[0].value, 0, 32);
1317
1318                 LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
1319
1320                 retval = target_read_u8(target, FTFx_FSTAT, &fstat);
1321                 if (retval == ERROR_OK) {
1322                         retval = kinetis_ftfx_decode_error(fstat);
1323
1324                         /* reset error flags */
1325                         target_write_u8(target, FTFx_FSTAT, 0x70);
1326                 }
1327         } else if (retval != ERROR_OK)
1328                 LOG_ERROR("Error executing kinetis Flash programming algorithm");
1329
1330         target_free_working_area(target, source);
1331         target_free_working_area(target, write_algorithm);
1332
1333         destroy_reg_param(&reg_params[0]);
1334         destroy_reg_param(&reg_params[1]);
1335         destroy_reg_param(&reg_params[2]);
1336         destroy_reg_param(&reg_params[3]);
1337         destroy_reg_param(&reg_params[4]);
1338
1339         return retval;
1340 }
1341
1342 static int kinetis_protect(struct flash_bank *bank, int set, int first, int last)
1343 {
1344         int i;
1345
1346         if (allow_fcf_writes) {
1347                 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1348                 return ERROR_FAIL;
1349         }
1350
1351         if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
1352                 LOG_ERROR("No protection possible for current bank!");
1353                 return ERROR_FLASH_BANK_INVALID;
1354         }
1355
1356         for (i = first; i < bank->num_prot_blocks && i <= last; i++)
1357                 bank->prot_blocks[i].is_protected = set;
1358
1359         LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1360         LOG_INFO("Do not issue 'flash info' command until protection is written,");
1361         LOG_INFO("doing so would re-read protection status from MCU.");
1362
1363         return ERROR_OK;
1364 }
1365
1366 static int kinetis_protect_check(struct flash_bank *bank)
1367 {
1368         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1369         int result;
1370         int i, b;
1371         uint32_t fprot;
1372
1373         if (k_bank->flash_class == FC_PFLASH) {
1374
1375                 /* read protection register */
1376                 result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
1377                 if (result != ERROR_OK)
1378                         return result;
1379
1380                 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1381
1382         } else if (k_bank->flash_class == FC_FLEX_NVM) {
1383                 uint8_t fdprot;
1384
1385                 /* read protection register */
1386                 result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
1387                 if (result != ERROR_OK)
1388                         return result;
1389
1390                 fprot = fdprot;
1391
1392         } else {
1393                 LOG_ERROR("Protection checks for FlexRAM not supported");
1394                 return ERROR_FLASH_BANK_INVALID;
1395         }
1396
1397         b = k_bank->protection_block;
1398         for (i = 0; i < bank->num_prot_blocks; i++) {
1399                 if ((fprot >> b) & 1)
1400                         bank->prot_blocks[i].is_protected = 0;
1401                 else
1402                         bank->prot_blocks[i].is_protected = 1;
1403
1404                 b++;
1405         }
1406
1407         return ERROR_OK;
1408 }
1409
1410
1411 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1412 {
1413         uint32_t fprot = 0xffffffff;
1414         uint8_t fsec = 0xfe;             /* set MCU unsecure */
1415         uint8_t fdprot = 0xff;
1416         int i;
1417         unsigned bank_idx;
1418         unsigned num_blocks;
1419         uint32_t pflash_bit;
1420         uint8_t dflash_bit;
1421         struct flash_bank *bank_iter;
1422         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1423         struct kinetis_chip *k_chip = k_bank->k_chip;
1424
1425         memset(fcf, 0xff, FCF_SIZE);
1426
1427         pflash_bit = 1;
1428         dflash_bit = 1;
1429
1430         /* iterate over all kinetis banks */
1431         /* current bank is bank 0, it contains FCF */
1432         num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
1433         for (bank_idx = 0; bank_idx < num_blocks; bank_idx++) {
1434                 k_bank = &(k_chip->banks[bank_idx]);
1435                 bank_iter = k_bank->bank;
1436
1437                 if (bank_iter == NULL) {
1438                         LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
1439                         continue;
1440                 }
1441
1442                 kinetis_auto_probe(bank_iter);
1443
1444                 if (k_bank->flash_class == FC_PFLASH) {
1445                         for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1446                                 if (bank_iter->prot_blocks[i].is_protected == 1)
1447                                         fprot &= ~pflash_bit;
1448
1449                                 pflash_bit <<= 1;
1450                         }
1451
1452                 } else if (k_bank->flash_class == FC_FLEX_NVM) {
1453                         for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1454                                 if (bank_iter->prot_blocks[i].is_protected == 1)
1455                                         fdprot &= ~dflash_bit;
1456
1457                                 dflash_bit <<= 1;
1458                         }
1459
1460                 }
1461         }
1462
1463         target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1464         fcf[FCF_FSEC] = fsec;
1465         fcf[FCF_FOPT] = fcf_fopt;
1466         fcf[FCF_FDPROT] = fdprot;
1467         return ERROR_OK;
1468 }
1469
1470 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1471                                 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1472                                 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1473                                 uint8_t *ftfx_fstat)
1474 {
1475         uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1476                         fccob7, fccob6, fccob5, fccob4,
1477                         fccobb, fccoba, fccob9, fccob8};
1478         int result;
1479         uint8_t fstat;
1480         int64_t ms_timeout = timeval_ms() + 250;
1481
1482         result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
1483         if (result != ERROR_OK)
1484                 return result;
1485
1486         /* start command */
1487         result = target_write_u8(target, FTFx_FSTAT, 0x80);
1488         if (result != ERROR_OK)
1489                 return result;
1490
1491         /* wait for done */
1492         do {
1493                 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1494
1495                 if (result != ERROR_OK)
1496                         return result;
1497
1498                 if (fstat & 0x80)
1499                         break;
1500
1501         } while (timeval_ms() < ms_timeout);
1502
1503         if (ftfx_fstat)
1504                 *ftfx_fstat = fstat;
1505
1506         if ((fstat & 0xf0) != 0x80) {
1507                 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1508                          fstat, command[3], command[2], command[1], command[0],
1509                          command[7], command[6], command[5], command[4],
1510                          command[11], command[10], command[9], command[8]);
1511
1512                 return kinetis_ftfx_decode_error(fstat);
1513         }
1514
1515         return ERROR_OK;
1516 }
1517
1518
1519 static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
1520 {
1521         int result;
1522         uint32_t stat32;
1523         struct target *target = k_chip->target;
1524
1525         switch (k_chip->sysmodectrlr_type) {
1526         case KINETIS_SMC:
1527                 result = target_read_u8(target, SMC_PMSTAT, pmstat);
1528                 return result;
1529
1530         case KINETIS_SMC32:
1531                 result = target_read_u32(target, SMC32_PMSTAT, &stat32);
1532                 if (result == ERROR_OK)
1533                         *pmstat = stat32 & 0xff;
1534                 return result;
1535         }
1536         return ERROR_FAIL;
1537 }
1538
1539 static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
1540 {
1541         int result, i;
1542         uint8_t pmstat;
1543         struct target *target;
1544
1545         if (k_chip == NULL) {
1546                 LOG_ERROR("Chip not probed.");
1547                 return ERROR_FAIL;
1548         }
1549         target = k_chip->target;
1550
1551         if (target->state != TARGET_HALTED) {
1552                 LOG_ERROR("Target not halted");
1553                 return ERROR_TARGET_NOT_HALTED;
1554         }
1555
1556         result = kinetis_read_pmstat(k_chip, &pmstat);
1557         if (result != ERROR_OK)
1558                 return result;
1559
1560         if (pmstat == PM_STAT_RUN)
1561                 return ERROR_OK;
1562
1563         if (pmstat == PM_STAT_VLPR) {
1564                 /* It is safe to switch from VLPR to RUN mode without changing clock */
1565                 LOG_INFO("Switching from VLPR to RUN mode.");
1566
1567                 switch (k_chip->sysmodectrlr_type) {
1568                 case KINETIS_SMC:
1569                         result = target_write_u8(target, SMC_PMCTRL, PM_CTRL_RUNM_RUN);
1570                         break;
1571
1572                 case KINETIS_SMC32:
1573                         result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN);
1574                         break;
1575                 }
1576                 if (result != ERROR_OK)
1577                         return result;
1578
1579                 for (i = 100; i; i--) {
1580                         result = kinetis_read_pmstat(k_chip, &pmstat);
1581                         if (result != ERROR_OK)
1582                                 return result;
1583
1584                         if (pmstat == PM_STAT_RUN)
1585                                 return ERROR_OK;
1586                 }
1587         }
1588
1589         LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1590         LOG_ERROR("Issue a 'reset init' command.");
1591         return ERROR_TARGET_NOT_HALTED;
1592 }
1593
1594
1595 static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip)
1596 {
1597         struct target *target = k_chip->target;
1598
1599         switch (k_chip->cache_type) {
1600         case KINETIS_CACHE_K:
1601                 target_write_u8(target, FMC_PFB01CR + 2, 0xf0);
1602                 /* Set CINV_WAY bits - request invalidate of all cache ways */
1603                 /* FMC_PFB0CR has same address and CINV_WAY bits as FMC_PFB01CR */
1604                 break;
1605
1606         case KINETIS_CACHE_L:
1607                 target_write_u8(target, MCM_PLACR + 1, 0x04);
1608                 /* set bit CFCC - Clear Flash Controller Cache */
1609                 break;
1610
1611         case KINETIS_CACHE_MSCM:
1612                 target_write_u32(target, MSCM_OCMDR0, 0x30);
1613                 /* disable data prefetch and flash speculate */
1614                 break;
1615
1616         default:
1617                 break;
1618         }
1619 }
1620
1621
1622 static int kinetis_erase(struct flash_bank *bank, int first, int last)
1623 {
1624         int result, i;
1625         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1626         struct kinetis_chip *k_chip = k_bank->k_chip;
1627
1628         result = kinetis_check_run_mode(k_chip);
1629         if (result != ERROR_OK)
1630                 return result;
1631
1632         /* reset error flags */
1633         result = kinetis_ftfx_prepare(bank->target);
1634         if (result != ERROR_OK)
1635                 return result;
1636
1637         if ((first > bank->num_sectors) || (last > bank->num_sectors))
1638                 return ERROR_FLASH_OPERATION_FAILED;
1639
1640         /*
1641          * FIXME: TODO: use the 'Erase Flash Block' command if the
1642          * requested erase is PFlash or NVM and encompasses the entire
1643          * block.  Should be quicker.
1644          */
1645         for (i = first; i <= last; i++) {
1646                 /* set command and sector address */
1647                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
1648                                 0, 0, 0, 0,  0, 0, 0, 0,  NULL);
1649
1650                 if (result != ERROR_OK) {
1651                         LOG_WARNING("erase sector %d failed", i);
1652                         return ERROR_FLASH_OPERATION_FAILED;
1653                 }
1654
1655                 bank->sectors[i].is_erased = 1;
1656
1657                 if (k_bank->prog_base == 0
1658                         && bank->sectors[i].offset <= FCF_ADDRESS
1659                         && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1660                         if (allow_fcf_writes) {
1661                                 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1662                                 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1663                         } else {
1664                                 uint8_t fcf_buffer[FCF_SIZE];
1665
1666                                 kinetis_fill_fcf(bank, fcf_buffer);
1667                                 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1668                                 if (result != ERROR_OK)
1669                                         LOG_WARNING("Flash Configuration Field write failed");
1670                                 bank->sectors[i].is_erased = 0;
1671                         }
1672                 }
1673         }
1674
1675         kinetis_invalidate_flash_cache(k_bank->k_chip);
1676
1677         return ERROR_OK;
1678 }
1679
1680 static int kinetis_make_ram_ready(struct target *target)
1681 {
1682         int result;
1683         uint8_t ftfx_fcnfg;
1684
1685         /* check if ram ready */
1686         result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1687         if (result != ERROR_OK)
1688                 return result;
1689
1690         if (ftfx_fcnfg & (1 << 1))
1691                 return ERROR_OK;        /* ram ready */
1692
1693         /* make flex ram available */
1694         result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1695                                  0, 0, 0, 0,  0, 0, 0, 0,  NULL);
1696         if (result != ERROR_OK)
1697                 return ERROR_FLASH_OPERATION_FAILED;
1698
1699         /* check again */
1700         result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1701         if (result != ERROR_OK)
1702                 return result;
1703
1704         if (ftfx_fcnfg & (1 << 1))
1705                 return ERROR_OK;        /* ram ready */
1706
1707         return ERROR_FLASH_OPERATION_FAILED;
1708 }
1709
1710
1711 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1712                          uint32_t offset, uint32_t count)
1713 {
1714         int result = ERROR_OK;
1715         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1716         struct kinetis_chip *k_chip = k_bank->k_chip;
1717         uint8_t *buffer_aligned = NULL;
1718         /*
1719          * Kinetis uses different terms for the granularity of
1720          * sector writes, e.g. "phrase" or "128 bits".  We use
1721          * the generic term "chunk". The largest possible
1722          * Kinetis "chunk" is 16 bytes (128 bits).
1723          */
1724         uint32_t prog_section_chunk_bytes = k_bank->sector_size >> 8;
1725         uint32_t prog_size_bytes = k_chip->max_flash_prog_size;
1726
1727         while (count > 0) {
1728                 uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1729                 uint32_t align_begin = offset % prog_section_chunk_bytes;
1730                 uint32_t align_end;
1731                 uint32_t size_aligned;
1732                 uint16_t chunk_count;
1733                 uint8_t ftfx_fstat;
1734
1735                 if (size > count)
1736                         size = count;
1737
1738                 align_end = (align_begin + size) % prog_section_chunk_bytes;
1739                 if (align_end)
1740                         align_end = prog_section_chunk_bytes - align_end;
1741
1742                 size_aligned = align_begin + size + align_end;
1743                 chunk_count = size_aligned / prog_section_chunk_bytes;
1744
1745                 if (size != size_aligned) {
1746                         /* aligned section: the first, the last or the only */
1747                         if (!buffer_aligned)
1748                                 buffer_aligned = malloc(prog_size_bytes);
1749
1750                         memset(buffer_aligned, 0xff, size_aligned);
1751                         memcpy(buffer_aligned + align_begin, buffer, size);
1752
1753                         result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1754                                                 4, size_aligned / 4, buffer_aligned);
1755
1756                         LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
1757                                         bank->base + offset, align_begin, align_end);
1758                 } else
1759                         result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1760                                                 4, size_aligned / 4, buffer);
1761
1762                 LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
1763                           bank->base + offset, size);
1764
1765                 if (result != ERROR_OK) {
1766                         LOG_ERROR("target_write_memory failed");
1767                         break;
1768                 }
1769
1770                 /* execute section-write command */
1771                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
1772                                 k_bank->prog_base + offset - align_begin,
1773                                 chunk_count>>8, chunk_count, 0, 0,
1774                                 0, 0, 0, 0,  &ftfx_fstat);
1775
1776                 if (result != ERROR_OK) {
1777                         LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
1778                         break;
1779                 }
1780
1781                 if (ftfx_fstat & 0x01) {
1782                         LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1783                         if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
1784                                         && (k_chip->flash_support & FS_WIDTH_256BIT)) {
1785                                 LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
1786                                 LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
1787                                 LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
1788                                 LOG_ERROR("or set 'kinetis fcf_source write'");
1789                         }
1790                 }
1791
1792                 buffer += size;
1793                 offset += size;
1794                 count -= size;
1795         }
1796
1797         free(buffer_aligned);
1798         return result;
1799 }
1800
1801
1802 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1803                          uint32_t offset, uint32_t count)
1804 {
1805         int result, fallback = 0;
1806         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1807         struct kinetis_chip *k_chip = k_bank->k_chip;
1808
1809         if (!(k_chip->flash_support & FS_PROGRAM_SECTOR)) {
1810                 /* fallback to longword write */
1811                 fallback = 1;
1812                 LOG_INFO("This device supports Program Longword execution only.");
1813         } else {
1814                 result = kinetis_make_ram_ready(bank->target);
1815                 if (result != ERROR_OK) {
1816                         fallback = 1;
1817                         LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1818                 }
1819         }
1820
1821         LOG_DEBUG("flash write @ %08" PRIx32, bank->base + offset);
1822
1823         if (fallback == 0) {
1824                 /* program section command */
1825                 kinetis_write_sections(bank, buffer, offset, count);
1826         } else if (k_chip->flash_support & FS_PROGRAM_LONGWORD) {
1827                 /* program longword command, not supported in FTFE */
1828                 uint8_t *new_buffer = NULL;
1829
1830                 /* check word alignment */
1831                 if (offset & 0x3) {
1832                         LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1833                         return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1834                 }
1835
1836                 if (count & 0x3) {
1837                         uint32_t old_count = count;
1838                         count = (old_count | 3) + 1;
1839                         new_buffer = malloc(count);
1840                         if (new_buffer == NULL) {
1841                                 LOG_ERROR("odd number of bytes to write and no memory "
1842                                         "for padding buffer");
1843                                 return ERROR_FAIL;
1844                         }
1845                         LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1846                                 "and padding with 0xff", old_count, count);
1847                         memset(new_buffer + old_count, 0xff, count - old_count);
1848                         buffer = memcpy(new_buffer, buffer, old_count);
1849                 }
1850
1851                 uint32_t words_remaining = count / 4;
1852
1853                 kinetis_disable_wdog(k_chip);
1854
1855                 /* try using a block write */
1856                 result = kinetis_write_block(bank, buffer, offset, words_remaining);
1857
1858                 if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1859                         /* if block write failed (no sufficient working area),
1860                          * we use normal (slow) single word accesses */
1861                         LOG_WARNING("couldn't use block writes, falling back to single "
1862                                 "memory accesses");
1863
1864                         while (words_remaining) {
1865                                 uint8_t ftfx_fstat;
1866
1867                                 LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1868
1869                                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
1870                                                 buffer[3], buffer[2], buffer[1], buffer[0],
1871                                                 0, 0, 0, 0,  &ftfx_fstat);
1872
1873                                 if (result != ERROR_OK) {
1874                                         LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
1875                                         break;
1876                                 }
1877
1878                                 if (ftfx_fstat & 0x01)
1879                                         LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1880
1881                                 buffer += 4;
1882                                 offset += 4;
1883                                 words_remaining--;
1884                         }
1885                 }
1886                 free(new_buffer);
1887         } else {
1888                 LOG_ERROR("Flash write strategy not implemented");
1889                 return ERROR_FLASH_OPERATION_FAILED;
1890         }
1891
1892         kinetis_invalidate_flash_cache(k_chip);
1893         return result;
1894 }
1895
1896
1897 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1898                          uint32_t offset, uint32_t count)
1899 {
1900         int result;
1901         bool set_fcf = false;
1902         bool fcf_in_data_valid = false;
1903         int sect = 0;
1904         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1905         struct kinetis_chip *k_chip = k_bank->k_chip;
1906         uint8_t fcf_buffer[FCF_SIZE];
1907         uint8_t fcf_current[FCF_SIZE];
1908         uint8_t fcf_in_data[FCF_SIZE];
1909
1910         result = kinetis_check_run_mode(k_chip);
1911         if (result != ERROR_OK)
1912                 return result;
1913
1914         /* reset error flags */
1915         result = kinetis_ftfx_prepare(bank->target);
1916         if (result != ERROR_OK)
1917                 return result;
1918
1919         if (k_bank->prog_base == 0 && !allow_fcf_writes) {
1920                 if (bank->sectors[1].offset <= FCF_ADDRESS)
1921                         sect = 1;       /* 1kb sector, FCF in 2nd sector */
1922
1923                 if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
1924                         && offset + count > bank->sectors[sect].offset)
1925                         set_fcf = true; /* write to any part of sector with FCF */
1926         }
1927
1928         if (set_fcf) {
1929                 kinetis_fill_fcf(bank, fcf_buffer);
1930
1931                 fcf_in_data_valid = offset <= FCF_ADDRESS
1932                                          && offset + count >= FCF_ADDRESS + FCF_SIZE;
1933                 if (fcf_in_data_valid) {
1934                         memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
1935                         if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer, 4)) {
1936                                 fcf_in_data_valid = false;
1937                                 LOG_INFO("Flash protection requested in programmed file differs from current setting.");
1938                         }
1939                         if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
1940                                 fcf_in_data_valid = false;
1941                                 LOG_INFO("Data flash protection requested in programmed file differs from current setting.");
1942                         }
1943                         if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
1944                                 fcf_in_data_valid = false;
1945                                 LOG_INFO("Device security requested in programmed file!");
1946                         } else if (k_chip->flash_support & FS_ECC
1947                             && fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
1948                                 fcf_in_data_valid = false;
1949                                 LOG_INFO("Strange unsecure mode 0x%02" PRIx8
1950                                          "requested in programmed file!",
1951                                          fcf_in_data[FCF_FSEC]);
1952                         }
1953                         if ((k_chip->flash_support & FS_ECC || fcf_fopt_configured)
1954                             && fcf_in_data[FCF_FOPT] != fcf_fopt) {
1955                                 fcf_in_data_valid = false;
1956                                 LOG_INFO("FOPT requested in programmed file differs from current setting.");
1957                         }
1958                         if (!fcf_in_data_valid)
1959                                 LOG_INFO("Expect verify errors at FCF (0x408-0x40f).");
1960                 }
1961         }
1962
1963         if (set_fcf && !fcf_in_data_valid) {
1964                 if (offset < FCF_ADDRESS) {
1965                         /* write part preceding FCF */
1966                         result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
1967                         if (result != ERROR_OK)
1968                                 return result;
1969                 }
1970
1971                 result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
1972                 if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
1973                         set_fcf = false;
1974
1975                 if (set_fcf) {
1976                         /* write FCF if differs from flash - eliminate multiple writes */
1977                         result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1978                         if (result != ERROR_OK)
1979                                 return result;
1980                 }
1981
1982                 LOG_WARNING("Flash Configuration Field written.");
1983                 LOG_WARNING("Reset or power off the device to make settings effective.");
1984
1985                 if (offset + count > FCF_ADDRESS + FCF_SIZE) {
1986                         uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
1987                         /* write part after FCF */
1988                         result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
1989                 }
1990                 return result;
1991
1992         } else {
1993                 /* no FCF fiddling, normal write */
1994                 return kinetis_write_inner(bank, buffer, offset, count);
1995         }
1996 }
1997
1998
1999 static int kinetis_probe_chip(struct kinetis_chip *k_chip)
2000 {
2001         int result;
2002         uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
2003         uint8_t fcfg2_pflsh;
2004         uint32_t ee_size = 0;
2005         uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
2006         uint32_t pflash_size_m;
2007         unsigned num_blocks = 0;
2008         unsigned maxaddr_shift = 13;
2009         struct target *target = k_chip->target;
2010
2011         unsigned familyid = 0, subfamid = 0;
2012         unsigned cpu_mhz = 120;
2013         unsigned idx;
2014         bool use_nvm_marking = false;
2015         char flash_marking[11], nvm_marking[2];
2016         char name[40];
2017
2018         k_chip->probed = false;
2019         k_chip->pflash_sector_size = 0;
2020         k_chip->pflash_base = 0;
2021         k_chip->nvm_base = 0x10000000;
2022         k_chip->progr_accel_ram = FLEXRAM;
2023
2024         name[0] = '\0';
2025
2026         if (k_chip->sim_base)
2027                 result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2028         else {
2029                 result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2030                 if (result == ERROR_OK)
2031                         k_chip->sim_base = SIM_BASE;
2032                 else {
2033                         result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2034                         if (result == ERROR_OK)
2035                                 k_chip->sim_base = SIM_BASE_KL28;
2036                 }
2037         }
2038         if (result != ERROR_OK)
2039                 return result;
2040
2041         if ((k_chip->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
2042                 /* older K-series MCU */
2043                 uint32_t mcu_type = k_chip->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
2044                 k_chip->cache_type = KINETIS_CACHE_K;
2045                 k_chip->watchdog_type = KINETIS_WDOG_K;
2046
2047                 switch (mcu_type) {
2048                 case KINETIS_K_SDID_K10_M50:
2049                 case KINETIS_K_SDID_K20_M50:
2050                         /* 1kB sectors */
2051                         k_chip->pflash_sector_size = 1<<10;
2052                         k_chip->nvm_sector_size = 1<<10;
2053                         num_blocks = 2;
2054                         k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2055                         break;
2056                 case KINETIS_K_SDID_K10_M72:
2057                 case KINETIS_K_SDID_K20_M72:
2058                 case KINETIS_K_SDID_K30_M72:
2059                 case KINETIS_K_SDID_K30_M100:
2060                 case KINETIS_K_SDID_K40_M72:
2061                 case KINETIS_K_SDID_K40_M100:
2062                 case KINETIS_K_SDID_K50_M72:
2063                         /* 2kB sectors, 1kB FlexNVM sectors */
2064                         k_chip->pflash_sector_size = 2<<10;
2065                         k_chip->nvm_sector_size = 1<<10;
2066                         num_blocks = 2;
2067                         k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2068                         k_chip->max_flash_prog_size = 1<<10;
2069                         break;
2070                 case KINETIS_K_SDID_K10_M100:
2071                 case KINETIS_K_SDID_K20_M100:
2072                 case KINETIS_K_SDID_K11:
2073                 case KINETIS_K_SDID_K12:
2074                 case KINETIS_K_SDID_K21_M50:
2075                 case KINETIS_K_SDID_K22_M50:
2076                 case KINETIS_K_SDID_K51_M72:
2077                 case KINETIS_K_SDID_K53:
2078                 case KINETIS_K_SDID_K60_M100:
2079                         /* 2kB sectors */
2080                         k_chip->pflash_sector_size = 2<<10;
2081                         k_chip->nvm_sector_size = 2<<10;
2082                         num_blocks = 2;
2083                         k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2084                         break;
2085                 case KINETIS_K_SDID_K21_M120:
2086                 case KINETIS_K_SDID_K22_M120:
2087                         /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
2088                         k_chip->pflash_sector_size = 4<<10;
2089                         k_chip->max_flash_prog_size = 1<<10;
2090                         k_chip->nvm_sector_size = 4<<10;
2091                         num_blocks = 2;
2092                         k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2093                         break;
2094                 case KINETIS_K_SDID_K10_M120:
2095                 case KINETIS_K_SDID_K20_M120:
2096                 case KINETIS_K_SDID_K60_M150:
2097                 case KINETIS_K_SDID_K70_M150:
2098                         /* 4kB sectors */
2099                         k_chip->pflash_sector_size = 4<<10;
2100                         k_chip->nvm_sector_size = 4<<10;
2101                         num_blocks = 4;
2102                         k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2103                         break;
2104                 default:
2105                         LOG_ERROR("Unsupported K-family FAMID");
2106                 }
2107
2108                 for (idx = 0; idx < ARRAY_SIZE(kinetis_types_old); idx++) {
2109                         if (kinetis_types_old[idx].sdid == mcu_type) {
2110                                 strcpy(name, kinetis_types_old[idx].name);
2111                                 use_nvm_marking = true;
2112                                 break;
2113                         }
2114                 }
2115
2116         } else {
2117                 /* Newer K-series or KL series MCU */
2118                 familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT;
2119                 subfamid = (k_chip->sim_sdid & KINETIS_SDID_SUBFAMID_MASK) >> KINETIS_SDID_SUBFAMID_SHIFT;
2120
2121                 switch (k_chip->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
2122                 case KINETIS_SDID_SERIESID_K:
2123                         use_nvm_marking = true;
2124                         k_chip->cache_type = KINETIS_CACHE_K;
2125                         k_chip->watchdog_type = KINETIS_WDOG_K;
2126
2127                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2128                         case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
2129                                 /* K02FN64, K02FN128: FTFA, 2kB sectors */
2130                                 k_chip->pflash_sector_size = 2<<10;
2131                                 num_blocks = 1;
2132                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2133                                 cpu_mhz = 100;
2134                                 break;
2135
2136                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
2137                                 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
2138                                 uint32_t sopt1;
2139                                 result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
2140                                 if (result != ERROR_OK)
2141                                         return result;
2142
2143                                 if (((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
2144                                                 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
2145                                         /* MK24FN1M */
2146                                         k_chip->pflash_sector_size = 4<<10;
2147                                         num_blocks = 2;
2148                                         k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2149                                         k_chip->max_flash_prog_size = 1<<10;
2150                                         subfamid = 4; /* errata 1N83J fix */
2151                                         break;
2152                                 }
2153                                 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
2154                                         || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
2155                                         || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
2156                                         /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
2157                                         k_chip->pflash_sector_size = 2<<10;
2158                                         /* autodetect 1 or 2 blocks */
2159                                         k_chip->flash_support = FS_PROGRAM_LONGWORD;
2160                                         break;
2161                                 }
2162                                 LOG_ERROR("Unsupported Kinetis K22 DIEID");
2163                                 break;
2164                         }
2165                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
2166                                 k_chip->pflash_sector_size = 4<<10;
2167                                 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
2168                                         /* K24FN256 - smaller pflash with FTFA */
2169                                         num_blocks = 1;
2170                                         k_chip->flash_support = FS_PROGRAM_LONGWORD;
2171                                         break;
2172                                 }
2173                                 /* K24FN1M without errata 7534 */
2174                                 num_blocks = 2;
2175                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2176                                 k_chip->max_flash_prog_size = 1<<10;
2177                                 break;
2178
2179                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1:     /* errata 7534 - should be K63 */
2180                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2:     /* errata 7534 - should be K64 */
2181                                 subfamid += 2; /* errata 7534 fix */
2182                                 /* fallthrough */
2183                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
2184                                 /* K63FN1M0 */
2185                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
2186                                 /* K64FN1M0, K64FX512 */
2187                                 k_chip->pflash_sector_size = 4<<10;
2188                                 k_chip->nvm_sector_size = 4<<10;
2189                                 k_chip->max_flash_prog_size = 1<<10;
2190                                 num_blocks = 2;
2191                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2192                                 break;
2193
2194                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
2195                                 /* K26FN2M0 */
2196                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
2197                                 /* K66FN2M0, K66FX1M0 */
2198                                 k_chip->pflash_sector_size = 4<<10;
2199                                 k_chip->nvm_sector_size = 4<<10;
2200                                 k_chip->max_flash_prog_size = 1<<10;
2201                                 num_blocks = 4;
2202                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2203                                 cpu_mhz = 180;
2204                                 break;
2205
2206                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX7:
2207                                 /* K27FN2M0 */
2208                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2209                                 /* K28FN2M0 */
2210                                 k_chip->pflash_sector_size = 4<<10;
2211                                 k_chip->max_flash_prog_size = 1<<10;
2212                                 num_blocks = 4;
2213                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2214                                 cpu_mhz = 150;
2215                                 break;
2216
2217                         case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX0:
2218                         case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX1:
2219                         case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX2:
2220                                 /* K80FN256, K81FN256, K82FN256 */
2221                                 k_chip->pflash_sector_size = 4<<10;
2222                                 num_blocks = 1;
2223                                 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2224                                 cpu_mhz = 150;
2225                                 break;
2226
2227                         case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX1:
2228                         case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX2:
2229                                 /* KL81Z128, KL82Z128 */
2230                                 k_chip->pflash_sector_size = 2<<10;
2231                                 num_blocks = 1;
2232                                 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2233                                 k_chip->cache_type = KINETIS_CACHE_L;
2234
2235                                 use_nvm_marking = false;
2236                                 snprintf(name, sizeof(name), "MKL8%uZ%%s7",
2237                                          subfamid);
2238                                 break;
2239
2240                         default:
2241                                 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
2242                         }
2243
2244                         if (name[0] == '\0')
2245                                 snprintf(name, sizeof(name), "MK%u%uF%%s%u",
2246                                          familyid, subfamid, cpu_mhz / 10);
2247                         break;
2248
2249                 case KINETIS_SDID_SERIESID_KL:
2250                         /* KL-series */
2251                         k_chip->pflash_sector_size = 1<<10;
2252                         k_chip->nvm_sector_size = 1<<10;
2253                         /* autodetect 1 or 2 blocks */
2254                         k_chip->flash_support = FS_PROGRAM_LONGWORD;
2255                         k_chip->cache_type = KINETIS_CACHE_L;
2256                         k_chip->watchdog_type = KINETIS_WDOG_COP;
2257
2258                         cpu_mhz = 48;
2259                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2260                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX3:
2261                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX3:
2262                                 subfamid = 7;
2263                                 break;
2264
2265                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2266                                 cpu_mhz = 72;
2267                                 k_chip->pflash_sector_size = 2<<10;
2268                                 num_blocks = 2;
2269                                 k_chip->watchdog_type = KINETIS_WDOG32_KL28;
2270                                 k_chip->sysmodectrlr_type = KINETIS_SMC32;
2271                                 break;
2272                         }
2273
2274                         snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
2275                                  familyid, subfamid, cpu_mhz / 10);
2276                         break;
2277
2278                 case KINETIS_SDID_SERIESID_KW:
2279                         /* Newer KW-series (all KW series except KW2xD, KW01Z) */
2280                         cpu_mhz = 48;
2281                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2282                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX0:
2283                                 /* KW40Z */
2284                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2285                                 /* KW30Z */
2286                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX0:
2287                                 /* KW20Z */
2288                                 /* FTFA, 1kB sectors */
2289                                 k_chip->pflash_sector_size = 1<<10;
2290                                 k_chip->nvm_sector_size = 1<<10;
2291                                 /* autodetect 1 or 2 blocks */
2292                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2293                                 k_chip->cache_type = KINETIS_CACHE_L;
2294                                 k_chip->watchdog_type = KINETIS_WDOG_COP;
2295                                 break;
2296                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX1:
2297                                 /* KW41Z */
2298                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2299                                 /* KW31Z */
2300                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX1:
2301                                 /* KW21Z */
2302                                 /* FTFA, 2kB sectors */
2303                                 k_chip->pflash_sector_size = 2<<10;
2304                                 k_chip->nvm_sector_size = 2<<10;
2305                                 /* autodetect 1 or 2 blocks */
2306                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2307                                 k_chip->cache_type = KINETIS_CACHE_L;
2308                                 k_chip->watchdog_type = KINETIS_WDOG_COP;
2309                                 break;
2310                         default:
2311                                 LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
2312                         }
2313                         snprintf(name, sizeof(name), "MKW%u%uZ%%s%u",
2314                                          familyid, subfamid, cpu_mhz / 10);
2315                         break;
2316
2317                 case KINETIS_SDID_SERIESID_KV:
2318                         /* KV-series */
2319                         k_chip->watchdog_type = KINETIS_WDOG_K;
2320                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2321                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
2322                                 /* KV10: FTFA, 1kB sectors */
2323                                 k_chip->pflash_sector_size = 1<<10;
2324                                 num_blocks = 1;
2325                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2326                                 k_chip->cache_type = KINETIS_CACHE_L;
2327                                 strcpy(name, "MKV10Z%s7");
2328                                 break;
2329
2330                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
2331                                 /* KV11: FTFA, 2kB sectors */
2332                                 k_chip->pflash_sector_size = 2<<10;
2333                                 num_blocks = 1;
2334                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2335                                 k_chip->cache_type = KINETIS_CACHE_L;
2336                                 strcpy(name, "MKV11Z%s7");
2337                                 break;
2338
2339                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2340                                 /* KV30: FTFA, 2kB sectors, 1 block */
2341                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2342                                 /* KV31: FTFA, 2kB sectors, 2 blocks */
2343                                 k_chip->pflash_sector_size = 2<<10;
2344                                 /* autodetect 1 or 2 blocks */
2345                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2346                                 k_chip->cache_type = KINETIS_CACHE_K;
2347                                 break;
2348
2349                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
2350                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
2351                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
2352                                 /* KV4x: FTFA, 4kB sectors */
2353                                 k_chip->pflash_sector_size = 4<<10;
2354                                 num_blocks = 1;
2355                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2356                                 k_chip->cache_type = KINETIS_CACHE_K;
2357                                 cpu_mhz = 168;
2358                                 break;
2359
2360                         case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX6:
2361                         case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX8:
2362                                 /* KV5x: FTFE, 8kB sectors */
2363                                 k_chip->pflash_sector_size = 8<<10;
2364                                 k_chip->max_flash_prog_size = 1<<10;
2365                                 num_blocks = 1;
2366                                 maxaddr_shift = 14;
2367                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_WIDTH_256BIT | FS_ECC;
2368                                 k_chip->pflash_base = 0x10000000;
2369                                 k_chip->progr_accel_ram = 0x18000000;
2370                                 cpu_mhz = 240;
2371                                 break;
2372
2373                         default:
2374                                 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
2375                         }
2376
2377                         if (name[0] == '\0')
2378                                 snprintf(name, sizeof(name), "MKV%u%uF%%s%u",
2379                                          familyid, subfamid, cpu_mhz / 10);
2380                         break;
2381
2382                 case KINETIS_SDID_SERIESID_KE:
2383                         /* KE1x-series */
2384                         k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
2385                         switch (k_chip->sim_sdid &
2386                                 (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
2387                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
2388                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
2389                                 /* KE1xZ: FTFE, 2kB sectors */
2390                                 k_chip->pflash_sector_size = 2<<10;
2391                                 k_chip->nvm_sector_size = 2<<10;
2392                                 k_chip->max_flash_prog_size = 1<<9;
2393                                 num_blocks = 2;
2394                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2395                                 k_chip->cache_type = KINETIS_CACHE_L;
2396
2397                                 cpu_mhz = 72;
2398                                 snprintf(name, sizeof(name), "MKE%u%uZ%%s%u",
2399                                          familyid, subfamid, cpu_mhz / 10);
2400                                 break;
2401
2402                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
2403                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
2404                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
2405                                 /* KE1xF: FTFE, 4kB sectors */
2406                                 k_chip->pflash_sector_size = 4<<10;
2407                                 k_chip->nvm_sector_size = 2<<10;
2408                                 k_chip->max_flash_prog_size = 1<<10;
2409                                 num_blocks = 2;
2410                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2411                                 k_chip->cache_type = KINETIS_CACHE_MSCM;
2412
2413                                 cpu_mhz = 168;
2414                                 snprintf(name, sizeof(name), "MKE%u%uF%%s%u",
2415                                          familyid, subfamid, cpu_mhz / 10);
2416                                 break;
2417
2418                         default:
2419                                 LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
2420                         }
2421                         break;
2422
2423                 default:
2424                         LOG_ERROR("Unsupported K-series");
2425                 }
2426         }
2427
2428         if (k_chip->pflash_sector_size == 0) {
2429                 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
2430                 return ERROR_FLASH_OPER_UNSUPPORTED;
2431         }
2432
2433         result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
2434         if (result != ERROR_OK)
2435                 return result;
2436
2437         result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
2438         if (result != ERROR_OK)
2439                 return result;
2440
2441         LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
2442                         k_chip->sim_fcfg1, k_chip->sim_fcfg2);
2443
2444         fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
2445         fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
2446         fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
2447         fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2448
2449         fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2450         k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
2451         k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
2452
2453         if (num_blocks == 0)
2454                 num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
2455         else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 && fcfg2_pflsh) {
2456                 /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
2457                  * Do not adjust block count in this case! */
2458                 num_blocks = 1;
2459                 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
2460         } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
2461                 num_blocks = 2;
2462                 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
2463         }
2464
2465         /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
2466         if (!fcfg2_pflsh) {
2467                 switch (fcfg1_nvmsize) {
2468                 case 0x03:
2469                 case 0x05:
2470                 case 0x07:
2471                 case 0x09:
2472                 case 0x0b:
2473                         k_chip->nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
2474                         break;
2475                 case 0x0f:
2476                         if (k_chip->pflash_sector_size >= 4<<10)
2477                                 k_chip->nvm_size = 512<<10;
2478                         else
2479                                 /* K20_100 */
2480                                 k_chip->nvm_size = 256<<10;
2481                         break;
2482                 default:
2483                         k_chip->nvm_size = 0;
2484                         break;
2485                 }
2486
2487                 switch (fcfg1_eesize) {
2488                 case 0x00:
2489                 case 0x01:
2490                 case 0x02:
2491                 case 0x03:
2492                 case 0x04:
2493                 case 0x05:
2494                 case 0x06:
2495                 case 0x07:
2496                 case 0x08:
2497                 case 0x09:
2498                         ee_size = (16 << (10 - fcfg1_eesize));
2499                         break;
2500                 default:
2501                         ee_size = 0;
2502                         break;
2503                 }
2504
2505                 switch (fcfg1_depart) {
2506                 case 0x01:
2507                 case 0x02:
2508                 case 0x03:
2509                 case 0x04:
2510                 case 0x05:
2511                 case 0x06:
2512                         k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
2513                         break;
2514                 case 0x07:
2515                 case 0x08:
2516                         k_chip->dflash_size = 0;
2517                         break;
2518                 case 0x09:
2519                 case 0x0a:
2520                 case 0x0b:
2521                 case 0x0c:
2522                 case 0x0d:
2523                         k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
2524                         break;
2525                 default:
2526                         k_chip->dflash_size = k_chip->nvm_size;
2527                         break;
2528                 }
2529         }
2530
2531         switch (fcfg1_pfsize) {
2532         case 0x00:
2533                 k_chip->pflash_size = 8192;
2534                 break;
2535         case 0x01:
2536         case 0x03:
2537         case 0x05:
2538         case 0x07:
2539         case 0x09:
2540         case 0x0b:
2541         case 0x0d:
2542                 k_chip->pflash_size = 1 << (14 + (fcfg1_pfsize >> 1));
2543                 break;
2544         case 0x0f:
2545                 /* a peculiar case: Freescale states different sizes for 0xf
2546                  * KL03P24M48SF0RM      32 KB .... duplicate of code 0x3
2547                  * K02P64M100SFARM      128 KB ... duplicate of code 0x7
2548                  * K22P121M120SF8RM     256 KB ... duplicate of code 0x9
2549                  * K22P121M120SF7RM     512 KB ... duplicate of code 0xb
2550                  * K22P100M120SF5RM     1024 KB ... duplicate of code 0xd
2551                  * K26P169M180SF5RM     2048 KB ... the only unique value
2552                  * fcfg2_maxaddr0 seems to be the only clue to pflash_size
2553                  * Checking fcfg2_maxaddr0 in bank probe is pointless then
2554                  */
2555                 if (fcfg2_pflsh)
2556                         k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks;
2557                 else
2558                         k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
2559                 if (k_chip->pflash_size != 2048<<10)
2560                         LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
2561
2562                 break;
2563         default:
2564                 k_chip->pflash_size = 0;
2565                 break;
2566         }
2567
2568         if (k_chip->flash_support & FS_PROGRAM_SECTOR && k_chip->max_flash_prog_size == 0) {
2569                 k_chip->max_flash_prog_size = k_chip->pflash_sector_size;
2570                 /* Program section size is equal to sector size by default */
2571         }
2572
2573         if (fcfg2_pflsh) {
2574                 k_chip->num_pflash_blocks = num_blocks;
2575                 k_chip->num_nvm_blocks = 0;
2576         } else {
2577                 k_chip->num_pflash_blocks = (num_blocks + 1) / 2;
2578                 k_chip->num_nvm_blocks = num_blocks - k_chip->num_pflash_blocks;
2579         }
2580
2581         if (use_nvm_marking) {
2582                 nvm_marking[0] = k_chip->num_nvm_blocks ? 'X' : 'N';
2583                 nvm_marking[1] = '\0';
2584         } else
2585                 nvm_marking[0] = '\0';
2586
2587         pflash_size_k = k_chip->pflash_size / 1024;
2588         pflash_size_m = pflash_size_k / 1024;
2589         if (pflash_size_m)
2590                 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "M0xxx", nvm_marking, pflash_size_m);
2591         else
2592                 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "xxx", nvm_marking, pflash_size_k);
2593
2594         snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
2595         LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
2596         LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
2597         if (k_chip->num_nvm_blocks) {
2598                 nvm_size_k = k_chip->nvm_size / 1024;
2599                 dflash_size_k = k_chip->dflash_size / 1024;
2600                 LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
2601                          k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
2602         }
2603
2604         k_chip->probed = true;
2605
2606         if (create_banks)
2607                 kinetis_create_missing_banks(k_chip);
2608
2609         return ERROR_OK;
2610 }
2611
2612 static int kinetis_probe(struct flash_bank *bank)
2613 {
2614         int result, i;
2615         uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
2616         unsigned num_blocks, first_nvm_bank;
2617         uint32_t size_k;
2618         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2619         struct kinetis_chip *k_chip = k_bank->k_chip;
2620
2621         k_bank->probed = false;
2622
2623         if (!k_chip->probed) {
2624                 result = kinetis_probe_chip(k_chip);
2625                 if (result != ERROR_OK)
2626                         return result;
2627         }
2628
2629         num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2630         first_nvm_bank = k_chip->num_pflash_blocks;
2631
2632         if (k_bank->bank_number < k_chip->num_pflash_blocks) {
2633                 /* pflash, banks start at address zero */
2634                 k_bank->flash_class = FC_PFLASH;
2635                 bank->size = (k_chip->pflash_size / k_chip->num_pflash_blocks);
2636                 bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
2637                 k_bank->prog_base = 0x00000000 + bank->size * k_bank->bank_number;
2638                 k_bank->sector_size = k_chip->pflash_sector_size;
2639                 /* pflash is divided into 32 protection areas for
2640                  * parts with more than 32K of PFlash. For parts with
2641                  * less the protection unit is set to 1024 bytes */
2642                 k_bank->protection_size = MAX(k_chip->pflash_size / 32, 1024);
2643                 bank->num_prot_blocks = bank->size / k_bank->protection_size;
2644                 k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
2645
2646                 size_k = bank->size / 1024;
2647                 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
2648                          k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2649
2650         } else if (k_bank->bank_number < num_blocks) {
2651                 /* nvm, banks start at address 0x10000000 */
2652                 unsigned nvm_ord = k_bank->bank_number - first_nvm_bank;
2653                 uint32_t limit;
2654
2655                 k_bank->flash_class = FC_FLEX_NVM;
2656                 bank->size = k_chip->nvm_size / k_chip->num_nvm_blocks;
2657                 bank->base = k_chip->nvm_base + bank->size * nvm_ord;
2658                 k_bank->prog_base = 0x00800000 + bank->size * nvm_ord;
2659                 k_bank->sector_size = k_chip->nvm_sector_size;
2660                 if (k_chip->dflash_size == 0) {
2661                         k_bank->protection_size = 0;
2662                 } else {
2663                         for (i = k_chip->dflash_size; ~i & 1; i >>= 1)
2664                                 ;
2665                         if (i == 1)
2666                                 k_bank->protection_size = k_chip->dflash_size / 8;      /* data flash size = 2^^n */
2667                         else
2668                                 k_bank->protection_size = k_chip->nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
2669                 }
2670                 bank->num_prot_blocks = 8 / k_chip->num_nvm_blocks;
2671                 k_bank->protection_block = bank->num_prot_blocks * nvm_ord;
2672
2673                 /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
2674                 if (k_chip->dflash_size > bank->size * nvm_ord)
2675                         limit = k_chip->dflash_size - bank->size * nvm_ord;
2676                 else
2677                         limit = 0;
2678
2679                 if (bank->size > limit) {
2680                         bank->size = limit;
2681                         LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
2682                                 k_bank->bank_number, limit);
2683                 }
2684
2685                 size_k = bank->size / 1024;
2686                 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
2687                          k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2688
2689         } else {
2690                 LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
2691                                 k_bank->bank_number, num_blocks);
2692                 return ERROR_FLASH_BANK_INVALID;
2693         }
2694
2695         fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2696         fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
2697         fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
2698
2699         if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
2700                 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
2701                                 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
2702
2703         if (fcfg2_pflsh) {
2704                 if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
2705                         LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
2706                                 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2707         } else {
2708                 if (k_bank->bank_number == first_nvm_bank
2709                                 && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
2710                         LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
2711                                 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2712         }
2713
2714         if (bank->sectors) {
2715                 free(bank->sectors);
2716                 bank->sectors = NULL;
2717         }
2718         if (bank->prot_blocks) {
2719                 free(bank->prot_blocks);
2720                 bank->prot_blocks = NULL;
2721         }
2722
2723         if (k_bank->sector_size == 0) {
2724                 LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
2725                 return ERROR_FLASH_BANK_INVALID;
2726         }
2727
2728         bank->num_sectors = bank->size / k_bank->sector_size;
2729
2730         if (bank->num_sectors > 0) {
2731                 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
2732                 bank->sectors = alloc_block_array(0, k_bank->sector_size, bank->num_sectors);
2733                 if (!bank->sectors)
2734                         return ERROR_FAIL;
2735
2736                 bank->prot_blocks = alloc_block_array(0, k_bank->protection_size, bank->num_prot_blocks);
2737                 if (!bank->prot_blocks)
2738                         return ERROR_FAIL;
2739
2740         } else {
2741                 bank->num_prot_blocks = 0;
2742         }
2743
2744         k_bank->probed = true;
2745
2746         return ERROR_OK;
2747 }
2748
2749 static int kinetis_auto_probe(struct flash_bank *bank)
2750 {
2751         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2752
2753         if (k_bank && k_bank->probed)
2754                 return ERROR_OK;
2755
2756         return kinetis_probe(bank);
2757 }
2758
2759 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
2760 {
2761         const char *bank_class_names[] = {
2762                 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
2763         };
2764
2765         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2766         struct kinetis_chip *k_chip = k_bank->k_chip;
2767         uint32_t size_k = bank->size / 1024;
2768
2769         snprintf(buf, buf_size,
2770                 "%s %s: %" PRIu32 "k %s bank %s at 0x%08" PRIx32,
2771                 bank->driver->name, k_chip->name,
2772                 size_k, bank_class_names[k_bank->flash_class],
2773                 bank->name, bank->base);
2774
2775         return ERROR_OK;
2776 }
2777
2778 static int kinetis_blank_check(struct flash_bank *bank)
2779 {
2780         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2781         struct kinetis_chip *k_chip = k_bank->k_chip;
2782         int result;
2783
2784         /* suprisingly blank check does not work in VLPR and HSRUN modes */
2785         result = kinetis_check_run_mode(k_chip);
2786         if (result != ERROR_OK)
2787                 return result;
2788
2789         /* reset error flags */
2790         result = kinetis_ftfx_prepare(bank->target);
2791         if (result != ERROR_OK)
2792                 return result;
2793
2794         if (k_bank->flash_class == FC_PFLASH || k_bank->flash_class == FC_FLEX_NVM) {
2795                 bool block_dirty = true;
2796                 bool use_block_cmd = !(k_chip->flash_support & FS_NO_CMD_BLOCKSTAT);
2797                 uint8_t ftfx_fstat;
2798
2799                 if (use_block_cmd && k_bank->flash_class == FC_FLEX_NVM) {
2800                         uint8_t fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2801                         /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
2802                         if (fcfg1_depart != 0xf && fcfg1_depart != 0)
2803                                 use_block_cmd = false;
2804                 }
2805
2806                 if (use_block_cmd) {
2807                         /* check if whole bank is blank */
2808                         result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
2809                                                          0, 0, 0, 0,  0, 0, 0, 0, &ftfx_fstat);
2810
2811                         if (result != ERROR_OK)
2812                                 kinetis_ftfx_clear_error(bank->target);
2813                         else if ((ftfx_fstat & 0x01) == 0)
2814                                 block_dirty = false;
2815                 }
2816
2817                 if (block_dirty) {
2818                         /* the whole bank is not erased, check sector-by-sector */
2819                         int i;
2820                         for (i = 0; i < bank->num_sectors; i++) {
2821                                 /* normal margin */
2822                                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
2823                                                 k_bank->prog_base + bank->sectors[i].offset,
2824                                                 1, 0, 0, 0,  0, 0, 0, 0, &ftfx_fstat);
2825
2826                                 if (result == ERROR_OK) {
2827                                         bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
2828                                 } else {
2829                                         LOG_DEBUG("Ignoring errored PFlash sector blank-check");
2830                                         kinetis_ftfx_clear_error(bank->target);
2831                                         bank->sectors[i].is_erased = -1;
2832                                 }
2833                         }
2834                 } else {
2835                         /* the whole bank is erased, update all sectors */
2836                         int i;
2837                         for (i = 0; i < bank->num_sectors; i++)
2838                                 bank->sectors[i].is_erased = 1;
2839                 }
2840         } else {
2841                 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
2842                 return ERROR_FLASH_OPERATION_FAILED;
2843         }
2844
2845         return ERROR_OK;
2846 }
2847
2848
2849 COMMAND_HANDLER(kinetis_nvm_partition)
2850 {
2851         int result;
2852         unsigned bank_idx;
2853         unsigned num_blocks, first_nvm_bank;
2854         unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
2855         enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
2856         bool enable;
2857         uint8_t load_flex_ram = 1;
2858         uint8_t ee_size_code = 0x3f;
2859         uint8_t flex_nvm_partition_code = 0;
2860         uint8_t ee_split = 3;
2861         struct target *target = get_current_target(CMD_CTX);
2862         struct kinetis_chip *k_chip;
2863         uint32_t sim_fcfg1;
2864
2865         k_chip = kinetis_get_chip(target);
2866
2867         if (CMD_ARGC >= 2) {
2868                 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
2869                         sz_type = DF_SIZE;
2870                 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
2871                         sz_type = EEBKP_SIZE;
2872
2873                 par = strtoul(CMD_ARGV[1], NULL, 10);
2874                 while (par >> (log2 + 3))
2875                         log2++;
2876         }
2877         switch (sz_type) {
2878         case SHOW_INFO:
2879                 if (k_chip == NULL) {
2880                         LOG_ERROR("Chip not probed.");
2881                         return ERROR_FAIL;
2882                 }
2883                 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
2884                 if (result != ERROR_OK)
2885                         return result;
2886
2887                 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
2888                 switch (flex_nvm_partition_code) {
2889                 case 0:
2890                         command_print(CMD_CTX, "No EEPROM backup, data flash only");
2891                         break;
2892                 case 1:
2893                 case 2:
2894                 case 3:
2895                 case 4:
2896                 case 5:
2897                 case 6:
2898                         command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
2899                         break;
2900                 case 8:
2901                         command_print(CMD_CTX, "No data flash, EEPROM backup only");
2902                         break;
2903                 case 0x9:
2904                 case 0xA:
2905                 case 0xB:
2906                 case 0xC:
2907                 case 0xD:
2908                 case 0xE:
2909                         command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
2910                         break;
2911                 case 0xf:
2912                         command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
2913                         break;
2914                 default:
2915                         command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
2916                 }
2917                 return ERROR_OK;
2918
2919         case DF_SIZE:
2920                 flex_nvm_partition_code = 0x8 | log2;
2921                 break;
2922
2923         case EEBKP_SIZE:
2924                 flex_nvm_partition_code = log2;
2925                 break;
2926         }
2927
2928         if (CMD_ARGC == 3)
2929                 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
2930         else if (CMD_ARGC >= 4) {
2931                 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
2932                 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
2933         }
2934
2935         enable = ee1 + ee2 > 0;
2936         if (enable) {
2937                 for (log2 = 2; ; log2++) {
2938                         if (ee1 + ee2 == (16u << 10) >> log2)
2939                                 break;
2940                         if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
2941                                 LOG_ERROR("Unsupported EEPROM size");
2942                                 return ERROR_FLASH_OPERATION_FAILED;
2943                         }
2944                 }
2945
2946                 if (ee1 * 3 == ee2)
2947                         ee_split = 1;
2948                 else if (ee1 * 7 == ee2)
2949                         ee_split = 0;
2950                 else if (ee1 != ee2) {
2951                         LOG_ERROR("Unsupported EEPROM sizes ratio");
2952                         return ERROR_FLASH_OPERATION_FAILED;
2953                 }
2954
2955                 ee_size_code = log2 | ee_split << 4;
2956         }
2957
2958         if (CMD_ARGC >= 5)
2959                 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
2960         if (enable)
2961                 load_flex_ram = 0;
2962
2963         LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
2964                  flex_nvm_partition_code, ee_size_code);
2965
2966         result = kinetis_check_run_mode(k_chip);
2967         if (result != ERROR_OK)
2968                 return result;
2969
2970         /* reset error flags */
2971         result = kinetis_ftfx_prepare(target);
2972         if (result != ERROR_OK)
2973                 return result;
2974
2975         result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
2976                                       ee_size_code, flex_nvm_partition_code, 0, 0,
2977                                       0, 0, 0, 0,  NULL);
2978         if (result != ERROR_OK)
2979                 return result;
2980
2981         command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
2982
2983         if (k_chip) {
2984                 first_nvm_bank = k_chip->num_pflash_blocks;
2985                 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2986                 for (bank_idx = first_nvm_bank; bank_idx < num_blocks; bank_idx++)
2987                         k_chip->banks[bank_idx].probed = false; /* re-probe before next use */
2988                 k_chip->probed = false;
2989         }
2990
2991         command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
2992         return ERROR_OK;
2993 }
2994
2995 COMMAND_HANDLER(kinetis_fcf_source_handler)
2996 {
2997         if (CMD_ARGC > 1)
2998                 return ERROR_COMMAND_SYNTAX_ERROR;
2999
3000         if (CMD_ARGC == 1) {
3001                 if (strcmp(CMD_ARGV[0], "write") == 0)
3002                         allow_fcf_writes = true;
3003                 else if (strcmp(CMD_ARGV[0], "protection") == 0)
3004                         allow_fcf_writes = false;
3005                 else
3006                         return ERROR_COMMAND_SYNTAX_ERROR;
3007         }
3008
3009         if (allow_fcf_writes) {
3010                 command_print(CMD_CTX, "Arbitrary Flash Configuration Field writes enabled.");
3011                 command_print(CMD_CTX, "Protection info writes to FCF disabled.");
3012                 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
3013         } else {
3014                 command_print(CMD_CTX, "Protection info writes to Flash Configuration Field enabled.");
3015                 command_print(CMD_CTX, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
3016         }
3017
3018         return ERROR_OK;
3019 }
3020
3021 COMMAND_HANDLER(kinetis_fopt_handler)
3022 {
3023         if (CMD_ARGC > 1)
3024                 return ERROR_COMMAND_SYNTAX_ERROR;
3025
3026         if (CMD_ARGC == 1) {
3027                 fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
3028                 fcf_fopt_configured = true;
3029         } else {
3030                 command_print(CMD_CTX, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
3031         }
3032
3033         return ERROR_OK;
3034 }
3035
3036 COMMAND_HANDLER(kinetis_create_banks_handler)
3037 {
3038         if (CMD_ARGC > 0)
3039                 return ERROR_COMMAND_SYNTAX_ERROR;
3040
3041         create_banks = true;
3042
3043         return ERROR_OK;
3044 }
3045
3046
3047 static const struct command_registration kinetis_security_command_handlers[] = {
3048         {
3049                 .name = "check_security",
3050                 .mode = COMMAND_EXEC,
3051                 .help = "Check status of device security lock",
3052                 .usage = "",
3053                 .handler = kinetis_check_flash_security_status,
3054         },
3055         {
3056                 .name = "halt",
3057                 .mode = COMMAND_EXEC,
3058                 .help = "Issue a halt via the MDM-AP",
3059                 .usage = "",
3060                 .handler = kinetis_mdm_halt,
3061         },
3062         {
3063                 .name = "mass_erase",
3064                 .mode = COMMAND_EXEC,
3065                 .help = "Issue a complete flash erase via the MDM-AP",
3066                 .usage = "",
3067                 .handler = kinetis_mdm_mass_erase,
3068         },
3069         {       .name = "reset",
3070                 .mode = COMMAND_EXEC,
3071                 .help = "Issue a reset via the MDM-AP",
3072                 .usage = "",
3073                 .handler = kinetis_mdm_reset,
3074         },
3075         COMMAND_REGISTRATION_DONE
3076 };
3077
3078 static const struct command_registration kinetis_exec_command_handlers[] = {
3079         {
3080                 .name = "mdm",
3081                 .mode = COMMAND_ANY,
3082                 .help = "MDM-AP command group",
3083                 .usage = "",
3084                 .chain = kinetis_security_command_handlers,
3085         },
3086         {
3087                 .name = "disable_wdog",
3088                 .mode = COMMAND_EXEC,
3089                 .help = "Disable the watchdog timer",
3090                 .usage = "",
3091                 .handler = kinetis_disable_wdog_handler,
3092         },
3093         {
3094                 .name = "nvm_partition",
3095                 .mode = COMMAND_EXEC,
3096                 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
3097                         " set two EEPROM sizes in bytes and FlexRAM loading during reset",
3098                 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
3099                 .handler = kinetis_nvm_partition,
3100         },
3101         {
3102                 .name = "fcf_source",
3103                 .mode = COMMAND_EXEC,
3104                 .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
3105                         " Mode 'protection' is safe from unwanted locking of the device.",
3106                 .usage = "['protection'|'write']",
3107                 .handler = kinetis_fcf_source_handler,
3108         },
3109         {
3110                 .name = "fopt",
3111                 .mode = COMMAND_EXEC,
3112                 .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
3113                 .usage = "[num]",
3114                 .handler = kinetis_fopt_handler,
3115         },
3116         {
3117                 .name = "create_banks",
3118                 .mode = COMMAND_CONFIG,
3119                 .help = "Driver creates additional banks if device with two/four flash blocks is probed",
3120                 .handler = kinetis_create_banks_handler,
3121         },
3122         COMMAND_REGISTRATION_DONE
3123 };
3124
3125 static const struct command_registration kinetis_command_handler[] = {
3126         {
3127                 .name = "kinetis",
3128                 .mode = COMMAND_ANY,
3129                 .help = "Kinetis flash controller commands",
3130                 .usage = "",
3131                 .chain = kinetis_exec_command_handlers,
3132         },
3133         COMMAND_REGISTRATION_DONE
3134 };
3135
3136
3137
3138 struct flash_driver kinetis_flash = {
3139         .name = "kinetis",
3140         .commands = kinetis_command_handler,
3141         .flash_bank_command = kinetis_flash_bank_command,
3142         .erase = kinetis_erase,
3143         .protect = kinetis_protect,
3144         .write = kinetis_write,
3145         .read = default_flash_read,
3146         .probe = kinetis_probe,
3147         .auto_probe = kinetis_auto_probe,
3148         .erase_check = kinetis_blank_check,
3149         .protect_check = kinetis_protect_check,
3150         .info = kinetis_info,
3151         .free_driver_priv = kinetis_free_driver_priv,
3152 };