1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
31 NRF5_FLASH_BASE = 0x00000000,
34 enum nrf5_ficr_registers {
35 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
37 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
39 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
40 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
41 NRF5_FICR_CLENR0 = NRF5_FICR_REG(0x028),
42 NRF5_FICR_PPFC = NRF5_FICR_REG(0x02C),
43 NRF5_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
44 NRF5_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
45 NRF5_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
46 NRF5_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
47 NRF5_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
48 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
49 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
50 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
51 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
52 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
53 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
54 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
55 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
56 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
57 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
58 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
59 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
60 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
61 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
62 NRF5_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
63 NRF5_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
64 NRF5_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
65 NRF5_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
66 NRF5_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
67 NRF5_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
68 NRF5_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
69 NRF5_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
70 NRF5_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
71 NRF5_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
72 NRF5_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
75 enum nrf5_uicr_registers {
76 NRF5_UICR_BASE = 0x10001000, /* User Information
77 * Configuration Regsters */
79 NRF5_UICR_SIZE = 0x100,
81 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
83 NRF5_UICR_CLENR0 = NRF5_UICR_REG(0x000),
84 NRF5_UICR_RBPCONF = NRF5_UICR_REG(0x004),
85 NRF5_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
86 NRF5_UICR_FWID = NRF5_UICR_REG(0x010),
89 enum nrf5_nvmc_registers {
90 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
91 * Controller Regsters */
93 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
95 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
96 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
97 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
98 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
99 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
102 enum nrf5_nvmc_config_bits {
103 NRF5_NVMC_CONFIG_REN = 0x00,
104 NRF5_NVMC_CONFIG_WEN = 0x01,
105 NRF5_NVMC_CONFIG_EEN = 0x02,
110 uint32_t code_page_size;
114 int (*write) (struct flash_bank *bank,
115 struct nrf5_info *chip,
116 const uint8_t *buffer, uint32_t offset, uint32_t count);
118 struct target *target;
121 struct nrf5_device_spec {
125 const char *build_code;
126 unsigned int flash_size_kb;
129 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
134 .build_code = bcode, \
135 .flash_size_kb = (fsize), \
138 /* The known devices table below is derived from the "nRF51 Series
139 * Compatibility Matrix" document, which can be found by searching for
140 * ATTN-51 on the Nordic Semi website:
142 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
144 * Up to date with Matrix v2.0, plus some additional HWIDs.
146 * The additional HWIDs apply where the build code in the matrix is
147 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
148 * for x==0, x!=0 means different (unspecified) HWIDs.
150 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
151 /* nRF51822 Devices (IC rev 1). */
152 NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
153 NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
154 NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
155 NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
156 NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
158 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
159 with built-in jlink seem to use engineering samples not listed
160 in the nRF51 Series Compatibility Matrix V1.0. */
161 NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
163 /* nRF51822 Devices (IC rev 2). */
164 NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
165 NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
166 NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
167 NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
168 NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
169 NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
170 NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
171 NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
172 NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
174 /* nRF51822 Devices (IC rev 3). */
175 NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
176 NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
177 NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
178 NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
179 NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
180 NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
181 NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
182 NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
183 NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
185 /* nRF51422 Devices (IC rev 1). */
186 NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
187 NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
188 NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
190 /* nRF51422 Devices (IC rev 2). */
191 NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
192 NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
193 NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
194 NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
196 /* nRF51422 Devices (IC rev 3). */
197 NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
198 NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
199 NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
200 NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
201 NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
202 NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
203 NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
205 /* nRF52832 Devices */
206 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
207 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
210 static int nrf5_bank_is_probed(struct flash_bank *bank)
212 struct nrf5_info *chip = bank->driver_priv;
214 assert(chip != NULL);
216 return chip->bank[bank->bank_number].probed;
218 static int nrf5_probe(struct flash_bank *bank);
220 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
222 if (bank->target->state != TARGET_HALTED) {
223 LOG_ERROR("Target not halted");
224 return ERROR_TARGET_NOT_HALTED;
227 *chip = bank->driver_priv;
229 int probed = nrf5_bank_is_probed(bank);
233 return nrf5_probe(bank);
238 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
245 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
246 if (res != ERROR_OK) {
247 LOG_ERROR("Couldn't read NVMC_READY register");
251 if (ready == 0x00000001)
257 LOG_DEBUG("Timed out waiting for NVMC_READY");
258 return ERROR_FLASH_BUSY;
261 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
264 res = target_write_u32(chip->target,
266 NRF5_NVMC_CONFIG_EEN);
268 if (res != ERROR_OK) {
269 LOG_ERROR("Failed to enable erase operation");
274 According to NVMC examples in Nordic SDK busy status must be
275 checked after writing to NVMC_CONFIG
277 res = nrf5_wait_for_nvmc(chip);
279 LOG_ERROR("Erase enable did not complete");
284 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
287 res = target_write_u32(chip->target,
289 NRF5_NVMC_CONFIG_WEN);
291 if (res != ERROR_OK) {
292 LOG_ERROR("Failed to enable write operation");
297 According to NVMC examples in Nordic SDK busy status must be
298 checked after writing to NVMC_CONFIG
300 res = nrf5_wait_for_nvmc(chip);
302 LOG_ERROR("Write enable did not complete");
307 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
310 res = target_write_u32(chip->target,
312 NRF5_NVMC_CONFIG_REN);
314 if (res != ERROR_OK) {
315 LOG_ERROR("Failed to enable read-only operation");
319 According to NVMC examples in Nordic SDK busy status must be
320 checked after writing to NVMC_CONFIG
322 res = nrf5_wait_for_nvmc(chip);
324 LOG_ERROR("Read only enable did not complete");
329 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
330 uint32_t erase_register, uint32_t erase_value)
334 res = nrf5_nvmc_erase_enable(chip);
338 res = target_write_u32(chip->target,
344 res = nrf5_wait_for_nvmc(chip);
348 return nrf5_nvmc_read_only(chip);
351 nrf5_nvmc_read_only(chip);
353 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
354 erase_register, erase_value);
358 static int nrf5_protect_check(struct flash_bank *bank)
363 /* UICR cannot be write protected so just return early */
364 if (bank->base == NRF5_UICR_BASE)
367 struct nrf5_info *chip = bank->driver_priv;
369 assert(chip != NULL);
371 res = target_read_u32(chip->target, NRF5_FICR_CLENR0,
373 if (res != ERROR_OK) {
374 LOG_ERROR("Couldn't read code region 0 size[FICR]");
378 if (clenr0 == 0xFFFFFFFF) {
379 res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
381 if (res != ERROR_OK) {
382 LOG_ERROR("Couldn't read code region 0 size[UICR]");
387 for (int i = 0; i < bank->num_sectors; i++)
388 bank->sectors[i].is_protected =
389 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
394 static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
397 uint32_t clenr0, ppfc;
398 struct nrf5_info *chip;
400 /* UICR cannot be write protected so just bail out early */
401 if (bank->base == NRF5_UICR_BASE)
404 res = nrf5_get_probed_chip_if_halted(bank, &chip);
409 LOG_ERROR("Code region 0 must start at the begining of the bank");
413 res = target_read_u32(chip->target, NRF5_FICR_PPFC,
415 if (res != ERROR_OK) {
416 LOG_ERROR("Couldn't read PPFC register");
420 if ((ppfc & 0xFF) == 0x00) {
421 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
425 res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
427 if (res != ERROR_OK) {
428 LOG_ERROR("Couldn't read code region 0 size[UICR]");
432 if (clenr0 == 0xFFFFFFFF) {
433 res = target_write_u32(chip->target, NRF5_UICR_CLENR0,
435 if (res != ERROR_OK) {
436 LOG_ERROR("Couldn't write code region 0 size[UICR]");
441 LOG_ERROR("You need to perform chip erase before changing the protection settings");
444 nrf5_protect_check(bank);
449 static int nrf5_probe(struct flash_bank *bank)
453 struct nrf5_info *chip = bank->driver_priv;
455 res = target_read_u32(chip->target, NRF5_FICR_CONFIGID, &hwid);
456 if (res != ERROR_OK) {
457 LOG_ERROR("Couldn't read CONFIGID register");
461 hwid &= 0xFFFF; /* HWID is stored in the lower two
462 * bytes of the CONFIGID register */
464 const struct nrf5_device_spec *spec = NULL;
465 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
466 if (hwid == nrf5_known_devices_table[i].hwid) {
467 spec = &nrf5_known_devices_table[i];
472 if (!chip->bank[0].probed && !chip->bank[1].probed) {
474 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
475 spec->part, spec->variant, spec->build_code,
476 spec->flash_size_kb);
478 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
481 if (bank->base == NRF5_FLASH_BASE) {
482 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
483 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
484 &chip->code_page_size);
485 if (res != ERROR_OK) {
486 LOG_ERROR("Couldn't read code page size");
490 /* Note the register name is misleading,
491 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
492 uint32_t num_sectors;
493 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
494 if (res != ERROR_OK) {
495 LOG_ERROR("Couldn't read code memory size");
499 bank->num_sectors = num_sectors;
500 bank->size = num_sectors * chip->code_page_size;
502 if (spec && bank->size / 1024 != spec->flash_size_kb)
503 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
505 bank->sectors = calloc(bank->num_sectors,
506 sizeof((bank->sectors)[0]));
508 return ERROR_FLASH_BANK_NOT_PROBED;
510 /* Fill out the sector information: all NRF5 sectors are the same size and
511 * there is always a fixed number of them. */
512 for (int i = 0; i < bank->num_sectors; i++) {
513 bank->sectors[i].size = chip->code_page_size;
514 bank->sectors[i].offset = i * chip->code_page_size;
516 /* mark as unknown */
517 bank->sectors[i].is_erased = -1;
518 bank->sectors[i].is_protected = -1;
521 nrf5_protect_check(bank);
523 chip->bank[0].probed = true;
525 bank->size = NRF5_UICR_SIZE;
526 bank->num_sectors = 1;
527 bank->sectors = calloc(bank->num_sectors,
528 sizeof((bank->sectors)[0]));
530 return ERROR_FLASH_BANK_NOT_PROBED;
532 bank->sectors[0].size = bank->size;
533 bank->sectors[0].offset = 0;
535 bank->sectors[0].is_erased = 0;
536 bank->sectors[0].is_protected = 0;
538 chip->bank[1].probed = true;
544 static int nrf5_auto_probe(struct flash_bank *bank)
546 int probed = nrf5_bank_is_probed(bank);
553 return nrf5_probe(bank);
556 static int nrf5_erase_all(struct nrf5_info *chip)
558 LOG_DEBUG("Erasing all non-volatile memory");
559 return nrf5_nvmc_generic_erase(chip,
564 static int nrf5_erase_page(struct flash_bank *bank,
565 struct nrf5_info *chip,
566 struct flash_sector *sector)
570 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
571 if (sector->is_protected) {
572 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
576 if (bank->base == NRF5_UICR_BASE) {
578 res = target_read_u32(chip->target, NRF5_FICR_PPFC,
580 if (res != ERROR_OK) {
581 LOG_ERROR("Couldn't read PPFC register");
585 if ((ppfc & 0xFF) == 0xFF) {
586 /* We can't erase the UICR. Double-check to
587 see if it's already erased before complaining. */
588 default_flash_blank_check(bank);
589 if (sector->is_erased == 1)
592 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
596 res = nrf5_nvmc_generic_erase(chip,
602 res = nrf5_nvmc_generic_erase(chip,
610 static const uint8_t nrf5_flash_write_code[] = {
611 /* See contrib/loaders/flash/cortex-m0.S */
613 0x0d, 0x68, /* ldr r5, [r1, #0] */
614 0x00, 0x2d, /* cmp r5, #0 */
615 0x0b, 0xd0, /* beq.n 1e <exit> */
616 0x4c, 0x68, /* ldr r4, [r1, #4] */
617 0xac, 0x42, /* cmp r4, r5 */
618 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
619 0x20, 0xcc, /* ldmia r4!, {r5} */
620 0x20, 0xc3, /* stmia r3!, {r5} */
621 0x94, 0x42, /* cmp r4, r2 */
622 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
623 0x0c, 0x46, /* mov r4, r1 */
624 0x08, 0x34, /* adds r4, #8 */
626 0x4c, 0x60, /* str r4, [r1, #4] */
627 0x04, 0x38, /* subs r0, #4 */
628 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
630 0x00, 0xbe /* bkpt 0x0000 */
634 /* Start a low level flash write for the specified region */
635 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
637 struct target *target = chip->target;
638 uint32_t buffer_size = 8192;
639 struct working_area *write_algorithm;
640 struct working_area *source;
641 uint32_t address = NRF5_FLASH_BASE + offset;
642 struct reg_param reg_params[4];
643 struct armv7m_algorithm armv7m_info;
644 int retval = ERROR_OK;
647 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
648 assert(bytes % 4 == 0);
650 /* allocate working area with flash programming code */
651 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
652 &write_algorithm) != ERROR_OK) {
653 LOG_WARNING("no working area available, falling back to slow memory writes");
655 for (; bytes > 0; bytes -= 4) {
656 retval = target_write_memory(chip->target, offset, 4, 1, buffer);
657 if (retval != ERROR_OK)
660 retval = nrf5_wait_for_nvmc(chip);
661 if (retval != ERROR_OK)
671 LOG_WARNING("using fast async flash loader. This is currently supported");
672 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
673 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg/nrf52.cfg to disable it");
675 retval = target_write_buffer(target, write_algorithm->address,
676 sizeof(nrf5_flash_write_code),
677 nrf5_flash_write_code);
678 if (retval != ERROR_OK)
682 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
684 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
685 if (buffer_size <= 256) {
686 /* free working area, write algorithm already allocated */
687 target_free_working_area(target, write_algorithm);
689 LOG_WARNING("No large enough working area available, can't do block memory writes");
690 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
694 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
695 armv7m_info.core_mode = ARM_MODE_THREAD;
697 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
698 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer start */
699 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer end */
700 init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
702 buf_set_u32(reg_params[0].value, 0, 32, bytes);
703 buf_set_u32(reg_params[1].value, 0, 32, source->address);
704 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
705 buf_set_u32(reg_params[3].value, 0, 32, address);
707 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
710 source->address, source->size,
711 write_algorithm->address, 0,
714 target_free_working_area(target, source);
715 target_free_working_area(target, write_algorithm);
717 destroy_reg_param(®_params[0]);
718 destroy_reg_param(®_params[1]);
719 destroy_reg_param(®_params[2]);
720 destroy_reg_param(®_params[3]);
725 /* Check and erase flash sectors in specified range then start a low level page write.
726 start/end must be sector aligned.
728 static int nrf5_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
730 int res = ERROR_FAIL;
731 struct nrf5_info *chip = bank->driver_priv;
733 assert(start % chip->code_page_size == 0);
734 assert(end % chip->code_page_size == 0);
736 res = nrf5_nvmc_write_enable(chip);
740 res = nrf5_ll_flash_write(chip, start, buffer, (end - start));
744 return nrf5_nvmc_read_only(chip);
747 nrf5_nvmc_read_only(chip);
748 LOG_ERROR("Failed to write to nrf5 flash");
752 static int nrf5_erase(struct flash_bank *bank, int first, int last)
755 struct nrf5_info *chip;
757 res = nrf5_get_probed_chip_if_halted(bank, &chip);
761 /* For each sector to be erased */
762 for (int s = first; s <= last && res == ERROR_OK; s++)
763 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
768 static int nrf5_code_flash_write(struct flash_bank *bank,
769 struct nrf5_info *chip,
770 const uint8_t *buffer, uint32_t offset, uint32_t count)
774 /* Need to perform reads to fill any gaps we need to preserve in the first page,
775 before the start of buffer, or in the last page, after the end of buffer */
776 uint32_t first_page = offset/chip->code_page_size;
777 uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
779 uint32_t first_page_offset = first_page * chip->code_page_size;
780 uint32_t last_page_offset = last_page * chip->code_page_size;
782 LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
783 offset, offset+count, first_page_offset, last_page_offset);
785 uint32_t page_cnt = last_page - first_page;
786 uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
788 /* Fill in any space between start of first page and start of buffer */
789 uint32_t pre = offset - first_page_offset;
791 res = target_read_memory(bank->target,
800 /* Fill in main contents of buffer */
801 memcpy(buffer_to_flash+pre, buffer, count);
803 /* Fill in any space between end of buffer and end of last page */
804 uint32_t post = last_page_offset - (offset+count);
806 /* Retrieve the full row contents from Flash */
807 res = target_read_memory(bank->target,
811 buffer_to_flash+pre+count);
816 return nrf5_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
819 static int nrf5_uicr_flash_write(struct flash_bank *bank,
820 struct nrf5_info *chip,
821 const uint8_t *buffer, uint32_t offset, uint32_t count)
824 uint8_t uicr[NRF5_UICR_SIZE];
825 struct flash_sector *sector = &bank->sectors[0];
827 if ((offset + count) > NRF5_UICR_SIZE)
830 res = target_read_memory(bank->target,
839 res = nrf5_erase_page(bank, chip, sector);
843 res = nrf5_nvmc_write_enable(chip);
847 memcpy(&uicr[offset], buffer, count);
849 res = nrf5_ll_flash_write(chip, NRF5_UICR_BASE, uicr, NRF5_UICR_SIZE);
850 if (res != ERROR_OK) {
851 nrf5_nvmc_read_only(chip);
855 return nrf5_nvmc_read_only(chip);
859 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
860 uint32_t offset, uint32_t count)
863 struct nrf5_info *chip;
865 res = nrf5_get_probed_chip_if_halted(bank, &chip);
869 return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
873 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
875 static struct nrf5_info *chip;
877 switch (bank->base) {
878 case NRF5_FLASH_BASE:
879 bank->bank_number = 0;
882 bank->bank_number = 1;
885 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
890 /* Create a new chip */
891 chip = calloc(1, sizeof(*chip));
895 chip->target = bank->target;
898 switch (bank->base) {
899 case NRF5_FLASH_BASE:
900 chip->bank[bank->bank_number].write = nrf5_code_flash_write;
903 chip->bank[bank->bank_number].write = nrf5_uicr_flash_write;
907 chip->bank[bank->bank_number].probed = false;
908 bank->driver_priv = chip;
913 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
916 struct flash_bank *bank = NULL;
917 struct target *target = get_current_target(CMD_CTX);
919 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
923 assert(bank != NULL);
925 struct nrf5_info *chip;
927 res = nrf5_get_probed_chip_if_halted(bank, &chip);
933 res = target_read_u32(target, NRF5_FICR_PPFC,
935 if (res != ERROR_OK) {
936 LOG_ERROR("Couldn't read PPFC register");
940 if ((ppfc & 0xFF) == 0x00) {
941 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
942 "mass erase command won't work.");
946 res = nrf5_erase_all(chip);
947 if (res != ERROR_OK) {
948 LOG_ERROR("Failed to erase the chip");
949 nrf5_protect_check(bank);
953 res = nrf5_protect_check(bank);
954 if (res != ERROR_OK) {
955 LOG_ERROR("Failed to check chip's write protection");
959 res = get_flash_bank_by_addr(target, NRF5_UICR_BASE, true, &bank);
966 static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
970 struct nrf5_info *chip;
972 res = nrf5_get_probed_chip_if_halted(bank, &chip);
977 const uint32_t address;
980 { .address = NRF5_FICR_CODEPAGESIZE },
981 { .address = NRF5_FICR_CODESIZE },
982 { .address = NRF5_FICR_CLENR0 },
983 { .address = NRF5_FICR_PPFC },
984 { .address = NRF5_FICR_NUMRAMBLOCK },
985 { .address = NRF5_FICR_SIZERAMBLOCK0 },
986 { .address = NRF5_FICR_SIZERAMBLOCK1 },
987 { .address = NRF5_FICR_SIZERAMBLOCK2 },
988 { .address = NRF5_FICR_SIZERAMBLOCK3 },
989 { .address = NRF5_FICR_CONFIGID },
990 { .address = NRF5_FICR_DEVICEID0 },
991 { .address = NRF5_FICR_DEVICEID1 },
992 { .address = NRF5_FICR_ER0 },
993 { .address = NRF5_FICR_ER1 },
994 { .address = NRF5_FICR_ER2 },
995 { .address = NRF5_FICR_ER3 },
996 { .address = NRF5_FICR_IR0 },
997 { .address = NRF5_FICR_IR1 },
998 { .address = NRF5_FICR_IR2 },
999 { .address = NRF5_FICR_IR3 },
1000 { .address = NRF5_FICR_DEVICEADDRTYPE },
1001 { .address = NRF5_FICR_DEVICEADDR0 },
1002 { .address = NRF5_FICR_DEVICEADDR1 },
1003 { .address = NRF5_FICR_OVERRIDEN },
1004 { .address = NRF5_FICR_NRF_1MBIT0 },
1005 { .address = NRF5_FICR_NRF_1MBIT1 },
1006 { .address = NRF5_FICR_NRF_1MBIT2 },
1007 { .address = NRF5_FICR_NRF_1MBIT3 },
1008 { .address = NRF5_FICR_NRF_1MBIT4 },
1009 { .address = NRF5_FICR_BLE_1MBIT0 },
1010 { .address = NRF5_FICR_BLE_1MBIT1 },
1011 { .address = NRF5_FICR_BLE_1MBIT2 },
1012 { .address = NRF5_FICR_BLE_1MBIT3 },
1013 { .address = NRF5_FICR_BLE_1MBIT4 },
1015 { .address = NRF5_UICR_CLENR0, },
1016 { .address = NRF5_UICR_RBPCONF },
1017 { .address = NRF5_UICR_XTALFREQ },
1018 { .address = NRF5_UICR_FWID },
1021 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1022 res = target_read_u32(chip->target, ficr[i].address,
1024 if (res != ERROR_OK) {
1025 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1030 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1031 res = target_read_u32(chip->target, uicr[i].address,
1033 if (res != ERROR_OK) {
1034 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1039 snprintf(buf, buf_size,
1040 "\n[factory information control block]\n\n"
1041 "code page size: %"PRIu32"B\n"
1042 "code memory size: %"PRIu32"kB\n"
1043 "code region 0 size: %"PRIu32"kB\n"
1044 "pre-programmed code: %s\n"
1045 "number of ram blocks: %"PRIu32"\n"
1046 "ram block 0 size: %"PRIu32"B\n"
1047 "ram block 1 size: %"PRIu32"B\n"
1048 "ram block 2 size: %"PRIu32"B\n"
1049 "ram block 3 size: %"PRIu32 "B\n"
1050 "config id: %" PRIx32 "\n"
1051 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1052 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1053 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1054 "device address type: 0x%"PRIx32"\n"
1055 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1056 "override enable: %"PRIx32"\n"
1057 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1058 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1059 "\n[user information control block]\n\n"
1060 "code region 0 size: %"PRIu32"kB\n"
1061 "read back protection configuration: %"PRIx32"\n"
1062 "reset value for XTALFREQ: %"PRIx32"\n"
1063 "firmware id: 0x%04"PRIx32,
1065 (ficr[1].value * ficr[0].value) / 1024,
1066 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1067 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1070 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1071 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1072 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1074 ficr[10].value, ficr[11].value,
1075 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1076 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1078 ficr[21].value, ficr[22].value,
1080 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1081 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1082 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1083 uicr[1].value & 0xFFFF,
1084 uicr[2].value & 0xFF,
1085 uicr[3].value & 0xFFFF);
1090 static const struct command_registration nrf5_exec_command_handlers[] = {
1092 .name = "mass_erase",
1093 .handler = nrf5_handle_mass_erase_command,
1094 .mode = COMMAND_EXEC,
1095 .help = "Erase all flash contents of the chip.",
1097 COMMAND_REGISTRATION_DONE
1100 static const struct command_registration nrf5_command_handlers[] = {
1103 .mode = COMMAND_ANY,
1104 .help = "nrf5 flash command group",
1106 .chain = nrf5_exec_command_handlers,
1110 .mode = COMMAND_ANY,
1111 .help = "nrf51 flash command group",
1113 .chain = nrf5_exec_command_handlers,
1115 COMMAND_REGISTRATION_DONE
1118 struct flash_driver nrf5_flash = {
1120 .commands = nrf5_command_handlers,
1121 .flash_bank_command = nrf5_flash_bank_command,
1123 .erase = nrf5_erase,
1124 .protect = nrf5_protect,
1125 .write = nrf5_write,
1126 .read = default_flash_read,
1127 .probe = nrf5_probe,
1128 .auto_probe = nrf5_auto_probe,
1129 .erase_check = default_flash_blank_check,
1130 .protect_check = nrf5_protect_check,
1133 /* We need to retain the flash-driver name as well as the commands
1134 * for backwards compatability */
1135 struct flash_driver nrf51_flash = {
1137 .commands = nrf5_command_handlers,
1138 .flash_bank_command = nrf5_flash_bank_command,
1140 .erase = nrf5_erase,
1141 .protect = nrf5_protect,
1142 .write = nrf5_write,
1143 .read = default_flash_read,
1144 .probe = nrf5_probe,
1145 .auto_probe = nrf5_auto_probe,
1146 .erase_check = default_flash_blank_check,
1147 .protect_check = nrf5_protect_check,