1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
31 NRF5_FLASH_BASE = 0x00000000,
34 enum nrf5_ficr_registers {
35 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
37 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
39 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
40 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
41 NRF5_FICR_CLENR0 = NRF5_FICR_REG(0x028),
42 NRF5_FICR_PPFC = NRF5_FICR_REG(0x02C),
43 NRF5_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
44 NRF5_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
45 NRF5_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
46 NRF5_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
47 NRF5_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
48 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
49 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
50 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
51 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
52 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
53 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
54 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
55 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
56 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
57 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
58 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
59 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
60 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
61 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
62 NRF5_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
63 NRF5_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
64 NRF5_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
65 NRF5_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
66 NRF5_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
67 NRF5_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
68 NRF5_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
69 NRF5_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
70 NRF5_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
71 NRF5_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
72 NRF5_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
75 enum nrf5_uicr_registers {
76 NRF5_UICR_BASE = 0x10001000, /* User Information
77 * Configuration Regsters */
79 NRF5_UICR_SIZE = 0x100,
81 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
83 NRF5_UICR_CLENR0 = NRF5_UICR_REG(0x000),
84 NRF5_UICR_RBPCONF = NRF5_UICR_REG(0x004),
85 NRF5_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
86 NRF5_UICR_FWID = NRF5_UICR_REG(0x010),
89 enum nrf5_nvmc_registers {
90 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
91 * Controller Regsters */
93 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
95 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
96 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
97 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
98 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
99 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
102 enum nrf5_nvmc_config_bits {
103 NRF5_NVMC_CONFIG_REN = 0x00,
104 NRF5_NVMC_CONFIG_WEN = 0x01,
105 NRF5_NVMC_CONFIG_EEN = 0x02,
110 uint32_t code_page_size;
114 int (*write) (struct flash_bank *bank,
115 struct nrf5_info *chip,
116 const uint8_t *buffer, uint32_t offset, uint32_t count);
118 struct target *target;
121 struct nrf5_device_spec {
125 const char *build_code;
126 unsigned int flash_size_kb;
129 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
134 .build_code = bcode, \
135 .flash_size_kb = (fsize), \
138 /* The known devices table below is derived from the "nRF51 Series
139 * Compatibility Matrix" document, which can be found by searching for
140 * ATTN-51 on the Nordic Semi website:
142 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
144 * Up to date with Matrix v2.0, plus some additional HWIDs.
146 * The additional HWIDs apply where the build code in the matrix is
147 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
148 * for x==0, x!=0 means different (unspecified) HWIDs.
150 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
151 /* nRF51822 Devices (IC rev 1). */
152 NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
153 NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
154 NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
155 NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
156 NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
158 /* nRF51822 Devices (IC rev 2). */
159 NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
160 NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
161 NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
162 NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
163 NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
164 NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
165 NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
166 NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
167 NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
169 /* nRF51822 Devices (IC rev 3). */
170 NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
171 NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
172 NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
173 NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
174 NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
175 NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
176 NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
178 /* nRF51422 Devices (IC rev 1). */
179 NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
180 NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
181 NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
183 /* nRF51422 Devices (IC rev 2). */
184 NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
185 NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
186 NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
187 NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
189 /* nRF51422 Devices (IC rev 3). */
190 NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
191 NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
192 NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
193 NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
194 NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
195 NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
196 NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
198 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
199 with built-in jlink seem to use engineering samples not listed
200 in the nRF51 Series Compatibility Matrix V1.0. */
201 NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
204 static int nrf5_bank_is_probed(struct flash_bank *bank)
206 struct nrf5_info *chip = bank->driver_priv;
208 assert(chip != NULL);
210 return chip->bank[bank->bank_number].probed;
212 static int nrf5_probe(struct flash_bank *bank);
214 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
216 if (bank->target->state != TARGET_HALTED) {
217 LOG_ERROR("Target not halted");
218 return ERROR_TARGET_NOT_HALTED;
221 *chip = bank->driver_priv;
223 int probed = nrf5_bank_is_probed(bank);
227 return nrf5_probe(bank);
232 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
239 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
240 if (res != ERROR_OK) {
241 LOG_ERROR("Couldn't read NVMC_READY register");
245 if (ready == 0x00000001)
251 LOG_DEBUG("Timed out waiting for NVMC_READY");
252 return ERROR_FLASH_BUSY;
255 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
258 res = target_write_u32(chip->target,
260 NRF5_NVMC_CONFIG_EEN);
262 if (res != ERROR_OK) {
263 LOG_ERROR("Failed to enable erase operation");
268 According to NVMC examples in Nordic SDK busy status must be
269 checked after writing to NVMC_CONFIG
271 res = nrf5_wait_for_nvmc(chip);
273 LOG_ERROR("Erase enable did not complete");
278 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
281 res = target_write_u32(chip->target,
283 NRF5_NVMC_CONFIG_WEN);
285 if (res != ERROR_OK) {
286 LOG_ERROR("Failed to enable write operation");
291 According to NVMC examples in Nordic SDK busy status must be
292 checked after writing to NVMC_CONFIG
294 res = nrf5_wait_for_nvmc(chip);
296 LOG_ERROR("Write enable did not complete");
301 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
304 res = target_write_u32(chip->target,
306 NRF5_NVMC_CONFIG_REN);
308 if (res != ERROR_OK) {
309 LOG_ERROR("Failed to enable read-only operation");
313 According to NVMC examples in Nordic SDK busy status must be
314 checked after writing to NVMC_CONFIG
316 res = nrf5_wait_for_nvmc(chip);
318 LOG_ERROR("Read only enable did not complete");
323 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
324 uint32_t erase_register, uint32_t erase_value)
328 res = nrf5_nvmc_erase_enable(chip);
332 res = target_write_u32(chip->target,
338 res = nrf5_wait_for_nvmc(chip);
342 return nrf5_nvmc_read_only(chip);
345 nrf5_nvmc_read_only(chip);
347 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
348 erase_register, erase_value);
352 static int nrf5_protect_check(struct flash_bank *bank)
357 /* UICR cannot be write protected so just return early */
358 if (bank->base == NRF5_UICR_BASE)
361 struct nrf5_info *chip = bank->driver_priv;
363 assert(chip != NULL);
365 res = target_read_u32(chip->target, NRF5_FICR_CLENR0,
367 if (res != ERROR_OK) {
368 LOG_ERROR("Couldn't read code region 0 size[FICR]");
372 if (clenr0 == 0xFFFFFFFF) {
373 res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
375 if (res != ERROR_OK) {
376 LOG_ERROR("Couldn't read code region 0 size[UICR]");
381 for (int i = 0; i < bank->num_sectors; i++)
382 bank->sectors[i].is_protected =
383 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
388 static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
391 uint32_t clenr0, ppfc;
392 struct nrf5_info *chip;
394 /* UICR cannot be write protected so just bail out early */
395 if (bank->base == NRF5_UICR_BASE)
398 res = nrf5_get_probed_chip_if_halted(bank, &chip);
403 LOG_ERROR("Code region 0 must start at the begining of the bank");
407 res = target_read_u32(chip->target, NRF5_FICR_PPFC,
409 if (res != ERROR_OK) {
410 LOG_ERROR("Couldn't read PPFC register");
414 if ((ppfc & 0xFF) == 0x00) {
415 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
419 res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
421 if (res != ERROR_OK) {
422 LOG_ERROR("Couldn't read code region 0 size[UICR]");
426 if (clenr0 == 0xFFFFFFFF) {
427 res = target_write_u32(chip->target, NRF5_UICR_CLENR0,
429 if (res != ERROR_OK) {
430 LOG_ERROR("Couldn't write code region 0 size[UICR]");
435 LOG_ERROR("You need to perform chip erase before changing the protection settings");
438 nrf5_protect_check(bank);
443 static int nrf5_probe(struct flash_bank *bank)
447 struct nrf5_info *chip = bank->driver_priv;
449 res = target_read_u32(chip->target, NRF5_FICR_CONFIGID, &hwid);
450 if (res != ERROR_OK) {
451 LOG_ERROR("Couldn't read CONFIGID register");
455 hwid &= 0xFFFF; /* HWID is stored in the lower two
456 * bytes of the CONFIGID register */
458 const struct nrf5_device_spec *spec = NULL;
459 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
460 if (hwid == nrf5_known_devices_table[i].hwid) {
461 spec = &nrf5_known_devices_table[i];
466 if (!chip->bank[0].probed && !chip->bank[1].probed) {
468 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
469 spec->part, spec->variant, spec->build_code,
470 spec->flash_size_kb);
472 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
475 if (bank->base == NRF5_FLASH_BASE) {
476 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
477 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
478 &chip->code_page_size);
479 if (res != ERROR_OK) {
480 LOG_ERROR("Couldn't read code page size");
484 /* Note the register name is misleading,
485 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
486 uint32_t num_sectors;
487 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
488 if (res != ERROR_OK) {
489 LOG_ERROR("Couldn't read code memory size");
493 bank->num_sectors = num_sectors;
494 bank->size = num_sectors * chip->code_page_size;
496 if (spec && bank->size / 1024 != spec->flash_size_kb)
497 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
499 bank->sectors = calloc(bank->num_sectors,
500 sizeof((bank->sectors)[0]));
502 return ERROR_FLASH_BANK_NOT_PROBED;
504 /* Fill out the sector information: all NRF5 sectors are the same size and
505 * there is always a fixed number of them. */
506 for (int i = 0; i < bank->num_sectors; i++) {
507 bank->sectors[i].size = chip->code_page_size;
508 bank->sectors[i].offset = i * chip->code_page_size;
510 /* mark as unknown */
511 bank->sectors[i].is_erased = -1;
512 bank->sectors[i].is_protected = -1;
515 nrf5_protect_check(bank);
517 chip->bank[0].probed = true;
519 bank->size = NRF5_UICR_SIZE;
520 bank->num_sectors = 1;
521 bank->sectors = calloc(bank->num_sectors,
522 sizeof((bank->sectors)[0]));
524 return ERROR_FLASH_BANK_NOT_PROBED;
526 bank->sectors[0].size = bank->size;
527 bank->sectors[0].offset = 0;
529 /* mark as unknown */
530 bank->sectors[0].is_erased = 0;
531 bank->sectors[0].is_protected = 0;
533 chip->bank[1].probed = true;
539 static int nrf5_auto_probe(struct flash_bank *bank)
541 int probed = nrf5_bank_is_probed(bank);
548 return nrf5_probe(bank);
551 static struct flash_sector *nrf5_find_sector_by_address(struct flash_bank *bank, uint32_t address)
553 struct nrf5_info *chip = bank->driver_priv;
555 for (int i = 0; i < bank->num_sectors; i++)
556 if (bank->sectors[i].offset <= address &&
557 address < (bank->sectors[i].offset + chip->code_page_size))
558 return &bank->sectors[i];
562 static int nrf5_erase_all(struct nrf5_info *chip)
564 LOG_DEBUG("Erasing all non-volatile memory");
565 return nrf5_nvmc_generic_erase(chip,
570 static int nrf5_erase_page(struct flash_bank *bank,
571 struct nrf5_info *chip,
572 struct flash_sector *sector)
576 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
577 if (sector->is_protected) {
578 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
582 if (bank->base == NRF5_UICR_BASE) {
584 res = target_read_u32(chip->target, NRF5_FICR_PPFC,
586 if (res != ERROR_OK) {
587 LOG_ERROR("Couldn't read PPFC register");
591 if ((ppfc & 0xFF) == 0xFF) {
592 /* We can't erase the UICR. Double-check to
593 see if it's already erased before complaining. */
594 default_flash_blank_check(bank);
595 if (sector->is_erased == 1)
598 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
602 res = nrf5_nvmc_generic_erase(chip,
608 res = nrf5_nvmc_generic_erase(chip,
614 sector->is_erased = 1;
619 static const uint8_t nrf5_flash_write_code[] = {
620 /* See contrib/loaders/flash/cortex-m0.S */
622 0x0d, 0x68, /* ldr r5, [r1, #0] */
623 0x00, 0x2d, /* cmp r5, #0 */
624 0x0b, 0xd0, /* beq.n 1e <exit> */
625 0x4c, 0x68, /* ldr r4, [r1, #4] */
626 0xac, 0x42, /* cmp r4, r5 */
627 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
628 0x20, 0xcc, /* ldmia r4!, {r5} */
629 0x20, 0xc3, /* stmia r3!, {r5} */
630 0x94, 0x42, /* cmp r4, r2 */
631 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
632 0x0c, 0x46, /* mov r4, r1 */
633 0x08, 0x34, /* adds r4, #8 */
635 0x4c, 0x60, /* str r4, [r1, #4] */
636 0x04, 0x38, /* subs r0, #4 */
637 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
639 0x00, 0xbe /* bkpt 0x0000 */
643 /* Start a low level flash write for the specified region */
644 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
646 struct target *target = chip->target;
647 uint32_t buffer_size = 8192;
648 struct working_area *write_algorithm;
649 struct working_area *source;
650 uint32_t address = NRF5_FLASH_BASE + offset;
651 struct reg_param reg_params[4];
652 struct armv7m_algorithm armv7m_info;
653 int retval = ERROR_OK;
656 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
657 assert(bytes % 4 == 0);
659 /* allocate working area with flash programming code */
660 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
661 &write_algorithm) != ERROR_OK) {
662 LOG_WARNING("no working area available, falling back to slow memory writes");
664 for (; bytes > 0; bytes -= 4) {
665 retval = target_write_memory(chip->target, offset, 4, 1, buffer);
666 if (retval != ERROR_OK)
669 retval = nrf5_wait_for_nvmc(chip);
670 if (retval != ERROR_OK)
680 LOG_WARNING("using fast async flash loader. This is currently supported");
681 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
682 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg/nrf52.cfg to disable it");
684 retval = target_write_buffer(target, write_algorithm->address,
685 sizeof(nrf5_flash_write_code),
686 nrf5_flash_write_code);
687 if (retval != ERROR_OK)
691 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
693 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
694 if (buffer_size <= 256) {
695 /* free working area, write algorithm already allocated */
696 target_free_working_area(target, write_algorithm);
698 LOG_WARNING("No large enough working area available, can't do block memory writes");
699 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
703 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
704 armv7m_info.core_mode = ARM_MODE_THREAD;
706 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
707 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer start */
708 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer end */
709 init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
711 buf_set_u32(reg_params[0].value, 0, 32, bytes);
712 buf_set_u32(reg_params[1].value, 0, 32, source->address);
713 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
714 buf_set_u32(reg_params[3].value, 0, 32, address);
716 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
719 source->address, source->size,
720 write_algorithm->address, 0,
723 target_free_working_area(target, source);
724 target_free_working_area(target, write_algorithm);
726 destroy_reg_param(®_params[0]);
727 destroy_reg_param(®_params[1]);
728 destroy_reg_param(®_params[2]);
729 destroy_reg_param(®_params[3]);
734 /* Check and erase flash sectors in specified range then start a low level page write.
735 start/end must be sector aligned.
737 static int nrf5_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
739 int res = ERROR_FAIL;
740 struct nrf5_info *chip = bank->driver_priv;
741 struct flash_sector *sector;
744 assert(start % chip->code_page_size == 0);
745 assert(end % chip->code_page_size == 0);
747 /* Erase all sectors */
748 for (offset = start; offset < end; offset += chip->code_page_size) {
749 sector = nrf5_find_sector_by_address(bank, offset);
751 LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
752 return ERROR_FLASH_SECTOR_INVALID;
755 if (sector->is_protected) {
756 LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
760 if (sector->is_erased != 1) { /* 1 = erased, 0= not erased, -1 = unknown */
761 res = nrf5_erase_page(bank, chip, sector);
762 if (res != ERROR_OK) {
763 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
767 sector->is_erased = 0;
770 res = nrf5_nvmc_write_enable(chip);
774 res = nrf5_ll_flash_write(chip, start, buffer, (end - start));
778 return nrf5_nvmc_read_only(chip);
781 nrf5_nvmc_read_only(chip);
783 LOG_ERROR("Failed to write to nrf5 flash");
787 static int nrf5_erase(struct flash_bank *bank, int first, int last)
790 struct nrf5_info *chip;
792 res = nrf5_get_probed_chip_if_halted(bank, &chip);
796 /* For each sector to be erased */
797 for (int s = first; s <= last && res == ERROR_OK; s++)
798 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
803 static int nrf5_code_flash_write(struct flash_bank *bank,
804 struct nrf5_info *chip,
805 const uint8_t *buffer, uint32_t offset, uint32_t count)
809 /* Need to perform reads to fill any gaps we need to preserve in the first page,
810 before the start of buffer, or in the last page, after the end of buffer */
811 uint32_t first_page = offset/chip->code_page_size;
812 uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
814 uint32_t first_page_offset = first_page * chip->code_page_size;
815 uint32_t last_page_offset = last_page * chip->code_page_size;
817 LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
818 offset, offset+count, first_page_offset, last_page_offset);
820 uint32_t page_cnt = last_page - first_page;
821 uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
823 /* Fill in any space between start of first page and start of buffer */
824 uint32_t pre = offset - first_page_offset;
826 res = target_read_memory(bank->target,
835 /* Fill in main contents of buffer */
836 memcpy(buffer_to_flash+pre, buffer, count);
838 /* Fill in any space between end of buffer and end of last page */
839 uint32_t post = last_page_offset - (offset+count);
841 /* Retrieve the full row contents from Flash */
842 res = target_read_memory(bank->target,
846 buffer_to_flash+pre+count);
851 return nrf5_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
854 static int nrf5_uicr_flash_write(struct flash_bank *bank,
855 struct nrf5_info *chip,
856 const uint8_t *buffer, uint32_t offset, uint32_t count)
859 uint8_t uicr[NRF5_UICR_SIZE];
860 struct flash_sector *sector = &bank->sectors[0];
862 if ((offset + count) > NRF5_UICR_SIZE)
865 res = target_read_memory(bank->target,
874 if (sector->is_erased != 1) {
875 res = nrf5_erase_page(bank, chip, sector);
880 res = nrf5_nvmc_write_enable(chip);
884 memcpy(&uicr[offset], buffer, count);
886 res = nrf5_ll_flash_write(chip, NRF5_UICR_BASE, uicr, NRF5_UICR_SIZE);
887 if (res != ERROR_OK) {
888 nrf5_nvmc_read_only(chip);
892 return nrf5_nvmc_read_only(chip);
896 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
897 uint32_t offset, uint32_t count)
900 struct nrf5_info *chip;
902 res = nrf5_get_probed_chip_if_halted(bank, &chip);
906 return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
910 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
912 static struct nrf5_info *chip;
914 switch (bank->base) {
915 case NRF5_FLASH_BASE:
916 bank->bank_number = 0;
919 bank->bank_number = 1;
922 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
927 /* Create a new chip */
928 chip = calloc(1, sizeof(*chip));
932 chip->target = bank->target;
935 switch (bank->base) {
936 case NRF5_FLASH_BASE:
937 chip->bank[bank->bank_number].write = nrf5_code_flash_write;
940 chip->bank[bank->bank_number].write = nrf5_uicr_flash_write;
944 chip->bank[bank->bank_number].probed = false;
945 bank->driver_priv = chip;
950 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
953 struct flash_bank *bank = NULL;
954 struct target *target = get_current_target(CMD_CTX);
956 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
960 assert(bank != NULL);
962 struct nrf5_info *chip;
964 res = nrf5_get_probed_chip_if_halted(bank, &chip);
970 res = target_read_u32(target, NRF5_FICR_PPFC,
972 if (res != ERROR_OK) {
973 LOG_ERROR("Couldn't read PPFC register");
977 if ((ppfc & 0xFF) == 0x00) {
978 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
979 "mass erase command won't work.");
983 res = nrf5_erase_all(chip);
984 if (res != ERROR_OK) {
985 LOG_ERROR("Failed to erase the chip");
986 nrf5_protect_check(bank);
990 for (int i = 0; i < bank->num_sectors; i++)
991 bank->sectors[i].is_erased = 1;
993 res = nrf5_protect_check(bank);
994 if (res != ERROR_OK) {
995 LOG_ERROR("Failed to check chip's write protection");
999 res = get_flash_bank_by_addr(target, NRF5_UICR_BASE, true, &bank);
1000 if (res != ERROR_OK)
1003 bank->sectors[0].is_erased = 1;
1008 static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
1012 struct nrf5_info *chip;
1014 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1015 if (res != ERROR_OK)
1019 const uint32_t address;
1022 { .address = NRF5_FICR_CODEPAGESIZE },
1023 { .address = NRF5_FICR_CODESIZE },
1024 { .address = NRF5_FICR_CLENR0 },
1025 { .address = NRF5_FICR_PPFC },
1026 { .address = NRF5_FICR_NUMRAMBLOCK },
1027 { .address = NRF5_FICR_SIZERAMBLOCK0 },
1028 { .address = NRF5_FICR_SIZERAMBLOCK1 },
1029 { .address = NRF5_FICR_SIZERAMBLOCK2 },
1030 { .address = NRF5_FICR_SIZERAMBLOCK3 },
1031 { .address = NRF5_FICR_CONFIGID },
1032 { .address = NRF5_FICR_DEVICEID0 },
1033 { .address = NRF5_FICR_DEVICEID1 },
1034 { .address = NRF5_FICR_ER0 },
1035 { .address = NRF5_FICR_ER1 },
1036 { .address = NRF5_FICR_ER2 },
1037 { .address = NRF5_FICR_ER3 },
1038 { .address = NRF5_FICR_IR0 },
1039 { .address = NRF5_FICR_IR1 },
1040 { .address = NRF5_FICR_IR2 },
1041 { .address = NRF5_FICR_IR3 },
1042 { .address = NRF5_FICR_DEVICEADDRTYPE },
1043 { .address = NRF5_FICR_DEVICEADDR0 },
1044 { .address = NRF5_FICR_DEVICEADDR1 },
1045 { .address = NRF5_FICR_OVERRIDEN },
1046 { .address = NRF5_FICR_NRF_1MBIT0 },
1047 { .address = NRF5_FICR_NRF_1MBIT1 },
1048 { .address = NRF5_FICR_NRF_1MBIT2 },
1049 { .address = NRF5_FICR_NRF_1MBIT3 },
1050 { .address = NRF5_FICR_NRF_1MBIT4 },
1051 { .address = NRF5_FICR_BLE_1MBIT0 },
1052 { .address = NRF5_FICR_BLE_1MBIT1 },
1053 { .address = NRF5_FICR_BLE_1MBIT2 },
1054 { .address = NRF5_FICR_BLE_1MBIT3 },
1055 { .address = NRF5_FICR_BLE_1MBIT4 },
1057 { .address = NRF5_UICR_CLENR0, },
1058 { .address = NRF5_UICR_RBPCONF },
1059 { .address = NRF5_UICR_XTALFREQ },
1060 { .address = NRF5_UICR_FWID },
1063 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1064 res = target_read_u32(chip->target, ficr[i].address,
1066 if (res != ERROR_OK) {
1067 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1072 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1073 res = target_read_u32(chip->target, uicr[i].address,
1075 if (res != ERROR_OK) {
1076 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1081 snprintf(buf, buf_size,
1082 "\n[factory information control block]\n\n"
1083 "code page size: %"PRIu32"B\n"
1084 "code memory size: %"PRIu32"kB\n"
1085 "code region 0 size: %"PRIu32"kB\n"
1086 "pre-programmed code: %s\n"
1087 "number of ram blocks: %"PRIu32"\n"
1088 "ram block 0 size: %"PRIu32"B\n"
1089 "ram block 1 size: %"PRIu32"B\n"
1090 "ram block 2 size: %"PRIu32"B\n"
1091 "ram block 3 size: %"PRIu32 "B\n"
1092 "config id: %" PRIx32 "\n"
1093 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1094 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1095 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1096 "device address type: 0x%"PRIx32"\n"
1097 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1098 "override enable: %"PRIx32"\n"
1099 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1100 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1101 "\n[user information control block]\n\n"
1102 "code region 0 size: %"PRIu32"kB\n"
1103 "read back protection configuration: %"PRIx32"\n"
1104 "reset value for XTALFREQ: %"PRIx32"\n"
1105 "firmware id: 0x%04"PRIx32,
1107 (ficr[1].value * ficr[0].value) / 1024,
1108 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1109 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1112 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1113 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1114 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1116 ficr[10].value, ficr[11].value,
1117 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1118 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1120 ficr[21].value, ficr[22].value,
1122 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1123 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1124 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1125 uicr[1].value & 0xFFFF,
1126 uicr[2].value & 0xFF,
1127 uicr[3].value & 0xFFFF);
1132 static const struct command_registration nrf5_exec_command_handlers[] = {
1134 .name = "mass_erase",
1135 .handler = nrf5_handle_mass_erase_command,
1136 .mode = COMMAND_EXEC,
1137 .help = "Erase all flash contents of the chip.",
1139 COMMAND_REGISTRATION_DONE
1142 static const struct command_registration nrf5_command_handlers[] = {
1145 .mode = COMMAND_ANY,
1146 .help = "nrf5 flash command group",
1148 .chain = nrf5_exec_command_handlers,
1152 .mode = COMMAND_ANY,
1153 .help = "nrf51 flash command group",
1155 .chain = nrf5_exec_command_handlers,
1157 COMMAND_REGISTRATION_DONE
1160 struct flash_driver nrf5_flash = {
1162 .commands = nrf5_command_handlers,
1163 .flash_bank_command = nrf5_flash_bank_command,
1165 .erase = nrf5_erase,
1166 .protect = nrf5_protect,
1167 .write = nrf5_write,
1168 .read = default_flash_read,
1169 .probe = nrf5_probe,
1170 .auto_probe = nrf5_auto_probe,
1171 .erase_check = default_flash_blank_check,
1172 .protect_check = nrf5_protect_check,
1175 /* We need to retain the flash-driver name as well as the commands
1176 * for backwards compatability */
1177 struct flash_driver nrf51_flash = {
1179 .commands = nrf5_command_handlers,
1180 .flash_bank_command = nrf5_flash_bank_command,
1182 .erase = nrf5_erase,
1183 .protect = nrf5_protect,
1184 .write = nrf5_write,
1185 .read = default_flash_read,
1186 .probe = nrf5_probe,
1187 .auto_probe = nrf5_auto_probe,
1188 .erase_check = default_flash_blank_check,
1189 .protect_check = nrf5_protect_check,