git.sur5r.net Git - openocd/blob - src/flash/nor/nrf51.c

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Synapse Product Development                        *
   3  *   Andrey Smirnov <andrew.smironv@gmail.com>                             *
   4  *   Angus Gratton <gus@projectgus.com>                                    *
   5  *   Erdem U. Altunyurt <spamjunkeater@gmail.com>                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  21  ***************************************************************************/
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include <target/algorithm.h>
  29 #include <target/armv7m.h>
  30 #include <helper/types.h>
  31
  32 enum {
  33         NRF51_FLASH_BASE = 0x00000000,
  34 };
  35
  36 enum nrf51_ficr_registers {
  37         NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
  38
  39 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
  40
  41         NRF51_FICR_CODEPAGESIZE         = NRF51_FICR_REG(0x010),
  42         NRF51_FICR_CODESIZE             = NRF51_FICR_REG(0x014),
  43         NRF51_FICR_CLENR0               = NRF51_FICR_REG(0x028),
  44         NRF51_FICR_PPFC                 = NRF51_FICR_REG(0x02C),
  45         NRF51_FICR_NUMRAMBLOCK          = NRF51_FICR_REG(0x034),
  46         NRF51_FICR_SIZERAMBLOCK0        = NRF51_FICR_REG(0x038),
  47         NRF51_FICR_SIZERAMBLOCK1        = NRF51_FICR_REG(0x03C),
  48         NRF51_FICR_SIZERAMBLOCK2        = NRF51_FICR_REG(0x040),
  49         NRF51_FICR_SIZERAMBLOCK3        = NRF51_FICR_REG(0x044),
  50         NRF51_FICR_CONFIGID             = NRF51_FICR_REG(0x05C),
  51         NRF51_FICR_DEVICEID0            = NRF51_FICR_REG(0x060),
  52         NRF51_FICR_DEVICEID1            = NRF51_FICR_REG(0x064),
  53         NRF51_FICR_ER0                  = NRF51_FICR_REG(0x080),
  54         NRF51_FICR_ER1                  = NRF51_FICR_REG(0x084),
  55         NRF51_FICR_ER2                  = NRF51_FICR_REG(0x088),
  56         NRF51_FICR_ER3                  = NRF51_FICR_REG(0x08C),
  57         NRF51_FICR_IR0                  = NRF51_FICR_REG(0x090),
  58         NRF51_FICR_IR1                  = NRF51_FICR_REG(0x094),
  59         NRF51_FICR_IR2                  = NRF51_FICR_REG(0x098),
  60         NRF51_FICR_IR3                  = NRF51_FICR_REG(0x09C),
  61         NRF51_FICR_DEVICEADDRTYPE       = NRF51_FICR_REG(0x0A0),
  62         NRF51_FICR_DEVICEADDR0          = NRF51_FICR_REG(0x0A4),
  63         NRF51_FICR_DEVICEADDR1          = NRF51_FICR_REG(0x0A8),
  64         NRF51_FICR_OVERRIDEN            = NRF51_FICR_REG(0x0AC),
  65         NRF51_FICR_NRF_1MBIT0           = NRF51_FICR_REG(0x0B0),
  66         NRF51_FICR_NRF_1MBIT1           = NRF51_FICR_REG(0x0B4),
  67         NRF51_FICR_NRF_1MBIT2           = NRF51_FICR_REG(0x0B8),
  68         NRF51_FICR_NRF_1MBIT3           = NRF51_FICR_REG(0x0BC),
  69         NRF51_FICR_NRF_1MBIT4           = NRF51_FICR_REG(0x0C0),
  70         NRF51_FICR_BLE_1MBIT0           = NRF51_FICR_REG(0x0EC),
  71         NRF51_FICR_BLE_1MBIT1           = NRF51_FICR_REG(0x0F0),
  72         NRF51_FICR_BLE_1MBIT2           = NRF51_FICR_REG(0x0F4),
  73         NRF51_FICR_BLE_1MBIT3           = NRF51_FICR_REG(0x0F8),
  74         NRF51_FICR_BLE_1MBIT4           = NRF51_FICR_REG(0x0FC),
  75 };
  76
  77 enum nrf51_uicr_registers {
  78         NRF51_UICR_BASE = 0x10001000, /* User Information
  79                                        * Configuration Regsters */
  80
  81         NRF51_UICR_SIZE = 0x100,
  82
  83 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
  84
  85         NRF51_UICR_CLENR0       = NRF51_UICR_REG(0x000),
  86         NRF51_UICR_RBPCONF      = NRF51_UICR_REG(0x004),
  87         NRF51_UICR_XTALFREQ     = NRF51_UICR_REG(0x008),
  88         NRF51_UICR_FWID         = NRF51_UICR_REG(0x010),
  89 };
  90
  91 enum nrf51_nvmc_registers {
  92         NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
  93                                        * Controller Regsters */
  94
  95 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
  96
  97         NRF51_NVMC_READY        = NRF51_NVMC_REG(0x400),
  98         NRF51_NVMC_CONFIG       = NRF51_NVMC_REG(0x504),
  99         NRF51_NVMC_ERASEPAGE    = NRF51_NVMC_REG(0x508),
 100         NRF51_NVMC_ERASEALL     = NRF51_NVMC_REG(0x50C),
 101         NRF51_NVMC_ERASEUICR    = NRF51_NVMC_REG(0x514),
 102 };
 103
 104 enum nrf51_nvmc_config_bits {
 105         NRF51_NVMC_CONFIG_REN = 0x00,
 106         NRF51_NVMC_CONFIG_WEN = 0x01,
 107         NRF51_NVMC_CONFIG_EEN = 0x02,
 108
 109 };
 110
 111 struct nrf51_info {
 112         uint32_t code_page_size;
 113         uint32_t code_memory_size;
 114
 115         struct {
 116                 bool probed;
 117                 int (*write) (struct flash_bank *bank,
 118                               struct nrf51_info *chip,
 119                               const uint8_t *buffer, uint32_t offset, uint32_t count);
 120         } bank[2];
 121         struct target *target;
 122 };
 123
 124 struct nrf51_device_spec {
 125         uint16_t hwid;
 126         const char *variant;
 127         const char *build_code;
 128         unsigned int flash_size_kb;
 129 };
 130
 131 /* The known devices table below is derived from the "nRF51 Series
 132  * Compatibility Matrix" document, which can be found by searching for
 133  * ATTN-51 on the Nordic Semi website:
 134  *
 135  * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
 136  *
 137  * Up to date with Matrix v2.0, plus some additional HWIDs.
 138  *
 139  * The additional HWIDs apply where the build code in the matrix is
 140  * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
 141  * for x==0, x!=0 means different (unspecified) HWIDs.
 142  */
 143 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 144         /* nRF51822 Devices (IC rev 1). */
 145         {
 146                 .hwid           = 0x001D,
 147                 .variant        = "QFAA",
 148                 .build_code     = "CA/C0",
 149                 .flash_size_kb  = 256,
 150         },
 151         {
 152                 .hwid           = 0x0026,
 153                 .variant        = "QFAB",
 154                 .build_code     = "AA",
 155                 .flash_size_kb  = 128,
 156         },
 157         {
 158                 .hwid           = 0x0027,
 159                 .variant        = "QFAB",
 160                 .build_code     = "A0",
 161                 .flash_size_kb  = 128,
 162         },
 163         {
 164                 .hwid           = 0x0020,
 165                 .variant        = "CEAA",
 166                 .build_code     = "BA",
 167                 .flash_size_kb  = 256,
 168         },
 169         {
 170                 .hwid           = 0x002F,
 171                 .variant        = "CEAA",
 172                 .build_code     = "B0",
 173                 .flash_size_kb  = 256,
 174         },
 175
 176         /* nRF51822 Devices (IC rev 2). */
 177         {
 178                 .hwid           = 0x002A,
 179                 .variant        = "QFAA",
 180                 .build_code     = "FA0",
 181                 .flash_size_kb  = 256,
 182         },
 183         {
 184                 .hwid           = 0x0044,
 185                 .variant        = "QFAA",
 186                 .build_code     = "GC0",
 187                 .flash_size_kb  = 256,
 188         },
 189         {
 190                 .hwid           = 0x003C,
 191                 .variant        = "QFAA",
 192                 .build_code     = "G0",
 193                 .flash_size_kb  = 256,
 194         },
 195         {
 196                 .hwid           = 0x004C,
 197                 .variant        = "QFAB",
 198                 .build_code     = "B0",
 199                 .flash_size_kb  = 128,
 200         },
 201         {
 202                 .hwid           = 0x0040,
 203                 .variant        = "CEAA",
 204                 .build_code     = "CA0",
 205                 .flash_size_kb  = 256,
 206         },
 207         {
 208                 .hwid           = 0x0047,
 209                 .variant        = "CEAA",
 210                 .build_code     = "DA0",
 211                 .flash_size_kb  = 256,
 212         },
 213         {
 214                 .hwid           = 0x004D,
 215                 .variant        = "CEAA",
 216                 .build_code     = "D00",
 217                 .flash_size_kb  = 256,
 218         },
 219
 220         /* nRF51822 Devices (IC rev 3). */
 221         {
 222                 .hwid           = 0x0072,
 223                 .variant        = "QFAA",
 224                 .build_code     = "H0",
 225                 .flash_size_kb  = 256,
 226         },
 227         {
 228                 .hwid           = 0x007B,
 229                 .variant        = "QFAB",
 230                 .build_code     = "C0",
 231                 .flash_size_kb  = 128,
 232         },
 233         {
 234                 .hwid           = 0x0083,
 235                 .variant        = "QFAC",
 236                 .build_code     = "A0",
 237                 .flash_size_kb  = 256,
 238         },
 239         {
 240                 .hwid           = 0x0084,
 241                 .variant        = "QFAC",
 242                 .build_code     = "A1",
 243                 .flash_size_kb  = 256,
 244         },
 245         {
 246                 .hwid           = 0x007D,
 247                 .variant        = "CDAB",
 248                 .build_code     = "A0",
 249                 .flash_size_kb  = 128,
 250         },
 251         {
 252                 .hwid           = 0x0079,
 253                 .variant        = "CEAA",
 254                 .build_code     = "E0",
 255                 .flash_size_kb  = 256,
 256         },
 257         {
 258                 .hwid           = 0x0087,
 259                 .variant        = "CFAC",
 260                 .build_code     = "A0",
 261                 .flash_size_kb  = 256,
 262         },
 263
 264         /* nRF51422 Devices (IC rev 1). */
 265         {
 266                 .hwid           = 0x001E,
 267                 .variant        = "QFAA",
 268                 .build_code     = "CA",
 269                 .flash_size_kb  = 256,
 270         },
 271         {
 272                 .hwid           = 0x0024,
 273                 .variant        = "QFAA",
 274                 .build_code     = "C0",
 275                 .flash_size_kb  = 256,
 276         },
 277         {
 278                 .hwid           = 0x0031,
 279                 .variant        = "CEAA",
 280                 .build_code     = "A0A",
 281                 .flash_size_kb  = 256,
 282         },
 283
 284         /* nRF51422 Devices (IC rev 2). */
 285         {
 286                 .hwid           = 0x002D,
 287                 .variant        = "QFAA",
 288                 .build_code     = "DAA",
 289                 .flash_size_kb  = 256,
 290         },
 291         {
 292                 .hwid           = 0x002E,
 293                 .variant        = "QFAA",
 294                 .build_code     = "E0",
 295                 .flash_size_kb  = 256,
 296         },
 297         {
 298                 .hwid           = 0x0061,
 299                 .variant        = "QFAB",
 300                 .build_code     = "A00",
 301                 .flash_size_kb  = 128,
 302         },
 303         {
 304                 .hwid           = 0x0050,
 305                 .variant        = "CEAA",
 306                 .build_code     = "B0",
 307                 .flash_size_kb  = 256,
 308         },
 309
 310         /* nRF51422 Devices (IC rev 3). */
 311         {
 312                 .hwid           = 0x0073,
 313                 .variant        = "QFAA",
 314                 .build_code     = "F0",
 315                 .flash_size_kb  = 256,
 316         },
 317         {
 318                 .hwid           = 0x007C,
 319                 .variant        = "QFAB",
 320                 .build_code     = "B0",
 321                 .flash_size_kb  = 128,
 322         },
 323         {
 324                 .hwid           = 0x0085,
 325                 .variant        = "QFAC",
 326                 .build_code     = "A0",
 327                 .flash_size_kb  = 256,
 328         },
 329         {
 330                 .hwid           = 0x0086,
 331                 .variant        = "QFAC",
 332                 .build_code     = "A1",
 333                 .flash_size_kb  = 256,
 334         },
 335         {
 336                 .hwid           = 0x007E,
 337                 .variant        = "CDAB",
 338                 .build_code     = "A0",
 339                 .flash_size_kb  = 128,
 340         },
 341         {
 342                 .hwid           = 0x007A,
 343                 .variant        = "CEAA",
 344                 .build_code     = "C0",
 345                 .flash_size_kb  = 256,
 346         },
 347         {
 348                 .hwid           = 0x0088,
 349                 .variant        = "CFAC",
 350                 .build_code     = "A0",
 351                 .flash_size_kb  = 256,
 352         },
 353
 354         /* mdbt40
 355            no idea if variant and build code are correct */
 356         {
 357                 .hwid           = 0x0057,
 358                 .variant        = "QFAA",
 359                 .build_code     = "G2",
 360                 .flash_size_kb  = 256,
 361         },
 362
 363         /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 364            with built-in jlink seem to use engineering samples not listed
 365            in the nRF51 Series Compatibility Matrix V1.0. */
 366         {
 367                 .hwid           = 0x0071,
 368                 .variant        = "QFAC",
 369                 .build_code     = "AB",
 370                 .flash_size_kb  = 256,
 371         },
 372 };
 373
 374 static int nrf51_bank_is_probed(struct flash_bank *bank)
 375 {
 376         struct nrf51_info *chip = bank->driver_priv;
 377
 378         assert(chip != NULL);
 379
 380         return chip->bank[bank->bank_number].probed;
 381 }
 382 static int nrf51_probe(struct flash_bank *bank);
 383
 384 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
 385 {
 386         if (bank->target->state != TARGET_HALTED) {
 387                 LOG_ERROR("Target not halted");
 388                 return ERROR_TARGET_NOT_HALTED;
 389         }
 390
 391         *chip = bank->driver_priv;
 392
 393         int probed = nrf51_bank_is_probed(bank);
 394         if (probed < 0)
 395                 return probed;
 396         else if (!probed)
 397                 return nrf51_probe(bank);
 398         else
 399                 return ERROR_OK;
 400 }
 401
 402 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
 403 {
 404         uint32_t ready;
 405         int res;
 406         int timeout = 100;
 407
 408         do {
 409                 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
 410                 if (res != ERROR_OK) {
 411                         LOG_ERROR("Couldn't read NVMC_READY register");
 412                         return res;
 413                 }
 414
 415                 if (ready == 0x00000001)
 416                         return ERROR_OK;
 417
 418                 alive_sleep(1);
 419         } while (timeout--);
 420
 421         LOG_DEBUG("Timed out waiting for NVMC_READY");
 422         return ERROR_FLASH_BUSY;
 423 }
 424
 425 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
 426 {
 427         int res;
 428         res = target_write_u32(chip->target,
 429                                NRF51_NVMC_CONFIG,
 430                                NRF51_NVMC_CONFIG_EEN);
 431
 432         if (res != ERROR_OK) {
 433                 LOG_ERROR("Failed to enable erase operation");
 434                 return res;
 435         }
 436
 437         /*
 438           According to NVMC examples in Nordic SDK busy status must be
 439           checked after writing to NVMC_CONFIG
 440          */
 441         res = nrf51_wait_for_nvmc(chip);
 442         if (res != ERROR_OK)
 443                 LOG_ERROR("Erase enable did not complete");
 444
 445         return res;
 446 }
 447
 448 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
 449 {
 450         int res;
 451         res = target_write_u32(chip->target,
 452                                NRF51_NVMC_CONFIG,
 453                                NRF51_NVMC_CONFIG_WEN);
 454
 455         if (res != ERROR_OK) {
 456                 LOG_ERROR("Failed to enable write operation");
 457                 return res;
 458         }
 459
 460         /*
 461           According to NVMC examples in Nordic SDK busy status must be
 462           checked after writing to NVMC_CONFIG
 463          */
 464         res = nrf51_wait_for_nvmc(chip);
 465         if (res != ERROR_OK)
 466                 LOG_ERROR("Write enable did not complete");
 467
 468         return res;
 469 }
 470
 471 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
 472 {
 473         int res;
 474         res = target_write_u32(chip->target,
 475                                NRF51_NVMC_CONFIG,
 476                                NRF51_NVMC_CONFIG_REN);
 477
 478         if (res != ERROR_OK) {
 479                 LOG_ERROR("Failed to enable read-only operation");
 480                 return res;
 481         }
 482         /*
 483           According to NVMC examples in Nordic SDK busy status must be
 484           checked after writing to NVMC_CONFIG
 485          */
 486         res = nrf51_wait_for_nvmc(chip);
 487         if (res != ERROR_OK)
 488                 LOG_ERROR("Read only enable did not complete");
 489
 490         return res;
 491 }
 492
 493 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
 494                                uint32_t erase_register, uint32_t erase_value)
 495 {
 496         int res;
 497
 498         res = nrf51_nvmc_erase_enable(chip);
 499         if (res != ERROR_OK)
 500                 goto error;
 501
 502         res = target_write_u32(chip->target,
 503                                erase_register,
 504                                erase_value);
 505         if (res != ERROR_OK)
 506                 goto set_read_only;
 507
 508         res = nrf51_wait_for_nvmc(chip);
 509         if (res != ERROR_OK)
 510                 goto set_read_only;
 511
 512         return nrf51_nvmc_read_only(chip);
 513
 514 set_read_only:
 515         nrf51_nvmc_read_only(chip);
 516 error:
 517         LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
 518                   erase_register, erase_value);
 519         return ERROR_FAIL;
 520 }
 521
 522 static int nrf51_protect_check(struct flash_bank *bank)
 523 {
 524         int res;
 525         uint32_t clenr0;
 526
 527         /* UICR cannot be write protected so just return early */
 528         if (bank->base == NRF51_UICR_BASE)
 529                 return ERROR_OK;
 530
 531         struct nrf51_info *chip = bank->driver_priv;
 532
 533         assert(chip != NULL);
 534
 535         res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
 536                               &clenr0);
 537         if (res != ERROR_OK) {
 538                 LOG_ERROR("Couldn't read code region 0 size[FICR]");
 539                 return res;
 540         }
 541
 542         if (clenr0 == 0xFFFFFFFF) {
 543                 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 544                                       &clenr0);
 545                 if (res != ERROR_OK) {
 546                         LOG_ERROR("Couldn't read code region 0 size[UICR]");
 547                         return res;
 548                 }
 549         }
 550
 551         for (int i = 0; i < bank->num_sectors; i++)
 552                 bank->sectors[i].is_protected =
 553                         clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 554
 555         return ERROR_OK;
 556 }
 557
 558 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 559 {
 560         int res;
 561         uint32_t clenr0, ppfc;
 562         struct nrf51_info *chip;
 563
 564         /* UICR cannot be write protected so just bail out early */
 565         if (bank->base == NRF51_UICR_BASE)
 566                 return ERROR_FAIL;
 567
 568         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 569         if (res != ERROR_OK)
 570                 return res;
 571
 572         if (first != 0) {
 573                 LOG_ERROR("Code region 0 must start at the begining of the bank");
 574                 return ERROR_FAIL;
 575         }
 576
 577         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 578                               &ppfc);
 579         if (res != ERROR_OK) {
 580                 LOG_ERROR("Couldn't read PPFC register");
 581                 return res;
 582         }
 583
 584         if ((ppfc & 0xFF) == 0x00) {
 585                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 586                 return ERROR_FAIL;
 587         };
 588
 589         res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 590                               &clenr0);
 591         if (res != ERROR_OK) {
 592                 LOG_ERROR("Couldn't read code region 0 size[UICR]");
 593                 return res;
 594         }
 595
 596         if (clenr0 == 0xFFFFFFFF) {
 597                 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
 598                                        clenr0);
 599                 if (res != ERROR_OK) {
 600                         LOG_ERROR("Couldn't write code region 0 size[UICR]");
 601                         return res;
 602                 }
 603
 604         } else {
 605                 LOG_ERROR("You need to perform chip erase before changing the protection settings");
 606         }
 607
 608         nrf51_protect_check(bank);
 609
 610         return ERROR_OK;
 611 }
 612
 613 static int nrf51_probe(struct flash_bank *bank)
 614 {
 615         uint32_t hwid;
 616         int res;
 617         struct nrf51_info *chip = bank->driver_priv;
 618
 619         res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
 620         if (res != ERROR_OK) {
 621                 LOG_ERROR("Couldn't read CONFIGID register");
 622                 return res;
 623         }
 624
 625         hwid &= 0xFFFF; /* HWID is stored in the lower two
 626                          * bytes of the CONFIGID register */
 627
 628         const struct nrf51_device_spec *spec = NULL;
 629         for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
 630                 if (hwid == nrf51_known_devices_table[i].hwid) {
 631                         spec = &nrf51_known_devices_table[i];
 632                         break;
 633                 }
 634
 635         if (!chip->bank[0].probed && !chip->bank[1].probed) {
 636                 if (spec)
 637                         LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
 638                                  spec->variant, spec->build_code, spec->flash_size_kb);
 639                 else
 640                         LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
 641         }
 642
 643
 644         if (bank->base == NRF51_FLASH_BASE) {
 645                 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
 646                                       &chip->code_page_size);
 647                 if (res != ERROR_OK) {
 648                         LOG_ERROR("Couldn't read code page size");
 649                         return res;
 650                 }
 651
 652                 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
 653                                       &chip->code_memory_size);
 654                 if (res != ERROR_OK) {
 655                         LOG_ERROR("Couldn't read code memory size");
 656                         return res;
 657                 }
 658
 659                 if (spec && chip->code_memory_size != spec->flash_size_kb) {
 660                         LOG_ERROR("Chip's reported Flash capacity does not match expected one");
 661                         return ERROR_FAIL;
 662                 }
 663
 664                 bank->size = chip->code_memory_size * 1024;
 665                 bank->num_sectors = bank->size / chip->code_page_size;
 666                 bank->sectors = calloc(bank->num_sectors,
 667                                        sizeof((bank->sectors)[0]));
 668                 if (!bank->sectors)
 669                         return ERROR_FLASH_BANK_NOT_PROBED;
 670
 671                 /* Fill out the sector information: all NRF51 sectors are the same size and
 672                  * there is always a fixed number of them. */
 673                 for (int i = 0; i < bank->num_sectors; i++) {
 674                         bank->sectors[i].size = chip->code_page_size;
 675                         bank->sectors[i].offset = i * chip->code_page_size;
 676
 677                         /* mark as unknown */
 678                         bank->sectors[i].is_erased = -1;
 679                         bank->sectors[i].is_protected = -1;
 680                 }
 681
 682                 nrf51_protect_check(bank);
 683
 684                 chip->bank[0].probed = true;
 685         } else {
 686                 bank->size = NRF51_UICR_SIZE;
 687                 bank->num_sectors = 1;
 688                 bank->sectors = calloc(bank->num_sectors,
 689                                        sizeof((bank->sectors)[0]));
 690                 if (!bank->sectors)
 691                         return ERROR_FLASH_BANK_NOT_PROBED;
 692
 693                 bank->sectors[0].size = bank->size;
 694                 bank->sectors[0].offset = 0;
 695
 696                 /* mark as unknown */
 697                 bank->sectors[0].is_erased = 0;
 698                 bank->sectors[0].is_protected = 0;
 699
 700                 chip->bank[1].probed = true;
 701         }
 702
 703         return ERROR_OK;
 704 }
 705
 706 static int nrf51_auto_probe(struct flash_bank *bank)
 707 {
 708         int probed = nrf51_bank_is_probed(bank);
 709
 710         if (probed < 0)
 711                 return probed;
 712         else if (probed)
 713                 return ERROR_OK;
 714         else
 715                 return nrf51_probe(bank);
 716 }
 717
 718 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
 719 {
 720         struct nrf51_info *chip = bank->driver_priv;
 721
 722         for (int i = 0; i < bank->num_sectors; i++)
 723                 if (bank->sectors[i].offset <= address &&
 724                     address < (bank->sectors[i].offset + chip->code_page_size))
 725                         return &bank->sectors[i];
 726         return NULL;
 727 }
 728
 729 static int nrf51_erase_all(struct nrf51_info *chip)
 730 {
 731         LOG_DEBUG("Erasing all non-volatile memory");
 732         return nrf51_nvmc_generic_erase(chip,
 733                                         NRF51_NVMC_ERASEALL,
 734                                         0x00000001);
 735 }
 736
 737 static int nrf51_erase_page(struct flash_bank *bank,
 738                                                         struct nrf51_info *chip,
 739                                                         struct flash_sector *sector)
 740 {
 741         int res;
 742
 743         LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
 744         if (sector->is_protected) {
 745                 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
 746                 return ERROR_FAIL;
 747         }
 748
 749         if (bank->base == NRF51_UICR_BASE) {
 750                 uint32_t ppfc;
 751                 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 752                                       &ppfc);
 753                 if (res != ERROR_OK) {
 754                         LOG_ERROR("Couldn't read PPFC register");
 755                         return res;
 756                 }
 757
 758                 if ((ppfc & 0xFF) == 0xFF) {
 759                         /* We can't erase the UICR.  Double-check to
 760                            see if it's already erased before complaining. */
 761                         default_flash_blank_check(bank);
 762                         if (sector->is_erased == 1)
 763                                 return ERROR_OK;
 764
 765                         LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 766                         return ERROR_FAIL;
 767                 };
 768
 769                 res = nrf51_nvmc_generic_erase(chip,
 770                                                NRF51_NVMC_ERASEUICR,
 771                                                0x00000001);
 772
 773
 774         } else {
 775                 res = nrf51_nvmc_generic_erase(chip,
 776                                                NRF51_NVMC_ERASEPAGE,
 777                                                sector->offset);
 778         }
 779
 780         if (res == ERROR_OK)
 781                 sector->is_erased = 1;
 782
 783         return res;
 784 }
 785
 786 static const uint8_t nrf51_flash_write_code[] = {
 787         /* See contrib/loaders/flash/cortex-m0.S */
 788 /* <wait_fifo>: */
 789         0x0d, 0x68,             /* ldr  r5,     [r1,    #0] */
 790         0x00, 0x2d,             /* cmp  r5,     #0 */
 791         0x0b, 0xd0,             /* beq.n        1e <exit> */
 792         0x4c, 0x68,             /* ldr  r4,     [r1,    #4] */
 793         0xac, 0x42,             /* cmp  r4,     r5 */
 794         0xf9, 0xd0,             /* beq.n        0 <wait_fifo> */
 795         0x20, 0xcc,             /* ldmia        r4!,    {r5} */
 796         0x20, 0xc3,             /* stmia        r3!,    {r5} */
 797         0x94, 0x42,             /* cmp  r4,     r2 */
 798         0x01, 0xd3,             /* bcc.n        18 <no_wrap> */
 799         0x0c, 0x46,             /* mov  r4,     r1 */
 800         0x08, 0x34,             /* adds r4,     #8 */
 801 /* <no_wrap>: */
 802         0x4c, 0x60,             /* str  r4, [r1,        #4] */
 803         0x04, 0x38,             /* subs r0, #4 */
 804         0xf0, 0xd1,             /* bne.n        0 <wait_fifo> */
 805 /* <exit>: */
 806         0x00, 0xbe              /* bkpt 0x0000 */
 807 };
 808
 809
 810 /* Start a low level flash write for the specified region */
 811 static int nrf51_ll_flash_write(struct nrf51_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
 812 {
 813         struct target *target = chip->target;
 814         uint32_t buffer_size = 8192;
 815         struct working_area *write_algorithm;
 816         struct working_area *source;
 817         uint32_t address = NRF51_FLASH_BASE + offset;
 818         struct reg_param reg_params[4];
 819         struct armv7m_algorithm armv7m_info;
 820         int retval = ERROR_OK;
 821
 822
 823         LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
 824         assert(bytes % 4 == 0);
 825
 826         /* allocate working area with flash programming code */
 827         if (target_alloc_working_area(target, sizeof(nrf51_flash_write_code),
 828                         &write_algorithm) != ERROR_OK) {
 829                 LOG_WARNING("no working area available, falling back to slow memory writes");
 830
 831                 for (; bytes > 0; bytes -= 4) {
 832                         retval = target_write_memory(chip->target, offset, 4, 1, buffer);
 833                         if (retval != ERROR_OK)
 834                                 return retval;
 835
 836                         retval = nrf51_wait_for_nvmc(chip);
 837                         if (retval != ERROR_OK)
 838                                 return retval;
 839
 840                         offset += 4;
 841                         buffer += 4;
 842                 }
 843
 844                 return ERROR_OK;
 845         }
 846
 847         LOG_WARNING("using fast async flash loader. This is currently supported");
 848         LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
 849         LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
 850
 851         retval = target_write_buffer(target, write_algorithm->address,
 852                                 sizeof(nrf51_flash_write_code),
 853                                 nrf51_flash_write_code);
 854         if (retval != ERROR_OK)
 855                 return retval;
 856
 857         /* memory buffer */
 858         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
 859                 buffer_size /= 2;
 860                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 861                 if (buffer_size <= 256) {
 862                         /* free working area, write algorithm already allocated */
 863                         target_free_working_area(target, write_algorithm);
 864
 865                         LOG_WARNING("No large enough working area available, can't do block memory writes");
 866                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 867                 }
 868         }
 869
 870         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 871         armv7m_info.core_mode = ARM_MODE_THREAD;
 872
 873         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
 874         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer start */
 875         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer end */
 876         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
 877
 878         buf_set_u32(reg_params[0].value, 0, 32, bytes);
 879         buf_set_u32(reg_params[1].value, 0, 32, source->address);
 880         buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
 881         buf_set_u32(reg_params[3].value, 0, 32, address);
 882
 883         retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
 884                         0, NULL,
 885                         4, reg_params,
 886                         source->address, source->size,
 887                         write_algorithm->address, 0,
 888                         &armv7m_info);
 889
 890         target_free_working_area(target, source);
 891         target_free_working_area(target, write_algorithm);
 892
 893         destroy_reg_param(&reg_params[0]);
 894         destroy_reg_param(&reg_params[1]);
 895         destroy_reg_param(&reg_params[2]);
 896         destroy_reg_param(&reg_params[3]);
 897
 898         return retval;
 899 }
 900
 901 /* Check and erase flash sectors in specified range then start a low level page write.
 902    start/end must be sector aligned.
 903 */
 904 static int nrf51_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
 905 {
 906         int res = ERROR_FAIL;
 907         struct nrf51_info *chip = bank->driver_priv;
 908         struct flash_sector *sector;
 909         uint32_t offset;
 910
 911         assert(start % chip->code_page_size == 0);
 912         assert(end % chip->code_page_size == 0);
 913
 914         /* Erase all sectors */
 915         for (offset = start; offset < end; offset += chip->code_page_size) {
 916                 sector = nrf51_find_sector_by_address(bank, offset);
 917                 if (!sector) {
 918                         LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
 919                         return ERROR_FLASH_SECTOR_INVALID;
 920                 }
 921
 922                 if (sector->is_protected) {
 923                         LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
 924                         goto error;
 925                 }
 926
 927                 if (sector->is_erased != 1) {   /* 1 = erased, 0= not erased, -1 = unknown */
 928                         res = nrf51_erase_page(bank, chip, sector);
 929                         if (res != ERROR_OK) {
 930                                 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
 931                                 goto error;
 932                         }
 933                 }
 934                 sector->is_erased = 0;
 935         }
 936
 937         res = nrf51_nvmc_write_enable(chip);
 938         if (res != ERROR_OK)
 939                 goto error;
 940
 941         res = nrf51_ll_flash_write(chip, start, buffer, (end - start));
 942         if (res != ERROR_OK)
 943                 goto set_read_only;
 944
 945         return nrf51_nvmc_read_only(chip);
 946
 947 set_read_only:
 948         nrf51_nvmc_read_only(chip);
 949 error:
 950         LOG_ERROR("Failed to write to nrf51 flash");
 951         return res;
 952 }
 953
 954 static int nrf51_erase(struct flash_bank *bank, int first, int last)
 955 {
 956         int res;
 957         struct nrf51_info *chip;
 958
 959         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 960         if (res != ERROR_OK)
 961                 return res;
 962
 963         /* For each sector to be erased */
 964         for (int s = first; s <= last && res == ERROR_OK; s++)
 965                 res = nrf51_erase_page(bank, chip, &bank->sectors[s]);
 966
 967         return res;
 968 }
 969
 970 static int nrf51_code_flash_write(struct flash_bank *bank,
 971                                   struct nrf51_info *chip,
 972                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
 973 {
 974
 975         int res;
 976         /* Need to perform reads to fill any gaps we need to preserve in the first page,
 977            before the start of buffer, or in the last page, after the end of buffer */
 978         uint32_t first_page = offset/chip->code_page_size;
 979         uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
 980
 981         uint32_t first_page_offset = first_page * chip->code_page_size;
 982         uint32_t last_page_offset = last_page * chip->code_page_size;
 983
 984         LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
 985                 offset, offset+count, first_page_offset, last_page_offset);
 986
 987         uint32_t page_cnt = last_page - first_page;
 988         uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
 989
 990         /* Fill in any space between start of first page and start of buffer */
 991         uint32_t pre = offset - first_page_offset;
 992         if (pre > 0) {
 993                 res = target_read_memory(bank->target,
 994                                         first_page_offset,
 995                                         1,
 996                                         pre,
 997                                         buffer_to_flash);
 998                 if (res != ERROR_OK)
 999                         return res;
1000         }
1001
1002         /* Fill in main contents of buffer */
1003         memcpy(buffer_to_flash+pre, buffer, count);
1004
1005         /* Fill in any space between end of buffer and end of last page */
1006         uint32_t post = last_page_offset - (offset+count);
1007         if (post > 0) {
1008                 /* Retrieve the full row contents from Flash */
1009                 res = target_read_memory(bank->target,
1010                                         offset + count,
1011                                         1,
1012                                         post,
1013                                         buffer_to_flash+pre+count);
1014                 if (res != ERROR_OK)
1015                         return res;
1016         }
1017
1018         return nrf51_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
1019 }
1020
1021 static int nrf51_uicr_flash_write(struct flash_bank *bank,
1022                                   struct nrf51_info *chip,
1023                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
1024 {
1025         int res;
1026         uint8_t uicr[NRF51_UICR_SIZE];
1027         struct flash_sector *sector = &bank->sectors[0];
1028
1029         if ((offset + count) > NRF51_UICR_SIZE)
1030                 return ERROR_FAIL;
1031
1032         res = target_read_memory(bank->target,
1033                                  NRF51_UICR_BASE,
1034                                  1,
1035                                  NRF51_UICR_SIZE,
1036                                  uicr);
1037
1038         if (res != ERROR_OK)
1039                 return res;
1040
1041         if (sector->is_erased != 1) {
1042                 res = nrf51_erase_page(bank, chip, sector);
1043                 if (res != ERROR_OK)
1044                         return res;
1045         }
1046
1047         res = nrf51_nvmc_write_enable(chip);
1048         if (res != ERROR_OK)
1049                 return res;
1050
1051         memcpy(&uicr[offset], buffer, count);
1052
1053         res = nrf51_ll_flash_write(chip, NRF51_UICR_BASE, uicr, NRF51_UICR_SIZE);
1054         if (res != ERROR_OK) {
1055                 nrf51_nvmc_read_only(chip);
1056                 return res;
1057         }
1058
1059         return nrf51_nvmc_read_only(chip);
1060 }
1061
1062
1063 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
1064                        uint32_t offset, uint32_t count)
1065 {
1066         int res;
1067         struct nrf51_info *chip;
1068
1069         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1070         if (res != ERROR_OK)
1071                 return res;
1072
1073         return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
1074 }
1075
1076
1077 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
1078 {
1079         static struct nrf51_info *chip;
1080
1081         switch (bank->base) {
1082         case NRF51_FLASH_BASE:
1083                 bank->bank_number = 0;
1084                 break;
1085         case NRF51_UICR_BASE:
1086                 bank->bank_number = 1;
1087                 break;
1088         default:
1089                 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
1090                 return ERROR_FAIL;
1091         }
1092
1093         if (!chip) {
1094                 /* Create a new chip */
1095                 chip = calloc(1, sizeof(*chip));
1096                 if (!chip)
1097                         return ERROR_FAIL;
1098
1099                 chip->target = bank->target;
1100         }
1101
1102         switch (bank->base) {
1103         case NRF51_FLASH_BASE:
1104                 chip->bank[bank->bank_number].write = nrf51_code_flash_write;
1105                 break;
1106         case NRF51_UICR_BASE:
1107                 chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
1108                 break;
1109         }
1110
1111         chip->bank[bank->bank_number].probed = false;
1112         bank->driver_priv = chip;
1113
1114         return ERROR_OK;
1115 }
1116
1117 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
1118 {
1119         int res;
1120         struct flash_bank *bank = NULL;
1121         struct target *target = get_current_target(CMD_CTX);
1122
1123         res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
1124         if (res != ERROR_OK)
1125                 return res;
1126
1127         assert(bank != NULL);
1128
1129         struct nrf51_info *chip;
1130
1131         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1132         if (res != ERROR_OK)
1133                 return res;
1134
1135         uint32_t ppfc;
1136
1137         res = target_read_u32(target, NRF51_FICR_PPFC,
1138                               &ppfc);
1139         if (res != ERROR_OK) {
1140                 LOG_ERROR("Couldn't read PPFC register");
1141                 return res;
1142         }
1143
1144         if ((ppfc & 0xFF) == 0x00) {
1145                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1146                           "mass erase command won't work.");
1147                 return ERROR_FAIL;
1148         };
1149
1150         res = nrf51_erase_all(chip);
1151         if (res != ERROR_OK) {
1152                 LOG_ERROR("Failed to erase the chip");
1153                 nrf51_protect_check(bank);
1154                 return res;
1155         }
1156
1157         for (int i = 0; i < bank->num_sectors; i++)
1158                 bank->sectors[i].is_erased = 1;
1159
1160         res = nrf51_protect_check(bank);
1161         if (res != ERROR_OK) {
1162                 LOG_ERROR("Failed to check chip's write protection");
1163                 return res;
1164         }
1165
1166         res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
1167         if (res != ERROR_OK)
1168                 return res;
1169
1170         bank->sectors[0].is_erased = 1;
1171
1172         return ERROR_OK;
1173 }
1174
1175 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
1176 {
1177         int res;
1178
1179         struct nrf51_info *chip;
1180
1181         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1182         if (res != ERROR_OK)
1183                 return res;
1184
1185         static struct {
1186                 const uint32_t address;
1187                 uint32_t value;
1188         } ficr[] = {
1189                 { .address = NRF51_FICR_CODEPAGESIZE    },
1190                 { .address = NRF51_FICR_CODESIZE        },
1191                 { .address = NRF51_FICR_CLENR0          },
1192                 { .address = NRF51_FICR_PPFC            },
1193                 { .address = NRF51_FICR_NUMRAMBLOCK     },
1194                 { .address = NRF51_FICR_SIZERAMBLOCK0   },
1195                 { .address = NRF51_FICR_SIZERAMBLOCK1   },
1196                 { .address = NRF51_FICR_SIZERAMBLOCK2   },
1197                 { .address = NRF51_FICR_SIZERAMBLOCK3   },
1198                 { .address = NRF51_FICR_CONFIGID        },
1199                 { .address = NRF51_FICR_DEVICEID0       },
1200                 { .address = NRF51_FICR_DEVICEID1       },
1201                 { .address = NRF51_FICR_ER0             },
1202                 { .address = NRF51_FICR_ER1             },
1203                 { .address = NRF51_FICR_ER2             },
1204                 { .address = NRF51_FICR_ER3             },
1205                 { .address = NRF51_FICR_IR0             },
1206                 { .address = NRF51_FICR_IR1             },
1207                 { .address = NRF51_FICR_IR2             },
1208                 { .address = NRF51_FICR_IR3             },
1209                 { .address = NRF51_FICR_DEVICEADDRTYPE  },
1210                 { .address = NRF51_FICR_DEVICEADDR0     },
1211                 { .address = NRF51_FICR_DEVICEADDR1     },
1212                 { .address = NRF51_FICR_OVERRIDEN       },
1213                 { .address = NRF51_FICR_NRF_1MBIT0      },
1214                 { .address = NRF51_FICR_NRF_1MBIT1      },
1215                 { .address = NRF51_FICR_NRF_1MBIT2      },
1216                 { .address = NRF51_FICR_NRF_1MBIT3      },
1217                 { .address = NRF51_FICR_NRF_1MBIT4      },
1218                 { .address = NRF51_FICR_BLE_1MBIT0      },
1219                 { .address = NRF51_FICR_BLE_1MBIT1      },
1220                 { .address = NRF51_FICR_BLE_1MBIT2      },
1221                 { .address = NRF51_FICR_BLE_1MBIT3      },
1222                 { .address = NRF51_FICR_BLE_1MBIT4      },
1223         }, uicr[] = {
1224                 { .address = NRF51_UICR_CLENR0,         },
1225                 { .address = NRF51_UICR_RBPCONF         },
1226                 { .address = NRF51_UICR_XTALFREQ        },
1227                 { .address = NRF51_UICR_FWID            },
1228         };
1229
1230         for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1231                 res = target_read_u32(chip->target, ficr[i].address,
1232                                       &ficr[i].value);
1233                 if (res != ERROR_OK) {
1234                         LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1235                         return res;
1236                 }
1237         }
1238
1239         for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1240                 res = target_read_u32(chip->target, uicr[i].address,
1241                                       &uicr[i].value);
1242                 if (res != ERROR_OK) {
1243                         LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1244                         return res;
1245                 }
1246         }
1247
1248         snprintf(buf, buf_size,
1249                  "\n[factory information control block]\n\n"
1250                  "code page size: %"PRIu32"B\n"
1251                  "code memory size: %"PRIu32"kB\n"
1252                  "code region 0 size: %"PRIu32"kB\n"
1253                  "pre-programmed code: %s\n"
1254                  "number of ram blocks: %"PRIu32"\n"
1255                  "ram block 0 size: %"PRIu32"B\n"
1256                  "ram block 1 size: %"PRIu32"B\n"
1257                  "ram block 2 size: %"PRIu32"B\n"
1258                  "ram block 3 size: %"PRIu32 "B\n"
1259                  "config id: %" PRIx32 "\n"
1260                  "device id: 0x%"PRIx32"%08"PRIx32"\n"
1261                  "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1262                  "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1263                  "device address type: 0x%"PRIx32"\n"
1264                  "device address: 0x%"PRIx32"%08"PRIx32"\n"
1265                  "override enable: %"PRIx32"\n"
1266                  "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1267                  "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1268                  "\n[user information control block]\n\n"
1269                  "code region 0 size: %"PRIu32"kB\n"
1270                  "read back protection configuration: %"PRIx32"\n"
1271                  "reset value for XTALFREQ: %"PRIx32"\n"
1272                  "firmware id: 0x%04"PRIx32,
1273                  ficr[0].value,
1274                  ficr[1].value,
1275                  (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1276                  ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1277                  ficr[4].value,
1278                  ficr[5].value,
1279                  (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1280                  (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1281                  (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1282                  ficr[9].value,
1283                  ficr[10].value, ficr[11].value,
1284                  ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1285                  ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1286                  ficr[20].value,
1287                  ficr[21].value, ficr[22].value,
1288                  ficr[23].value,
1289                  ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1290                  ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1291                  (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1292                  uicr[1].value & 0xFFFF,
1293                  uicr[2].value & 0xFF,
1294                  uicr[3].value & 0xFFFF);
1295
1296         return ERROR_OK;
1297 }
1298
1299 static const struct command_registration nrf51_exec_command_handlers[] = {
1300         {
1301                 .name           = "mass_erase",
1302                 .handler        = nrf51_handle_mass_erase_command,
1303                 .mode           = COMMAND_EXEC,
1304                 .help           = "Erase all flash contents of the chip.",
1305         },
1306         COMMAND_REGISTRATION_DONE
1307 };
1308
1309 static const struct command_registration nrf51_command_handlers[] = {
1310         {
1311                 .name   = "nrf51",
1312                 .mode   = COMMAND_ANY,
1313                 .help   = "nrf51 flash command group",
1314                 .usage  = "",
1315                 .chain  = nrf51_exec_command_handlers,
1316         },
1317         COMMAND_REGISTRATION_DONE
1318 };
1319
1320 struct flash_driver nrf51_flash = {
1321         .name                   = "nrf51",
1322         .commands               = nrf51_command_handlers,
1323         .flash_bank_command     = nrf51_flash_bank_command,
1324         .info                   = nrf51_info,
1325         .erase                  = nrf51_erase,
1326         .protect                = nrf51_protect,
1327         .write                  = nrf51_write,
1328         .read                   = default_flash_read,
1329         .probe                  = nrf51_probe,
1330         .auto_probe             = nrf51_auto_probe,
1331         .erase_check            = default_flash_blank_check,
1332         .protect_check          = nrf51_protect_check,
1333 };