1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
24 /***************************************************************************
25 * STELLARIS is tested on LM3S811, LM3S6965
26 ***************************************************************************/
32 #include "stellaris.h"
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
37 #define DID0_VER(did0) ((did0 >> 28)&0x07)
39 static int stellaris_read_part_info(struct flash_bank *bank);
40 static uint32_t stellaris_get_flash_status(struct flash_bank *bank);
42 static int stellaris_mass_erase(struct flash_bank *bank);
219 static char * StellarisClassname[5] =
228 /***************************************************************************
229 * openocd command interface *
230 ***************************************************************************/
232 /* flash_bank stellaris <base> <size> 0 0 <target#>
234 FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
236 struct stellaris_flash_bank *stellaris_info;
240 LOG_WARNING("incomplete flash_bank stellaris configuration");
241 return ERROR_FLASH_BANK_INVALID;
244 stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
246 bank->driver_priv = stellaris_info;
248 stellaris_info->target_name = "Unknown target";
250 /* part wasn't probed for info yet */
251 stellaris_info->did1 = 0;
253 /* TODO Specify the main crystal speed in kHz using an optional
254 * argument; ditto, the speed of an external oscillator used
255 * instead of a crystal. Avoid programming flash using IOSC.
260 static int stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
262 int printed, device_class;
263 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
265 stellaris_read_part_info(bank);
267 if (stellaris_info->did1 == 0)
269 printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");
272 return ERROR_FLASH_OPERATION_FAILED;
275 if (DID0_VER(stellaris_info->did0) > 0)
277 device_class = (stellaris_info->did0 >> 16) & 0xFF;
283 printed = snprintf(buf,
285 "\nTI/LMI Stellaris information: Chip is "
286 "class %i (%s) %s rev %c%i\n",
288 StellarisClassname[device_class],
289 stellaris_info->target_name,
290 (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
291 (int)((stellaris_info->did0) & 0xFF));
295 printed = snprintf(buf,
297 "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
298 ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
299 stellaris_info->did1,
300 stellaris_info->did1,
302 (int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
303 (int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
307 printed = snprintf(buf,
309 "master clock: %ikHz%s, "
310 "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
311 (int)(stellaris_info->mck_freq / 1000),
312 stellaris_info->mck_desc,
314 stellaris_info->rcc2);
318 if (stellaris_info->num_lockbits > 0)
320 printed = snprintf(buf,
322 "pagesize: %" PRIi32 ", pages: %d, "
323 "lockbits: %i, pages per lockbit: %i\n",
324 stellaris_info->pagesize,
325 (unsigned) stellaris_info->num_pages,
326 stellaris_info->num_lockbits,
327 (unsigned) stellaris_info->pages_in_lockregion);
334 /***************************************************************************
335 * chip identification and status *
336 ***************************************************************************/
338 static uint32_t stellaris_get_flash_status(struct flash_bank *bank)
340 struct target *target = bank->target;
343 target_read_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, &fmc);
348 /* Setup the timimg registers */
349 static void stellaris_set_flash_mode(struct flash_bank *bank,int mode)
351 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
352 struct target *target = bank->target;
353 uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
355 LOG_DEBUG("usecrl = %i",(int)(usecrl));
356 target_write_u32(target, SCB_BASE | USECRL, usecrl);
359 static const unsigned rcc_xtal[32] = {
360 [0x00] = 1000000, /* no pll */
361 [0x01] = 1843200, /* no pll */
362 [0x02] = 2000000, /* no pll */
363 [0x03] = 2457600, /* no pll */
367 [0x06] = 4000000, /* usb */
371 [0x09] = 5000000, /* usb */
373 [0x0b] = 6000000, /* (reset) usb */
377 [0x0e] = 8000000, /* usb */
380 /* parts before DustDevil use just 4 bits for xtal spec */
382 [0x10] = 10000000, /* usb */
383 [0x11] = 12000000, /* usb */
388 [0x15] = 16000000, /* usb */
392 /** Read clock configuration and set stellaris_info->usec_clocks. */
393 static void stellaris_read_clock_info(struct flash_bank *bank)
395 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
396 struct target *target = bank->target;
397 uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
399 unsigned long mainfreq;
401 target_read_u32(target, SCB_BASE | RCC, &rcc);
402 LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
404 target_read_u32(target, SCB_BASE | RCC2, &rcc2);
405 LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
407 target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
408 LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
410 stellaris_info->rcc = rcc;
411 stellaris_info->rcc = rcc2;
413 sysdiv = (rcc >> 23) & 0xF;
414 usesysdiv = (rcc >> 22) & 0x1;
415 bypass = (rcc >> 11) & 0x1;
416 oscsrc = (rcc >> 4) & 0x3;
417 xtal = (rcc >> 6) & stellaris_info->xtal_mask;
419 /* NOTE: post-Sandstorm parts have RCC2 which may override
420 * parts of RCC ... with more sysdiv options, option for
421 * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
422 * as zero, so the "use RCC2" flag is always clear.
424 if (rcc2 & (1 << 31)) {
425 sysdiv = (rcc2 >> 23) & 0x3F;
426 bypass = (rcc2 >> 11) & 0x1;
427 oscsrc = (rcc2 >> 4) & 0x7;
429 /* FIXME Tempest parts have an additional lsb for
430 * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
434 stellaris_info->mck_desc = "";
439 mainfreq = rcc_xtal[xtal];
442 mainfreq = stellaris_info->iosc_freq;
443 stellaris_info->mck_desc = stellaris_info->iosc_desc;
446 mainfreq = stellaris_info->iosc_freq / 4;
447 stellaris_info->mck_desc = stellaris_info->iosc_desc;
449 case 3: /* lowspeed */
450 /* Sandstorm doesn't have this 30K +/- 30% osc */
452 stellaris_info->mck_desc = " (±30%)";
454 case 8: /* hibernation osc */
455 /* not all parts support hibernation */
459 default: /* NOTREACHED */
464 /* PLL is used if it's not bypassed; its output is 200 MHz
465 * even when it runs at 400 MHz (adds divide-by-two stage).
468 mainfreq = 200000000;
471 stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
473 stellaris_info->mck_freq = mainfreq;
475 /* Forget old flash timing */
476 stellaris_set_flash_mode(bank, 0);
480 static uint32_t stellaris_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout)
484 /* Stellaris waits for cmdbit to clear */
485 while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
487 LOG_DEBUG("status: 0x%x", status);
491 /* Flash errors are reflected in the FLASH_CRIS register */
496 /* Send one command to the flash controller */
497 static int stellaris_flash_command(struct flash_bank *bank,uint8_t cmd,uint16_t pagen)
500 struct target *target = bank->target;
502 fmc = FMC_WRKEY | cmd;
503 target_write_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, fmc);
504 LOG_DEBUG("Flash command: 0x%x", fmc);
506 if (stellaris_wait_status_busy(bank, cmd, 100))
508 return ERROR_FLASH_OPERATION_FAILED;
515 /* Read device id register, main clock frequency register and fill in driver info structure */
516 static int stellaris_read_part_info(struct flash_bank *bank)
518 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
519 struct target *target = bank->target;
520 uint32_t did0, did1, ver, fam, status;
523 /* Read and parse chip identification register */
524 target_read_u32(target, SCB_BASE | DID0, &did0);
525 target_read_u32(target, SCB_BASE | DID1, &did1);
526 target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
527 target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
528 LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
529 did0, did1, stellaris_info->dc0, stellaris_info->dc1);
532 if ((ver != 0) && (ver != 1))
534 LOG_WARNING("Unknown did0 version, cannot identify target");
535 return ERROR_FLASH_OPERATION_FAILED;
540 LOG_WARNING("Cannot identify target as a Stellaris");
541 return ERROR_FLASH_OPERATION_FAILED;
545 fam = (did1 >> 24) & 0xF;
546 if (((ver != 0) && (ver != 1)) || (fam != 0))
548 LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
551 /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
552 * is 12 MHz, but some older parts have 15 MHz. A few data sheets
553 * even give _both_ numbers! We'll use current numbers; IOSC is
554 * always approximate.
556 * For Tempest: IOSC is calibrated, 16 MHz
558 stellaris_info->iosc_freq = 12000000;
559 stellaris_info->iosc_desc = " (±30%)";
560 stellaris_info->xtal_mask = 0x0f;
562 switch ((did0 >> 28) & 0x7) {
563 case 0: /* Sandstorm */
565 * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
566 * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
567 * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
569 if (((did0 >> 8) & 0xff) < 2) {
570 stellaris_info->iosc_freq = 15000000;
571 stellaris_info->iosc_desc = " (±50%)";
575 switch ((did0 >> 16) & 0xff) {
578 case 4: /* Tempest */
579 stellaris_info->iosc_freq = 16000000; /* +/- 1% */
580 stellaris_info->iosc_desc = " (±1%)";
582 case 3: /* DustDevil */
583 stellaris_info->xtal_mask = 0x1f;
586 LOG_WARNING("Unknown did0 class");
590 LOG_WARNING("Unknown did0 version");
593 for (i = 0; StellarisParts[i].partno; i++)
595 if (StellarisParts[i].partno == ((did1 >> 16) & 0xFFFF))
599 stellaris_info->target_name = StellarisParts[i].partname;
601 stellaris_info->did0 = did0;
602 stellaris_info->did1 = did1;
604 stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
605 stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF));
606 stellaris_info->pagesize = 1024;
607 bank->size = 1024 * stellaris_info->num_pages;
608 stellaris_info->pages_in_lockregion = 2;
610 /* provide this for the benefit of the higher flash driver layers */
611 bank->num_sectors = stellaris_info->num_pages;
612 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
613 for (i = 0; i < bank->num_sectors; i++)
615 bank->sectors[i].offset = i * stellaris_info->pagesize;
616 bank->sectors[i].size = stellaris_info->pagesize;
617 bank->sectors[i].is_erased = -1;
618 bank->sectors[i].is_protected = -1;
621 /* Read main and master clock freqency register */
622 stellaris_read_clock_info(bank);
624 status = stellaris_get_flash_status(bank);
629 /***************************************************************************
631 ***************************************************************************/
633 static int stellaris_protect_check(struct flash_bank *bank)
635 struct stellaris_flash_bank *stellaris = bank->driver_priv;
636 int status = ERROR_OK;
640 if (stellaris->did1 == 0)
642 status = stellaris_read_part_info(bank);
647 for (i = 0; i < (unsigned) bank->num_sectors; i++)
648 bank->sectors[i].is_protected = -1;
650 /* Read each Flash Memory Protection Program Enable (FMPPE) register
651 * to report any pages that we can't write. Ignore the Read Enable
654 for (i = 0, page = 0;
655 i < DIV_ROUND_UP(stellaris->num_lockbits, 32u);
659 status = target_read_u32(bank->target,
660 SCB_BASE + (i ? (FMPPE0 + 4 * i) : FMPPE),
662 LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i,
663 (unsigned) lockbits, status);
664 if (status != ERROR_OK)
667 for (unsigned j = 0; j < 32; j++) {
670 for (k = 0; k < stellaris->pages_in_lockregion; k++) {
671 if (page >= (unsigned) bank->num_sectors)
673 bank->sectors[page++].is_protected =
674 !(lockbits & (1 << j));
683 static int stellaris_erase(struct flash_bank *bank, int first, int last)
686 uint32_t flash_fmc, flash_cris;
687 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
688 struct target *target = bank->target;
690 if (bank->target->state != TARGET_HALTED)
692 LOG_ERROR("Target not halted");
693 return ERROR_TARGET_NOT_HALTED;
696 if (stellaris_info->did1 == 0)
698 stellaris_read_part_info(bank);
701 if (stellaris_info->did1 == 0)
703 LOG_WARNING("Cannot identify target as Stellaris");
704 return ERROR_FLASH_OPERATION_FAILED;
707 if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
709 return ERROR_FLASH_SECTOR_INVALID;
712 if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
714 return stellaris_mass_erase(bank);
717 /* Configure the flash controller timing */
718 stellaris_read_clock_info(bank);
719 stellaris_set_flash_mode(bank,0);
721 /* Clear and disable flash programming interrupts */
722 target_write_u32(target, FLASH_CIM, 0);
723 target_write_u32(target, FLASH_MISC, PMISC | AMISC);
725 for (banknr = first; banknr <= last; banknr++)
727 /* Address is first word in page */
728 target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
729 /* Write erase command */
730 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
731 /* Wait until erase complete */
734 target_read_u32(target, FLASH_FMC, &flash_fmc);
736 while (flash_fmc & FMC_ERASE);
738 /* Check acess violations */
739 target_read_u32(target, FLASH_CRIS, &flash_cris);
740 if (flash_cris & (AMASK))
742 LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "", banknr, flash_cris);
743 target_write_u32(target, FLASH_CRIS, 0);
744 return ERROR_FLASH_OPERATION_FAILED;
747 bank->sectors[banknr].is_erased = 1;
753 static int stellaris_protect(struct flash_bank *bank, int set, int first, int last)
755 uint32_t fmppe, flash_fmc, flash_cris;
758 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
759 struct target *target = bank->target;
761 if (bank->target->state != TARGET_HALTED)
763 LOG_ERROR("Target not halted");
764 return ERROR_TARGET_NOT_HALTED;
769 LOG_ERROR("Can't unprotect write-protected pages.");
770 /* except by the "recover locked device" procedure ... */
771 return ERROR_INVALID_ARGUMENTS;
774 /* lockregions are 2 pages ... must protect [even..odd] */
775 if ((first < 0) || (first & 1)
776 || (last < first) || !(last & 1)
777 || (last >= 2 * stellaris_info->num_lockbits))
779 LOG_ERROR("Can't protect unaligned or out-of-range sectors.");
780 return ERROR_FLASH_SECTOR_INVALID;
783 if (stellaris_info->did1 == 0)
785 stellaris_read_part_info(bank);
788 if (stellaris_info->did1 == 0)
790 LOG_WARNING("Cannot identify target as an Stellaris MCU");
791 return ERROR_FLASH_OPERATION_FAILED;
794 /* Configure the flash controller timing */
795 stellaris_read_clock_info(bank);
796 stellaris_set_flash_mode(bank, 0);
798 /* convert from pages to lockregions */
802 /* FIXME this assumes single FMPPE, for a max of 64K of flash!!
803 * Current parts can be much bigger.
806 LOG_ERROR("No support yet for protection > 64K");
807 return ERROR_FLASH_OPERATION_FAILED;
810 target_read_u32(target, SCB_BASE | FMPPE, &fmppe);
812 for (lockregion = first; lockregion <= last; lockregion++)
813 fmppe &= ~(1 << lockregion);
815 /* Clear and disable flash programming interrupts */
816 target_write_u32(target, FLASH_CIM, 0);
817 target_write_u32(target, FLASH_MISC, PMISC | AMISC);
819 LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
820 target_write_u32(target, SCB_BASE | FMPPE, fmppe);
823 target_write_u32(target, FLASH_FMA, 1);
825 /* Write commit command */
826 /* REVISIT safety check, since this cannot be undone
827 * except by the "Recover a locked device" procedure.
829 LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
830 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
832 /* Wait until erase complete */
835 target_read_u32(target, FLASH_FMC, &flash_fmc);
837 while (flash_fmc & FMC_COMT);
839 /* Check acess violations */
840 target_read_u32(target, FLASH_CRIS, &flash_cris);
841 if (flash_cris & (AMASK))
843 LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
844 target_write_u32(target, FLASH_CRIS, 0);
845 return ERROR_FLASH_OPERATION_FAILED;
851 static const uint8_t stellaris_write_code[] =
856 r1 = destination address
857 r2 = bytecount (in) - endaddr (work)
860 r3 = pFLASH_CTRL_BASE
866 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
867 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
868 0x01,0x25, /* movs r5, 1 */
869 0x00,0x26, /* movs r6, #0 */
871 0x19,0x60, /* str r1, [r3, #0] */
872 0x87,0x59, /* ldr r7, [r0, r6] */
873 0x5F,0x60, /* str r7, [r3, #4] */
874 0x9C,0x60, /* str r4, [r3, #8] */
876 0x9F,0x68, /* ldr r7, [r3, #8] */
877 0x2F,0x42, /* tst r7, r5 */
878 0xFC,0xD1, /* bne waitloop */
879 0x04,0x31, /* adds r1, r1, #4 */
880 0x04,0x36, /* adds r6, r6, #4 */
881 0x96,0x42, /* cmp r6, r2 */
882 0xF4,0xD1, /* bne mainloop */
884 0xFE,0xE7, /* b exit */
885 /* pFLASH_CTRL_BASE: */
886 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
888 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
891 static int stellaris_write_block(struct flash_bank *bank,
892 uint8_t *buffer, uint32_t offset, uint32_t wcount)
894 struct target *target = bank->target;
895 uint32_t buffer_size = 8192;
896 struct working_area *source;
897 struct working_area *write_algorithm;
898 uint32_t address = bank->base + offset;
899 struct reg_param reg_params[3];
900 struct armv7m_algorithm armv7m_info;
901 int retval = ERROR_OK;
903 LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
904 bank, buffer, offset, wcount);
906 /* flash write code */
907 if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
909 LOG_WARNING("no working area available, can't do block memory writes");
910 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
913 target_write_buffer(target, write_algorithm->address,
914 sizeof(stellaris_write_code),
915 (uint8_t *) stellaris_write_code);
918 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
920 LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08" PRIx32 " source=%p)",
921 target, buffer_size, source);
923 if (buffer_size <= 256)
925 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
927 target_free_working_area(target, write_algorithm);
929 LOG_WARNING("no large enough working area available, can't do block memory writes");
930 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
934 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
935 armv7m_info.core_mode = ARMV7M_MODE_ANY;
937 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
938 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
939 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
943 uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
945 target_write_buffer(target, source->address, thisrun_count * 4, buffer);
947 buf_set_u32(reg_params[0].value, 0, 32, source->address);
948 buf_set_u32(reg_params[1].value, 0, 32, address);
949 buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
950 LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
951 LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
952 if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
954 LOG_ERROR("error executing stellaris flash write algorithm");
955 retval = ERROR_FLASH_OPERATION_FAILED;
959 buffer += thisrun_count * 4;
960 address += thisrun_count * 4;
961 wcount -= thisrun_count;
964 target_free_working_area(target, write_algorithm);
965 target_free_working_area(target, source);
967 destroy_reg_param(®_params[0]);
968 destroy_reg_param(®_params[1]);
969 destroy_reg_param(®_params[2]);
974 static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
976 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
977 struct target *target = bank->target;
978 uint32_t address = offset;
979 uint32_t flash_cris, flash_fmc;
980 uint32_t words_remaining = (count / 4);
981 uint32_t bytes_remaining = (count & 0x00000003);
982 uint32_t bytes_written = 0;
985 if (bank->target->state != TARGET_HALTED)
987 LOG_ERROR("Target not halted");
988 return ERROR_TARGET_NOT_HALTED;
991 LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
992 bank, buffer, offset, count);
994 if (stellaris_info->did1 == 0)
996 stellaris_read_part_info(bank);
999 if (stellaris_info->did1 == 0)
1001 LOG_WARNING("Cannot identify target as a Stellaris processor");
1002 return ERROR_FLASH_OPERATION_FAILED;
1007 LOG_WARNING("offset size must be word aligned");
1008 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1011 if (offset + count > bank->size)
1012 return ERROR_FLASH_DST_OUT_OF_BANK;
1014 /* Configure the flash controller timing */
1015 stellaris_read_clock_info(bank);
1016 stellaris_set_flash_mode(bank, 0);
1018 /* Clear and disable flash programming interrupts */
1019 target_write_u32(target, FLASH_CIM, 0);
1020 target_write_u32(target, FLASH_MISC, PMISC | AMISC);
1022 /* multiple words to be programmed? */
1023 if (words_remaining > 0)
1025 /* try using a block write */
1026 if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
1028 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1030 /* if block write failed (no sufficient working area),
1031 * we use normal (slow) single dword accesses */
1032 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
1034 else if (retval == ERROR_FLASH_OPERATION_FAILED)
1036 /* if an error occured, we examine the reason, and quit */
1037 target_read_u32(target, FLASH_CRIS, &flash_cris);
1039 LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
1040 return ERROR_FLASH_OPERATION_FAILED;
1045 buffer += words_remaining * 4;
1046 address += words_remaining * 4;
1047 words_remaining = 0;
1051 while (words_remaining > 0)
1053 if (!(address & 0xff))
1054 LOG_DEBUG("0x%" PRIx32 "", address);
1056 /* Program one word */
1057 target_write_u32(target, FLASH_FMA, address);
1058 target_write_buffer(target, FLASH_FMD, 4, buffer);
1059 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
1060 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1061 /* Wait until write complete */
1064 target_read_u32(target, FLASH_FMC, &flash_fmc);
1065 } while (flash_fmc & FMC_WRITE);
1072 if (bytes_remaining)
1074 uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
1077 while (bytes_remaining > 0)
1079 last_word[i++] = *(buffer + bytes_written);
1084 if (!(address & 0xff))
1085 LOG_DEBUG("0x%" PRIx32 "", address);
1087 /* Program one word */
1088 target_write_u32(target, FLASH_FMA, address);
1089 target_write_buffer(target, FLASH_FMD, 4, last_word);
1090 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
1091 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1092 /* Wait until write complete */
1095 target_read_u32(target, FLASH_FMC, &flash_fmc);
1096 } while (flash_fmc & FMC_WRITE);
1099 /* Check access violations */
1100 target_read_u32(target, FLASH_CRIS, &flash_cris);
1101 if (flash_cris & (AMASK))
1103 LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
1104 return ERROR_FLASH_OPERATION_FAILED;
1109 static int stellaris_probe(struct flash_bank *bank)
1111 /* we can't probe on an stellaris
1112 * if this is an stellaris, it has the configured flash
1115 if (bank->target->state != TARGET_HALTED)
1117 LOG_ERROR("Target not halted");
1118 return ERROR_TARGET_NOT_HALTED;
1121 /* stellaris_read_part_info() already takes care about error checking and reporting */
1122 return stellaris_read_part_info(bank);
1125 static int stellaris_auto_probe(struct flash_bank *bank)
1127 struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
1128 if (stellaris_info->did1)
1130 return stellaris_probe(bank);
1133 static int stellaris_mass_erase(struct flash_bank *bank)
1135 struct target *target = NULL;
1136 struct stellaris_flash_bank *stellaris_info = NULL;
1139 stellaris_info = bank->driver_priv;
1140 target = bank->target;
1142 if (target->state != TARGET_HALTED)
1144 LOG_ERROR("Target not halted");
1145 return ERROR_TARGET_NOT_HALTED;
1148 if (stellaris_info->did1 == 0)
1150 stellaris_read_part_info(bank);
1153 if (stellaris_info->did1 == 0)
1155 LOG_WARNING("Cannot identify target as Stellaris");
1156 return ERROR_FLASH_OPERATION_FAILED;
1159 /* Configure the flash controller timing */
1160 stellaris_read_clock_info(bank);
1161 stellaris_set_flash_mode(bank, 0);
1163 /* Clear and disable flash programming interrupts */
1164 target_write_u32(target, FLASH_CIM, 0);
1165 target_write_u32(target, FLASH_MISC, PMISC | AMISC);
1167 target_write_u32(target, FLASH_FMA, 0);
1168 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
1169 /* Wait until erase complete */
1172 target_read_u32(target, FLASH_FMC, &flash_fmc);
1174 while (flash_fmc & FMC_MERASE);
1176 /* if device has > 128k, then second erase cycle is needed
1177 * this is only valid for older devices, but will not hurt */
1178 if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
1180 target_write_u32(target, FLASH_FMA, 0x20000);
1181 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
1182 /* Wait until erase complete */
1185 target_read_u32(target, FLASH_FMC, &flash_fmc);
1187 while (flash_fmc & FMC_MERASE);
1193 COMMAND_HANDLER(stellaris_handle_mass_erase_command)
1199 command_print(CMD_CTX, "stellaris mass_erase <bank>");
1203 struct flash_bank *bank;
1204 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1205 if (ERROR_OK != retval)
1208 if (stellaris_mass_erase(bank) == ERROR_OK)
1210 /* set all sectors as erased */
1211 for (i = 0; i < bank->num_sectors; i++)
1213 bank->sectors[i].is_erased = 1;
1216 command_print(CMD_CTX, "stellaris mass erase complete");
1220 command_print(CMD_CTX, "stellaris mass erase failed");
1226 static const struct command_registration stellaris_exec_command_handlers[] = {
1228 .name = "mass_erase",
1229 .handler = &stellaris_handle_mass_erase_command,
1230 .mode = COMMAND_EXEC,
1231 .help = "erase entire device",
1233 COMMAND_REGISTRATION_DONE
1235 static const struct command_registration stellaris_command_handlers[] = {
1237 .name = "stellaris",
1238 .mode = COMMAND_ANY,
1239 .help = "Stellaris flash command group",
1240 .chain = stellaris_exec_command_handlers,
1242 COMMAND_REGISTRATION_DONE
1245 struct flash_driver stellaris_flash = {
1246 .name = "stellaris",
1247 .commands = stellaris_command_handlers,
1248 .flash_bank_command = stellaris_flash_bank_command,
1249 .erase = stellaris_erase,
1250 .protect = stellaris_protect,
1251 .write = stellaris_write,
1252 .probe = stellaris_probe,
1253 .auto_probe = stellaris_auto_probe,
1254 .erase_check = default_flash_mem_blank_check,
1255 .protect_check = stellaris_protect_check,
1256 .info = stellaris_info,