1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
83 /* FLASH_SR register bits */
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
90 /* STM32_FLASH_OBR bit definitions (reading) */
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
99 /* register unlock keys */
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
109 struct stm32x_options {
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
126 int user_data_offset;
128 uint32_t user_bank_size;
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t offset, uint32_t count);
136 /* flash bank stm32x <base> <size> 0 0 <target#>
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
140 struct stm32x_flash_bank *stm32x_info;
143 return ERROR_COMMAND_SYNTAX_ERROR;
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = 0;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
171 struct target *target = bank->target;
173 int retval = ERROR_OK;
175 /* wait for busy to clear */
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
225 static int stm32x_read_options(struct flash_bank *bank)
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
232 /* read user and read protection option bytes */
233 retval = target_read_u32(target, STM32_OB_RDP, &option_bytes);
234 if (retval != ERROR_OK)
237 stm32x_info->option_bytes.rdp = option_bytes & 0xFF;
238 stm32x_info->option_bytes.user = (option_bytes >> 16) & 0xFF;
240 /* read user data option bytes */
241 retval = target_read_u32(target, STM32_OB_DATA0, &option_bytes);
242 if (retval != ERROR_OK)
245 stm32x_info->option_bytes.data = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
247 /* read write protection option bytes */
248 retval = target_read_u32(target, STM32_OB_WRP0, &option_bytes);
249 if (retval != ERROR_OK)
252 stm32x_info->option_bytes.protection = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
254 retval = target_read_u32(target, STM32_OB_WRP2, &option_bytes);
255 if (retval != ERROR_OK)
258 stm32x_info->option_bytes.protection |= (((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF)) << 16;
263 static int stm32x_erase_options(struct flash_bank *bank)
265 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
266 struct target *target = bank->target;
268 /* read current options */
269 stm32x_read_options(bank);
271 /* unlock flash registers */
272 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
273 if (retval != ERROR_OK)
276 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
277 if (retval != ERROR_OK)
280 /* unlock option flash registers */
281 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
282 if (retval != ERROR_OK)
284 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
285 if (retval != ERROR_OK)
288 /* erase option bytes */
289 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
290 if (retval != ERROR_OK)
292 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
293 if (retval != ERROR_OK)
296 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
297 if (retval != ERROR_OK)
300 /* clear read protection option byte
301 * this will also force a device unlock if set */
302 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
307 static int stm32x_write_options(struct flash_bank *bank)
309 struct stm32x_flash_bank *stm32x_info = NULL;
310 struct target *target = bank->target;
312 stm32x_info = bank->driver_priv;
314 /* unlock flash registers */
315 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
316 if (retval != ERROR_OK)
318 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
319 if (retval != ERROR_OK)
322 /* unlock option flash registers */
323 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
324 if (retval != ERROR_OK)
326 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
327 if (retval != ERROR_OK)
330 /* program option bytes */
331 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
332 if (retval != ERROR_OK)
335 uint8_t opt_bytes[16];
337 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
338 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
339 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
340 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
341 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
342 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
343 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
344 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
346 uint32_t offset = STM32_OB_RDP - bank->base;
347 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
348 if (retval != ERROR_OK) {
349 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
350 LOG_ERROR("working area required to erase options bytes");
354 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
355 if (retval != ERROR_OK)
361 static int stm32x_protect_check(struct flash_bank *bank)
363 struct target *target = bank->target;
366 int retval = stm32x_check_operation_supported(bank);
367 if (ERROR_OK != retval)
370 /* medium density - each bit refers to a 4 sector protection block
371 * high density - each bit refers to a 2 sector protection block
372 * bit 31 refers to all remaining sectors in a bank */
373 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
374 if (retval != ERROR_OK)
377 for (int i = 0; i < bank->num_prot_blocks; i++)
378 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
383 static int stm32x_erase(struct flash_bank *bank, int first, int last)
385 struct target *target = bank->target;
388 if (bank->target->state != TARGET_HALTED) {
389 LOG_ERROR("Target not halted");
390 return ERROR_TARGET_NOT_HALTED;
393 if ((first == 0) && (last == (bank->num_sectors - 1)))
394 return stm32x_mass_erase(bank);
396 /* unlock flash registers */
397 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
398 if (retval != ERROR_OK)
400 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
401 if (retval != ERROR_OK)
404 for (i = first; i <= last; i++) {
405 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
406 if (retval != ERROR_OK)
408 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
409 bank->base + bank->sectors[i].offset);
410 if (retval != ERROR_OK)
412 retval = target_write_u32(target,
413 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
414 if (retval != ERROR_OK)
417 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
418 if (retval != ERROR_OK)
421 bank->sectors[i].is_erased = 1;
424 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
425 if (retval != ERROR_OK)
431 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
433 struct target *target = bank->target;
434 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
436 if (target->state != TARGET_HALTED) {
437 LOG_ERROR("Target not halted");
438 return ERROR_TARGET_NOT_HALTED;
441 int retval = stm32x_check_operation_supported(bank);
442 if (retval != ERROR_OK)
445 retval = stm32x_erase_options(bank);
446 if (retval != ERROR_OK)
449 for (int i = first; i <= last; i++) {
451 stm32x_info->option_bytes.protection &= ~(1 << i);
453 stm32x_info->option_bytes.protection |= (1 << i);
456 return stm32x_write_options(bank);
459 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
460 uint32_t offset, uint32_t count)
462 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
463 struct target *target = bank->target;
464 uint32_t buffer_size = 16384;
465 struct working_area *write_algorithm;
466 struct working_area *source;
467 uint32_t address = bank->base + offset;
468 struct reg_param reg_params[5];
469 struct armv7m_algorithm armv7m_info;
470 int retval = ERROR_OK;
472 static const uint8_t stm32x_flash_write_code[] = {
473 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
476 /* flash write code */
477 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
478 &write_algorithm) != ERROR_OK) {
479 LOG_WARNING("no working area available, can't do block memory writes");
480 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
483 retval = target_write_buffer(target, write_algorithm->address,
484 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
485 if (retval != ERROR_OK) {
486 target_free_working_area(target, write_algorithm);
491 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
493 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
494 if (buffer_size <= 256) {
495 /* we already allocated the writing code, but failed to get a
496 * buffer, free the algorithm */
497 target_free_working_area(target, write_algorithm);
499 LOG_WARNING("no large enough working area available, can't do block memory writes");
500 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
504 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
505 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
506 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
507 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
508 init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
510 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
511 buf_set_u32(reg_params[1].value, 0, 32, count);
512 buf_set_u32(reg_params[2].value, 0, 32, source->address);
513 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
514 buf_set_u32(reg_params[4].value, 0, 32, address);
516 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
517 armv7m_info.core_mode = ARM_MODE_THREAD;
519 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
522 source->address, source->size,
523 write_algorithm->address, 0,
526 if (retval == ERROR_FLASH_OPERATION_FAILED) {
527 LOG_ERROR("flash write failed at address 0x%"PRIx32,
528 buf_get_u32(reg_params[4].value, 0, 32));
530 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
531 LOG_ERROR("flash memory not erased before writing");
532 /* Clear but report errors */
533 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
536 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
537 LOG_ERROR("flash memory write protected");
538 /* Clear but report errors */
539 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
543 target_free_working_area(target, source);
544 target_free_working_area(target, write_algorithm);
546 destroy_reg_param(®_params[0]);
547 destroy_reg_param(®_params[1]);
548 destroy_reg_param(®_params[2]);
549 destroy_reg_param(®_params[3]);
550 destroy_reg_param(®_params[4]);
555 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
556 uint32_t offset, uint32_t count)
558 struct target *target = bank->target;
559 uint8_t *new_buffer = NULL;
561 if (bank->target->state != TARGET_HALTED) {
562 LOG_ERROR("Target not halted");
563 return ERROR_TARGET_NOT_HALTED;
567 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
568 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
571 /* If there's an odd number of bytes, the data has to be padded. Duplicate
572 * the buffer and use the normal code path with a single block write since
573 * it's probably cheaper than to special case the last odd write using
574 * discrete accesses. */
576 new_buffer = malloc(count + 1);
577 if (new_buffer == NULL) {
578 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
581 LOG_INFO("odd number of bytes to write, padding with 0xff");
582 buffer = memcpy(new_buffer, buffer, count);
583 new_buffer[count++] = 0xff;
586 uint32_t words_remaining = count / 2;
589 /* unlock flash registers */
590 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
591 if (retval != ERROR_OK)
593 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
594 if (retval != ERROR_OK)
597 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
598 if (retval != ERROR_OK)
601 /* try using a block write */
602 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
604 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
605 /* if block write failed (no sufficient working area),
606 * we use normal (slow) single halfword accesses */
607 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
609 while (words_remaining > 0) {
611 memcpy(&value, buffer, sizeof(uint16_t));
613 retval = target_write_u16(target, bank->base + offset, value);
614 if (retval != ERROR_OK)
615 goto reset_pg_and_lock;
617 retval = stm32x_wait_status_busy(bank, 5);
618 if (retval != ERROR_OK)
619 goto reset_pg_and_lock;
628 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
629 if (retval == ERROR_OK)
639 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
641 /* This check the device CPUID core register to detect
642 * the M0 from the M3 devices. */
644 struct target *target = bank->target;
645 uint32_t cpuid, device_id_register = 0;
647 /* Get the CPUID from the ARM Core
648 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
649 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
650 if (retval != ERROR_OK)
653 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
654 /* 0xC20 is M0 devices */
655 device_id_register = 0x40015800;
656 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
657 /* 0xC23 is M3 devices */
658 device_id_register = 0xE0042000;
659 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
660 /* 0xC24 is M4 devices */
661 device_id_register = 0xE0042000;
663 LOG_ERROR("Cannot identify target as a stm32x");
667 /* read stm32 device id register */
668 retval = target_read_u32(target, device_id_register, device_id);
669 if (retval != ERROR_OK)
675 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
677 struct target *target = bank->target;
678 uint32_t cpuid, flash_size_reg;
680 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
681 if (retval != ERROR_OK)
684 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
685 /* 0xC20 is M0 devices */
686 flash_size_reg = 0x1FFFF7CC;
687 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
688 /* 0xC23 is M3 devices */
689 flash_size_reg = 0x1FFFF7E0;
690 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
691 /* 0xC24 is M4 devices */
692 flash_size_reg = 0x1FFFF7CC;
694 LOG_ERROR("Cannot identify target as a stm32x");
698 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
699 if (retval != ERROR_OK)
705 static int stm32x_probe(struct flash_bank *bank)
707 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
708 uint16_t flash_size_in_kb;
709 uint16_t max_flash_size_in_kb;
712 uint32_t base_address = 0x08000000;
714 stm32x_info->probed = 0;
715 stm32x_info->register_base = FLASH_REG_BASE_B0;
716 stm32x_info->user_data_offset = 10;
717 stm32x_info->option_offset = 0;
719 /* default factory read protection level 0 */
720 stm32x_info->default_rdp = 0xA5;
722 /* read stm32 device id register */
723 int retval = stm32x_get_device_id(bank, &device_id);
724 if (retval != ERROR_OK)
727 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
729 /* set page size, protection granularity and max flash size depending on family */
730 switch (device_id & 0xfff) {
731 case 0x410: /* medium density */
733 stm32x_info->ppage_size = 4;
734 max_flash_size_in_kb = 128;
736 case 0x412: /* low density */
738 stm32x_info->ppage_size = 4;
739 max_flash_size_in_kb = 32;
741 case 0x414: /* high density */
743 stm32x_info->ppage_size = 2;
744 max_flash_size_in_kb = 512;
746 case 0x418: /* connectivity line density */
748 stm32x_info->ppage_size = 2;
749 max_flash_size_in_kb = 256;
751 case 0x420: /* value line density */
753 stm32x_info->ppage_size = 4;
754 max_flash_size_in_kb = 128;
756 case 0x422: /* stm32f302/3xb/c */
758 stm32x_info->ppage_size = 2;
759 max_flash_size_in_kb = 256;
760 stm32x_info->user_data_offset = 16;
761 stm32x_info->option_offset = 6;
762 stm32x_info->default_rdp = 0xAA;
763 stm32x_info->can_load_options = true;
765 case 0x446: /* stm32f303xD/E */
767 stm32x_info->ppage_size = 2;
768 max_flash_size_in_kb = 512;
769 stm32x_info->user_data_offset = 16;
770 stm32x_info->option_offset = 6;
771 stm32x_info->default_rdp = 0xAA;
772 stm32x_info->can_load_options = true;
774 case 0x428: /* value line High density */
776 stm32x_info->ppage_size = 4;
777 max_flash_size_in_kb = 128;
779 case 0x430: /* xl line density (dual flash banks) */
781 stm32x_info->ppage_size = 2;
782 max_flash_size_in_kb = 1024;
783 stm32x_info->has_dual_banks = true;
785 case 0x432: /* stm32f37x */
787 stm32x_info->ppage_size = 2;
788 max_flash_size_in_kb = 256;
789 stm32x_info->user_data_offset = 16;
790 stm32x_info->option_offset = 6;
791 stm32x_info->default_rdp = 0xAA;
792 stm32x_info->can_load_options = true;
794 case 0x438: /* stm32f33x */
795 case 0x439: /* stm32f302x6/8 */
797 stm32x_info->ppage_size = 2;
798 max_flash_size_in_kb = 64;
799 stm32x_info->user_data_offset = 16;
800 stm32x_info->option_offset = 6;
801 stm32x_info->default_rdp = 0xAA;
802 stm32x_info->can_load_options = true;
804 case 0x440: /* stm32f05x */
805 case 0x444: /* stm32f03x */
806 case 0x445: /* stm32f04x */
808 stm32x_info->ppage_size = 4;
809 max_flash_size_in_kb = 64;
810 stm32x_info->user_data_offset = 16;
811 stm32x_info->option_offset = 6;
812 stm32x_info->default_rdp = 0xAA;
813 stm32x_info->can_load_options = true;
815 case 0x448: /* stm32f07x */
816 case 0x442: /* stm32f09x */
818 stm32x_info->ppage_size = 4;
819 max_flash_size_in_kb = 256;
820 stm32x_info->user_data_offset = 16;
821 stm32x_info->option_offset = 6;
822 stm32x_info->default_rdp = 0xAA;
823 stm32x_info->can_load_options = true;
826 LOG_WARNING("Cannot identify target as a STM32 family.");
830 /* get flash size from target. */
831 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
833 /* failed reading flash size or flash size invalid (early silicon),
834 * default to max target family */
835 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
836 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
837 max_flash_size_in_kb);
838 flash_size_in_kb = max_flash_size_in_kb;
841 if (stm32x_info->has_dual_banks) {
842 /* split reported size into matching bank */
843 if (bank->base != 0x08080000) {
844 /* bank 0 will be fixed 512k */
845 flash_size_in_kb = 512;
847 flash_size_in_kb -= 512;
848 /* bank1 also uses a register offset */
849 stm32x_info->register_base = FLASH_REG_BASE_B1;
850 base_address = 0x08080000;
854 /* if the user sets the size manually then ignore the probed value
855 * this allows us to work around devices that have a invalid flash size register value */
856 if (stm32x_info->user_bank_size) {
857 LOG_INFO("ignoring flash probed value, using configured bank size");
858 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
861 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
863 /* did we assign flash size? */
864 assert(flash_size_in_kb != 0xffff);
866 /* calculate numbers of pages */
867 int num_pages = flash_size_in_kb * 1024 / page_size;
869 /* check that calculation result makes sense */
870 assert(num_pages > 0);
874 bank->sectors = NULL;
877 if (bank->prot_blocks) {
878 free(bank->prot_blocks);
879 bank->prot_blocks = NULL;
882 bank->base = base_address;
883 bank->size = (num_pages * page_size);
885 bank->num_sectors = num_pages;
886 bank->sectors = alloc_block_array(0, page_size, num_pages);
890 /* calculate number of write protection blocks */
891 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
892 if (num_prot_blocks > 32)
893 num_prot_blocks = 32;
895 bank->num_prot_blocks = num_prot_blocks;
896 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
897 if (!bank->prot_blocks)
900 if (num_prot_blocks == 32)
901 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
903 stm32x_info->probed = 1;
908 static int stm32x_auto_probe(struct flash_bank *bank)
910 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
911 if (stm32x_info->probed)
913 return stm32x_probe(bank);
917 COMMAND_HANDLER(stm32x_handle_part_id_command)
923 static const char *get_stm32f0_revision(uint16_t rev_id)
925 const char *rev_str = NULL;
938 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
940 uint32_t dbgmcu_idcode;
942 /* read stm32 device id register */
943 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
944 if (retval != ERROR_OK)
947 uint16_t device_id = dbgmcu_idcode & 0xfff;
948 uint16_t rev_id = dbgmcu_idcode >> 16;
949 const char *device_str;
950 const char *rev_str = NULL;
954 device_str = "STM32F10x (Medium Density)";
976 device_str = "STM32F10x (Low Density)";
986 device_str = "STM32F10x (High Density)";
1004 device_str = "STM32F10x (Connectivity)";
1018 device_str = "STM32F100 (Low/Medium Density)";
1032 device_str = "STM32F302xB/C";
1054 device_str = "STM32F100 (High Density)";
1068 device_str = "STM32F10x (XL Density)";
1078 device_str = "STM32F37x";
1092 device_str = "STM32F33x";
1102 device_str = "STM32F302x6/8";
1116 device_str = "STM32F03x";
1117 rev_str = get_stm32f0_revision(rev_id);
1121 device_str = "STM32F05x";
1122 rev_str = get_stm32f0_revision(rev_id);
1126 device_str = "STM32F04x";
1127 rev_str = get_stm32f0_revision(rev_id);
1131 device_str = "STM32F303xD/E";
1140 device_str = "STM32F07x";
1141 rev_str = get_stm32f0_revision(rev_id);
1145 device_str = "STM32F09x";
1146 rev_str = get_stm32f0_revision(rev_id);
1150 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1154 if (rev_str != NULL)
1155 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1157 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1162 COMMAND_HANDLER(stm32x_handle_lock_command)
1164 struct target *target = NULL;
1165 struct stm32x_flash_bank *stm32x_info = NULL;
1168 return ERROR_COMMAND_SYNTAX_ERROR;
1170 struct flash_bank *bank;
1171 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1172 if (ERROR_OK != retval)
1175 stm32x_info = bank->driver_priv;
1177 target = bank->target;
1179 if (target->state != TARGET_HALTED) {
1180 LOG_ERROR("Target not halted");
1181 return ERROR_TARGET_NOT_HALTED;
1184 retval = stm32x_check_operation_supported(bank);
1185 if (ERROR_OK != retval)
1188 if (stm32x_erase_options(bank) != ERROR_OK) {
1189 command_print(CMD_CTX, "stm32x failed to erase options");
1193 /* set readout protection */
1194 stm32x_info->option_bytes.rdp = 0;
1196 if (stm32x_write_options(bank) != ERROR_OK) {
1197 command_print(CMD_CTX, "stm32x failed to lock device");
1201 command_print(CMD_CTX, "stm32x locked");
1206 COMMAND_HANDLER(stm32x_handle_unlock_command)
1208 struct target *target = NULL;
1211 return ERROR_COMMAND_SYNTAX_ERROR;
1213 struct flash_bank *bank;
1214 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1215 if (ERROR_OK != retval)
1218 target = bank->target;
1220 if (target->state != TARGET_HALTED) {
1221 LOG_ERROR("Target not halted");
1222 return ERROR_TARGET_NOT_HALTED;
1225 retval = stm32x_check_operation_supported(bank);
1226 if (ERROR_OK != retval)
1229 if (stm32x_erase_options(bank) != ERROR_OK) {
1230 command_print(CMD_CTX, "stm32x failed to unlock device");
1234 if (stm32x_write_options(bank) != ERROR_OK) {
1235 command_print(CMD_CTX, "stm32x failed to lock device");
1239 command_print(CMD_CTX, "stm32x unlocked.\n"
1240 "INFO: a reset or power cycle is required "
1241 "for the new settings to take effect.");
1246 COMMAND_HANDLER(stm32x_handle_options_read_command)
1248 uint32_t optionbyte, protection;
1249 struct target *target = NULL;
1250 struct stm32x_flash_bank *stm32x_info = NULL;
1253 return ERROR_COMMAND_SYNTAX_ERROR;
1255 struct flash_bank *bank;
1256 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1257 if (ERROR_OK != retval)
1260 stm32x_info = bank->driver_priv;
1262 target = bank->target;
1264 if (target->state != TARGET_HALTED) {
1265 LOG_ERROR("Target not halted");
1266 return ERROR_TARGET_NOT_HALTED;
1269 retval = stm32x_check_operation_supported(bank);
1270 if (ERROR_OK != retval)
1273 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1274 if (retval != ERROR_OK)
1277 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1279 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1280 if (retval != ERROR_OK)
1283 if (optionbyte & (1 << OPT_ERROR))
1284 command_print(CMD_CTX, "option byte complement error");
1286 command_print(CMD_CTX, "option byte register = 0x%" PRIx32 "", optionbyte);
1287 command_print(CMD_CTX, "write protection register = 0x%" PRIx32 "", protection);
1289 command_print(CMD_CTX, "read protection: %s",
1290 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1292 /* user option bytes are offset depending on variant */
1293 optionbyte >>= stm32x_info->option_offset;
1295 command_print(CMD_CTX, "watchdog: %sware",
1296 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1298 command_print(CMD_CTX, "stop mode: %sreset generated upon entry",
1299 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1301 command_print(CMD_CTX, "standby mode: %sreset generated upon entry",
1302 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1304 if (stm32x_info->has_dual_banks)
1305 command_print(CMD_CTX, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1307 command_print(CMD_CTX, "user data = 0x%02" PRIx16 "", user_data);
1312 COMMAND_HANDLER(stm32x_handle_options_write_command)
1314 struct target *target = NULL;
1315 struct stm32x_flash_bank *stm32x_info = NULL;
1316 uint16_t optionbyte;
1319 return ERROR_COMMAND_SYNTAX_ERROR;
1321 struct flash_bank *bank;
1322 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1323 if (ERROR_OK != retval)
1326 stm32x_info = bank->driver_priv;
1328 target = bank->target;
1330 if (target->state != TARGET_HALTED) {
1331 LOG_ERROR("Target not halted");
1332 return ERROR_TARGET_NOT_HALTED;
1335 retval = stm32x_check_operation_supported(bank);
1336 if (ERROR_OK != retval)
1339 retval = stm32x_read_options(bank);
1340 if (ERROR_OK != retval)
1343 /* start with current options */
1344 optionbyte = stm32x_info->option_bytes.user;
1346 /* skip over flash bank */
1351 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1352 optionbyte |= (1 << 0);
1353 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1354 optionbyte &= ~(1 << 0);
1355 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1356 optionbyte |= (1 << 1);
1357 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1358 optionbyte &= ~(1 << 1);
1359 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1360 optionbyte |= (1 << 2);
1361 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1362 optionbyte &= ~(1 << 2);
1363 else if (stm32x_info->has_dual_banks) {
1364 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1365 optionbyte |= (1 << 3);
1366 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1367 optionbyte &= ~(1 << 3);
1369 return ERROR_COMMAND_SYNTAX_ERROR;
1371 return ERROR_COMMAND_SYNTAX_ERROR;
1376 if (stm32x_erase_options(bank) != ERROR_OK) {
1377 command_print(CMD_CTX, "stm32x failed to erase options");
1381 stm32x_info->option_bytes.user = optionbyte;
1383 if (stm32x_write_options(bank) != ERROR_OK) {
1384 command_print(CMD_CTX, "stm32x failed to write options");
1388 command_print(CMD_CTX, "stm32x write options complete.\n"
1389 "INFO: %spower cycle is required "
1390 "for the new settings to take effect.",
1391 stm32x_info->can_load_options
1392 ? "'stm32f1x options_load' command or " : "");
1397 COMMAND_HANDLER(stm32x_handle_options_load_command)
1400 return ERROR_COMMAND_SYNTAX_ERROR;
1402 struct flash_bank *bank;
1403 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1404 if (ERROR_OK != retval)
1407 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1409 if (!stm32x_info->can_load_options) {
1410 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1411 "required instead.");
1415 struct target *target = bank->target;
1417 if (target->state != TARGET_HALTED) {
1418 LOG_ERROR("Target not halted");
1419 return ERROR_TARGET_NOT_HALTED;
1422 retval = stm32x_check_operation_supported(bank);
1423 if (ERROR_OK != retval)
1426 /* unlock option flash registers */
1427 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1428 if (retval != ERROR_OK)
1430 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1431 if (retval != ERROR_OK)
1434 /* force re-load of option bytes - generates software reset */
1435 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1436 if (retval != ERROR_OK)
1442 static int stm32x_mass_erase(struct flash_bank *bank)
1444 struct target *target = bank->target;
1446 if (target->state != TARGET_HALTED) {
1447 LOG_ERROR("Target not halted");
1448 return ERROR_TARGET_NOT_HALTED;
1451 /* unlock option flash registers */
1452 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1453 if (retval != ERROR_OK)
1455 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1456 if (retval != ERROR_OK)
1459 /* mass erase flash memory */
1460 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1461 if (retval != ERROR_OK)
1463 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1464 FLASH_MER | FLASH_STRT);
1465 if (retval != ERROR_OK)
1468 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1469 if (retval != ERROR_OK)
1472 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1473 if (retval != ERROR_OK)
1479 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1484 return ERROR_COMMAND_SYNTAX_ERROR;
1486 struct flash_bank *bank;
1487 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1488 if (ERROR_OK != retval)
1491 retval = stm32x_mass_erase(bank);
1492 if (retval == ERROR_OK) {
1493 /* set all sectors as erased */
1494 for (i = 0; i < bank->num_sectors; i++)
1495 bank->sectors[i].is_erased = 1;
1497 command_print(CMD_CTX, "stm32x mass erase complete");
1499 command_print(CMD_CTX, "stm32x mass erase failed");
1504 static const struct command_registration stm32x_exec_command_handlers[] = {
1507 .handler = stm32x_handle_lock_command,
1508 .mode = COMMAND_EXEC,
1510 .help = "Lock entire flash device.",
1514 .handler = stm32x_handle_unlock_command,
1515 .mode = COMMAND_EXEC,
1517 .help = "Unlock entire protected flash device.",
1520 .name = "mass_erase",
1521 .handler = stm32x_handle_mass_erase_command,
1522 .mode = COMMAND_EXEC,
1524 .help = "Erase entire flash device.",
1527 .name = "options_read",
1528 .handler = stm32x_handle_options_read_command,
1529 .mode = COMMAND_EXEC,
1531 .help = "Read and display device option bytes.",
1534 .name = "options_write",
1535 .handler = stm32x_handle_options_write_command,
1536 .mode = COMMAND_EXEC,
1537 .usage = "bank_id ('SWWDG'|'HWWDG') "
1538 "('RSTSTNDBY'|'NORSTSTNDBY') "
1539 "('RSTSTOP'|'NORSTSTOP')",
1540 .help = "Replace bits in device option bytes.",
1543 .name = "options_load",
1544 .handler = stm32x_handle_options_load_command,
1545 .mode = COMMAND_EXEC,
1547 .help = "Force re-load of device option bytes.",
1549 COMMAND_REGISTRATION_DONE
1552 static const struct command_registration stm32x_command_handlers[] = {
1555 .mode = COMMAND_ANY,
1556 .help = "stm32f1x flash command group",
1558 .chain = stm32x_exec_command_handlers,
1560 COMMAND_REGISTRATION_DONE
1563 struct flash_driver stm32f1x_flash = {
1565 .commands = stm32x_command_handlers,
1566 .flash_bank_command = stm32x_flash_bank_command,
1567 .erase = stm32x_erase,
1568 .protect = stm32x_protect,
1569 .write = stm32x_write,
1570 .read = default_flash_read,
1571 .probe = stm32x_probe,
1572 .auto_probe = stm32x_auto_probe,
1573 .erase_check = default_flash_blank_check,
1574 .protect_check = stm32x_protect_check,
1575 .info = get_stm32x_info,
1576 .free_driver_priv = default_flash_free_driver_priv,