1 /***************************************************************************
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2 * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
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3 * Written by Nicolas Pitre <nico at marvell.com> *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
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22 * NAND controller interface for Marvell Orion/Kirkwood SoCs.
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25 #ifdef HAVE_CONFIG_H
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29 #include "replacements.h"
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37 #include "armv4_5.h"
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38 #include "binarybuffer.h"
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40 typedef struct orion_nand_controller_s
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42 struct target_s *target;
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43 working_area_t *copy_area;
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48 } orion_nand_controller_t;
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50 #define CHECK_HALTED \
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52 if (target->state != TARGET_HALTED) { \
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53 LOG_ERROR("NAND flash access requires halted target"); \
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54 return ERROR_NAND_OPERATION_FAILED; \
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58 int orion_nand_command(struct nand_device_s *device, u8 command)
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60 orion_nand_controller_t *hw = device->controller_priv;
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61 target_t *target = hw->target;
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64 target_write_u8(target, hw->cmd, command);
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68 int orion_nand_address(struct nand_device_s *device, u8 address)
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70 orion_nand_controller_t *hw = device->controller_priv;
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71 target_t *target = hw->target;
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74 target_write_u8(target, hw->addr, address);
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78 int orion_nand_read(struct nand_device_s *device, void *data)
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80 orion_nand_controller_t *hw = device->controller_priv;
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81 target_t *target = hw->target;
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84 target_read_u8(target, hw->data, data);
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88 int orion_nand_write(struct nand_device_s *device, u16 data)
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90 orion_nand_controller_t *hw = device->controller_priv;
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91 target_t *target = hw->target;
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94 target_write_u8(target, hw->data, data);
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98 int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
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101 orion_nand_write(device, *data++);
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105 int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
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107 orion_nand_controller_t *hw = device->controller_priv;
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108 target_t *target = hw->target;
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109 armv4_5_algorithm_t algo;
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110 reg_param_t reg_params[3];
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114 static const u32 code[] = {
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115 0xe4d13001, /* ldrb r3, [r1], #1 */
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116 0xe5c03000, /* strb r3, [r0] */
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117 0xe2522001, /* subs r2, r2, #1 */
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118 0x1afffffb, /* bne 0 */
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119 0xeafffffe, /* b . */
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121 int code_size = sizeof(code);
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123 if (!hw->copy_area) {
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124 u8 code_buf[code_size];
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127 /* make sure we have a working area */
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128 if (target_alloc_working_area(target,
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129 code_size + device->page_size,
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130 &hw->copy_area) != ERROR_OK)
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132 return orion_nand_slow_block_write(device, data, size);
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135 /* copy target instructions to target endianness */
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136 for (i = 0; i < code_size/4; i++)
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137 target_buffer_set_u32(target, code_buf + i*4, code[i]);
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139 /* write code to working area */
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140 retval = target->type->write_memory(target,
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141 hw->copy_area->address,
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142 4, code_size/4, code_buf);
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143 if (retval != ERROR_OK)
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147 /* copy data to target's memory */
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148 target_buf = hw->copy_area->address + code_size;
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149 retval = target->type->bulk_write_memory(target, target_buf,
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151 if (retval == ERROR_OK && size & 3) {
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152 retval = target->type->write_memory(target,
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153 target_buf + (size & ~3),
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154 1, size & 3, data + (size & ~3));
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156 if (retval != ERROR_OK)
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159 algo.common_magic = ARMV4_5_COMMON_MAGIC;
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160 algo.core_mode = ARMV4_5_MODE_SVC;
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161 algo.core_state = ARMV4_5_STATE_ARM;
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163 init_reg_param(®_params[0], "r0", 32, PARAM_IN);
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164 init_reg_param(®_params[1], "r1", 32, PARAM_IN);
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165 init_reg_param(®_params[2], "r2", 32, PARAM_IN);
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167 buf_set_u32(reg_params[0].value, 0, 32, hw->data);
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168 buf_set_u32(reg_params[1].value, 0, 32, target_buf);
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169 buf_set_u32(reg_params[2].value, 0, 32, size);
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171 retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
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172 hw->copy_area->address,
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173 hw->copy_area->address + code_size - 4,
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175 if (retval != ERROR_OK)
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176 LOG_ERROR("error executing hosted NAND write");
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178 destroy_reg_param(®_params[0]);
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179 destroy_reg_param(®_params[1]);
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180 destroy_reg_param(®_params[2]);
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184 int orion_nand_reset(struct nand_device_s *device)
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186 return orion_nand_command(device, NAND_CMD_RESET);
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189 int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
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194 int orion_nand_register_commands(struct command_context_s *cmd_ctx)
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199 int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
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200 char **args, int argc,
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201 struct nand_device_s *device)
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203 orion_nand_controller_t *hw;
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208 LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
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209 return ERROR_NAND_DEVICE_INVALID;
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212 hw = calloc(1, sizeof(*hw));
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214 LOG_ERROR("no memory for nand controller\n");
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215 return ERROR_NAND_DEVICE_INVALID;
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218 device->controller_priv = hw;
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219 hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
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221 LOG_ERROR("no target '%s' configured", args[1]);
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223 return ERROR_NAND_DEVICE_INVALID;
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226 base = strtoul(args[2], NULL, 0);
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231 hw->cmd = base + (1 << cle);
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232 hw->addr = base + (1 << ale);
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237 int orion_nand_init(struct nand_device_s *device)
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242 nand_flash_controller_t orion_nand_controller =
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245 .command = orion_nand_command,
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246 .address = orion_nand_address,
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247 .read_data = orion_nand_read,
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248 .write_data = orion_nand_write,
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249 .write_block_data = orion_nand_fast_block_write,
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250 .reset = orion_nand_reset,
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251 .controller_ready = orion_nand_controller_ready,
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252 .nand_device_command = orion_nand_device_command,
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253 .register_commands = orion_nand_register_commands,
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254 .init = orion_nand_init,
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