1 /***************************************************************************
2 * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico at marvell.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * NAND controller interface for Marvell Orion/Kirkwood SoCs.
31 #include "binarybuffer.h"
34 typedef struct orion_nand_controller_s
36 struct target_s *target;
37 working_area_t *copy_area;
42 } orion_nand_controller_t;
44 #define CHECK_HALTED \
46 if (target->state != TARGET_HALTED) { \
47 LOG_ERROR("NAND flash access requires halted target"); \
48 return ERROR_NAND_OPERATION_FAILED; \
52 static int orion_nand_command(struct nand_device_s *device, u8 command)
54 orion_nand_controller_t *hw = device->controller_priv;
55 target_t *target = hw->target;
58 target_write_u8(target, hw->cmd, command);
62 static int orion_nand_address(struct nand_device_s *device, u8 address)
64 orion_nand_controller_t *hw = device->controller_priv;
65 target_t *target = hw->target;
68 target_write_u8(target, hw->addr, address);
72 static int orion_nand_read(struct nand_device_s *device, void *data)
74 orion_nand_controller_t *hw = device->controller_priv;
75 target_t *target = hw->target;
78 target_read_u8(target, hw->data, data);
82 static int orion_nand_write(struct nand_device_s *device, u16 data)
84 orion_nand_controller_t *hw = device->controller_priv;
85 target_t *target = hw->target;
88 target_write_u8(target, hw->data, data);
92 static int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
95 orion_nand_write(device, *data++);
99 static int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
101 orion_nand_controller_t *hw = device->controller_priv;
102 target_t *target = hw->target;
103 armv4_5_algorithm_t algo;
104 reg_param_t reg_params[3];
108 static const u32 code[] = {
109 0xe4d13001, /* ldrb r3, [r1], #1 */
110 0xe5c03000, /* strb r3, [r0] */
111 0xe2522001, /* subs r2, r2, #1 */
112 0x1afffffb, /* bne 0 */
113 0xeafffffe, /* b . */
115 int code_size = sizeof(code);
117 if (!hw->copy_area) {
118 u8 code_buf[code_size];
121 /* make sure we have a working area */
122 if (target_alloc_working_area(target,
123 code_size + device->page_size,
124 &hw->copy_area) != ERROR_OK)
126 return orion_nand_slow_block_write(device, data, size);
129 /* copy target instructions to target endianness */
130 for (i = 0; i < code_size/4; i++)
131 target_buffer_set_u32(target, code_buf + i*4, code[i]);
133 /* write code to working area */
134 retval = target_write_memory(target,
135 hw->copy_area->address,
136 4, code_size/4, code_buf);
137 if (retval != ERROR_OK)
141 /* copy data to target's memory */
142 target_buf = hw->copy_area->address + code_size;
143 retval = target->type->bulk_write_memory(target, target_buf,
145 if (retval == ERROR_OK && size & 3) {
146 retval = target_write_memory(target,
147 target_buf + (size & ~3),
148 1, size & 3, data + (size & ~3));
150 if (retval != ERROR_OK)
153 algo.common_magic = ARMV4_5_COMMON_MAGIC;
154 algo.core_mode = ARMV4_5_MODE_SVC;
155 algo.core_state = ARMV4_5_STATE_ARM;
157 init_reg_param(®_params[0], "r0", 32, PARAM_IN);
158 init_reg_param(®_params[1], "r1", 32, PARAM_IN);
159 init_reg_param(®_params[2], "r2", 32, PARAM_IN);
161 buf_set_u32(reg_params[0].value, 0, 32, hw->data);
162 buf_set_u32(reg_params[1].value, 0, 32, target_buf);
163 buf_set_u32(reg_params[2].value, 0, 32, size);
165 retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
166 hw->copy_area->address,
167 hw->copy_area->address + code_size - 4,
169 if (retval != ERROR_OK)
170 LOG_ERROR("error executing hosted NAND write");
172 destroy_reg_param(®_params[0]);
173 destroy_reg_param(®_params[1]);
174 destroy_reg_param(®_params[2]);
178 static int orion_nand_reset(struct nand_device_s *device)
180 return orion_nand_command(device, NAND_CMD_RESET);
183 static int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
188 static int orion_nand_register_commands(struct command_context_s *cmd_ctx)
193 int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
194 char **args, int argc,
195 struct nand_device_s *device)
197 orion_nand_controller_t *hw;
202 LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
203 return ERROR_NAND_DEVICE_INVALID;
206 hw = calloc(1, sizeof(*hw));
208 LOG_ERROR("no memory for nand controller\n");
209 return ERROR_NAND_DEVICE_INVALID;
212 device->controller_priv = hw;
213 hw->target = get_target(args[1]);
215 LOG_ERROR("target '%s' not defined", args[1]);
217 return ERROR_NAND_DEVICE_INVALID;
220 base = strtoul(args[2], NULL, 0);
225 hw->cmd = base + (1 << cle);
226 hw->addr = base + (1 << ale);
231 static int orion_nand_init(struct nand_device_s *device)
236 nand_flash_controller_t orion_nand_controller =
239 .command = orion_nand_command,
240 .address = orion_nand_address,
241 .read_data = orion_nand_read,
242 .write_data = orion_nand_write,
243 .write_block_data = orion_nand_fast_block_write,
244 .reset = orion_nand_reset,
245 .controller_ready = orion_nand_controller_ready,
246 .nand_device_command = orion_nand_device_command,
247 .register_commands = orion_nand_register_commands,
248 .init = orion_nand_init,