1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by John McCarthy *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
35 struct pic32mx_devs_s {
40 { 0x78, "460F512L USB", 512 },
41 { 0x74, "460F256L USB", 256 },
42 { 0x6D, "440F128L USB", 128 },
43 { 0x56, "440F512H USB", 512 },
44 { 0x52, "440F256H USB", 256 },
45 { 0x4D, "440F128H USB", 128 },
46 { 0x42, "420F032H USB", 32 },
47 { 0x38, "360F512L", 512 },
48 { 0x34, "360F256L", 256 },
49 { 0x2D, "340F128L", 128 },
50 { 0x2A, "320F128L", 128 },
51 { 0x16, "340F512H", 512 },
52 { 0x12, "340F256H", 256 },
53 { 0x0D, "340F128H", 128 },
54 { 0x0A, "320F128H", 128 },
55 { 0x06, "320F064H", 64 },
56 { 0x02, "320F032H", 32 },
60 static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr);
61 static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word);
63 /* flash bank pic32mx <base> <size> 0 0 <target#>
65 FLASH_BANK_COMMAND_HANDLER(pic32mx_flash_bank_command)
67 struct pic32mx_flash_bank *pic32mx_info;
71 LOG_WARNING("incomplete flash_bank pic32mx configuration");
72 return ERROR_FLASH_BANK_INVALID;
75 pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
76 bank->driver_priv = pic32mx_info;
78 pic32mx_info->write_algorithm = NULL;
79 pic32mx_info->probed = 0;
84 static uint32_t pic32mx_get_flash_status(struct flash_bank *bank)
86 struct target *target = bank->target;
89 target_read_u32(target, PIC32MX_NVMCON, &status);
94 static uint32_t pic32mx_wait_status_busy(struct flash_bank *bank, int timeout)
98 /* wait for busy to clear */
99 while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))
101 LOG_DEBUG("status: 0x%" PRIx32, status);
105 LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
110 static int pic32mx_nvm_exec(struct flash_bank *bank, uint32_t op, uint32_t timeout)
112 struct target *target = bank->target;
115 target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN | op);
117 /* unlock flash registers */
118 target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);
119 target_write_u32(target, PIC32MX_NVMKEY, NVMKEY2);
121 /* start operation */
122 target_write_u32(target, PIC32MX_NVMCONSET, NVMCON_NVMWR);
124 status = pic32mx_wait_status_busy(bank, timeout);
126 /* lock flash registers */
127 target_write_u32(target, PIC32MX_NVMCONCLR, NVMCON_NVMWREN);
132 static int pic32mx_protect_check(struct flash_bank *bank)
134 struct target *target = bank->target;
140 if (target->state != TARGET_HALTED)
142 LOG_ERROR("Target not halted");
143 return ERROR_TARGET_NOT_HALTED;
146 target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
147 if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
148 num_pages = 0xffff; /* All pages protected */
149 else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
151 if (devcfg0 & (1 << 24))
152 num_pages = 0; /* All pages unprotected */
154 num_pages = 0xffff; /* All pages protected */
157 num_pages = (~devcfg0 >> 12) & 0xff;
158 for (s = 0; s < bank->num_sectors && s < num_pages; s++)
159 bank->sectors[s].is_protected = 1;
160 for (; s < bank->num_sectors; s++)
161 bank->sectors[s].is_protected = 0;
166 static int pic32mx_erase(struct flash_bank *bank, int first, int last)
168 struct target *target = bank->target;
172 if (bank->target->state != TARGET_HALTED)
174 LOG_ERROR("Target not halted");
175 return ERROR_TARGET_NOT_HALTED;
178 if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))
180 LOG_DEBUG("Erasing entire program flash");
181 status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
182 if (status & NVMCON_NVMERR)
183 return ERROR_FLASH_OPERATION_FAILED;
184 if (status & NVMCON_LVDERR)
185 return ERROR_FLASH_OPERATION_FAILED;
189 for (i = first; i <= last; i++)
191 if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
192 target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(bank->base + bank->sectors[i].offset));
194 target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(bank->base + bank->sectors[i].offset));
196 status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
198 if (status & NVMCON_NVMERR)
199 return ERROR_FLASH_OPERATION_FAILED;
200 if (status & NVMCON_LVDERR)
201 return ERROR_FLASH_OPERATION_FAILED;
202 bank->sectors[i].is_erased = 1;
208 static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
210 struct pic32mx_flash_bank *pic32mx_info = NULL;
211 struct target *target = bank->target;
213 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
219 pic32mx_info = bank->driver_priv;
221 if (target->state != TARGET_HALTED)
223 LOG_ERROR("Target not halted");
224 return ERROR_TARGET_NOT_HALTED;
228 if ((first && (first % pic32mx_info->ppage_size)) || ((last + 1) && (last + 1) % pic32mx_info->ppage_size))
230 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", pic32mx_info->ppage_size);
231 return ERROR_FLASH_SECTOR_INVALID;
234 /* medium density - each bit refers to a 4bank protection
235 * high density - each bit refers to a 2bank protection */
236 target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);
238 prot_reg[0] = (uint16_t)protection;
239 prot_reg[1] = (uint16_t)(protection >> 8);
240 prot_reg[2] = (uint16_t)(protection >> 16);
241 prot_reg[3] = (uint16_t)(protection >> 24);
243 if (pic32mx_info->ppage_size == 2)
245 /* high density flash */
247 /* bit 7 controls sector 62 - 255 protection */
251 prot_reg[3] &= ~(1 << 7);
253 prot_reg[3] |= (1 << 7);
261 for (i = first; i <= last; i++)
263 reg = (i / pic32mx_info->ppage_size) / 8;
264 bit = (i / pic32mx_info->ppage_size) - (reg * 8);
267 prot_reg[reg] &= ~(1 << bit);
269 prot_reg[reg] |= (1 << bit);
274 /* medium density flash */
275 for (i = first; i <= last; i++)
277 reg = (i / pic32mx_info->ppage_size) / 8;
278 bit = (i / pic32mx_info->ppage_size) - (reg * 8);
281 prot_reg[reg] &= ~(1 << bit);
283 prot_reg[reg] |= (1 << bit);
287 if ((status = pic32mx_erase_options(bank)) != ERROR_OK)
290 pic32mx_info->option_bytes.protection[0] = prot_reg[0];
291 pic32mx_info->option_bytes.protection[1] = prot_reg[1];
292 pic32mx_info->option_bytes.protection[2] = prot_reg[2];
293 pic32mx_info->option_bytes.protection[3] = prot_reg[3];
295 return pic32mx_write_options(bank);
301 static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
303 struct target *target = bank->target;
304 uint32_t buffer_size = 512;
305 struct working_area *source;
306 uint32_t address = bank->base + offset;
307 int retval = ERROR_OK;
309 struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
310 struct armv7m_algorithm armv7m_info;
312 uint8_t pic32mx_flash_write_code[] = {
314 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, PIC32MX_FLASH_CR */
315 0x09, 0x4D, /* ldr r5, PIC32MX_FLASH_SR */
316 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
317 0x23, 0x60, /* str r3, [r4, #0] */
318 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
319 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
321 0x2B, 0x68, /* ldr r3, [r5, #0] */
322 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
323 0xFB, 0xD0, /* beq busy */
324 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
325 0x01, 0xD1, /* bne exit */
326 0x01, 0x3A, /* subs r2, r2, #1 */
327 0xED, 0xD1, /* bne write */
329 0xFE, 0xE7, /* b exit */
330 0x10, 0x20, 0x02, 0x40, /* PIC32MX_FLASH_CR: .word 0x40022010 */
331 0x0C, 0x20, 0x02, 0x40 /* PIC32MX_FLASH_SR: .word 0x4002200C */
334 /* flash write code */
335 if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code), &pic32mx_info->write_algorithm) != ERROR_OK)
337 LOG_WARNING("no working area available, can't do block memory writes");
338 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
341 if ((retval = target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code)) != ERROR_OK)
346 if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
349 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
350 if (pic32mx_info->write_algorithm)
351 target_free_working_area(target, pic32mx_info->write_algorithm);
354 LOG_WARNING("no large enough working area available, can't do block memory writes");
355 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
358 while (count >= buffer_size/4)
362 if ((retval = target_write_buffer(target, source->address, buffer_size, buffer)) != ERROR_OK) {
363 LOG_ERROR("Failed to write row buffer (%d words) to RAM", (int)(buffer_size/4));
368 buf_set_u32(reg_params[0].value, 0, 32, source->address);
369 buf_set_u32(reg_params[1].value, 0, 32, address);
370 buf_set_u32(reg_params[2].value, 0, 32, buffer_size/4);
372 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \
373 pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
375 LOG_ERROR("error executing pic32mx flash write algorithm");
376 retval = ERROR_FLASH_OPERATION_FAILED;
380 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
382 retval = ERROR_FLASH_OPERATION_FAILED;
386 status = pic32mx_write_row(bank, address, source->address);
387 if (status & NVMCON_NVMERR) {
388 LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
389 retval = ERROR_FLASH_OPERATION_FAILED;
392 if (status & NVMCON_LVDERR) {
393 LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
394 retval = ERROR_FLASH_OPERATION_FAILED;
398 buffer += buffer_size;
399 address += buffer_size;
400 count -= buffer_size/4;
403 target_free_working_area(target, source);
408 memcpy(&value, buffer, sizeof(uint32_t));
410 uint32_t status = pic32mx_write_word(bank, address, value);
411 if (status & NVMCON_NVMERR) {
412 LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
413 retval = ERROR_FLASH_OPERATION_FAILED;
416 if (status & NVMCON_LVDERR) {
417 LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
418 retval = ERROR_FLASH_OPERATION_FAILED;
430 static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word)
432 struct target *target = bank->target;
434 if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
435 target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
437 target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
438 target_write_u32(target, PIC32MX_NVMDATA, word);
440 return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
444 * Write a 128 word (512 byte) row to flash address from RAM srcaddr.
446 static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr)
448 struct target *target = bank->target;
450 LOG_DEBUG("addr: 0x%08" PRIx32 " srcaddr: 0x%08" PRIx32 "", address, srcaddr);
452 if (address >= PIC32MX_KSEG1_PGM_FLASH)
453 target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
455 target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
456 if (srcaddr >= PIC32MX_KSEG1_RAM)
457 target_write_u32(target, PIC32MX_NVMSRCADDR, KS1Virt2Phys(srcaddr));
459 target_write_u32(target, PIC32MX_NVMSRCADDR, KS0Virt2Phys(srcaddr));
461 return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
464 static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
466 uint32_t words_remaining = (count / 4);
467 uint32_t bytes_remaining = (count & 0x00000003);
468 uint32_t address = bank->base + offset;
469 uint32_t bytes_written = 0;
473 if (bank->target->state != TARGET_HALTED)
475 LOG_ERROR("Target not halted");
476 return ERROR_TARGET_NOT_HALTED;
481 LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
482 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
485 /* multiple words (4-byte) to be programmed? */
486 if (words_remaining > 0)
488 /* try using a block write */
489 if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
491 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
493 /* if block write failed (no sufficient working area),
494 * we use normal (slow) single dword accesses */
495 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
497 else if (retval == ERROR_FLASH_OPERATION_FAILED)
499 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
500 return ERROR_FLASH_OPERATION_FAILED;
505 buffer += words_remaining * 4;
506 address += words_remaining * 4;
511 while (words_remaining > 0)
514 memcpy(&value, buffer + bytes_written, sizeof(uint32_t));
516 status = pic32mx_write_word(bank, address, value);
517 if (status & NVMCON_NVMERR)
518 return ERROR_FLASH_OPERATION_FAILED;
519 if (status & NVMCON_LVDERR)
520 return ERROR_FLASH_OPERATION_FAILED;
529 uint32_t value = 0xffffffff;
530 memcpy(&value, buffer + bytes_written, bytes_remaining);
532 status = pic32mx_write_word(bank, address, value);
533 if (status & NVMCON_NVMERR)
534 return ERROR_FLASH_OPERATION_FAILED;
535 if (status & NVMCON_LVDERR)
536 return ERROR_FLASH_OPERATION_FAILED;
542 static int pic32mx_probe(struct flash_bank *bank)
544 struct target *target = bank->target;
545 struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
546 struct mips32_common *mips32 = target->arch_info;
547 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
549 uint16_t num_pages = 0;
553 pic32mx_info->probed = 0;
555 device_id = ejtag_info->idcode;
556 LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%02x, ver 0x%03x)",
558 (unsigned)((device_id >> 1)&0x7ff),
559 (unsigned)((device_id >> 12)&0xff),
560 (unsigned)((device_id >> 20)&0xfff));
562 if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
563 LOG_WARNING("Cannot identify target as a PIC32MX family.");
564 return ERROR_FLASH_OPERATION_FAILED;
568 if (bank->base == PIC32MX_KSEG1_BOOT_FLASH || bank->base == 1) {
569 /* 0xBFC00000: Boot flash size fixed at 12k */
572 /* 0xBD000000: Program flash size varies with device */
573 for (i = 0; pic32mx_devs[i].name != NULL; i++)
574 if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
575 num_pages = pic32mx_devs[i].pfm_size;
578 if (pic32mx_devs[i].name == NULL) {
579 LOG_WARNING("Cannot identify target as a PIC32MX family.");
580 return ERROR_FLASH_OPERATION_FAILED;
585 if (bank->target->state != TARGET_HALTED)
587 LOG_ERROR("Target not halted");
588 return ERROR_TARGET_NOT_HALTED;
591 /* get flash size from target */
592 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
594 /* failed reading flash size, default to max target family */
599 LOG_INFO("flash size = %dkbytes", num_pages);
601 /* calculate numbers of pages */
602 num_pages /= (page_size / 1024);
604 if (bank->base == 0) bank->base = PIC32MX_KSEG1_PGM_FLASH;
605 if (bank->base == 1) bank->base = PIC32MX_KSEG1_BOOT_FLASH;
606 bank->size = (num_pages * page_size);
607 bank->num_sectors = num_pages;
608 bank->chip_width = 4;
610 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
612 for (i = 0; i < num_pages; i++)
614 bank->sectors[i].offset = i * page_size;
615 bank->sectors[i].size = page_size;
616 bank->sectors[i].is_erased = -1;
617 bank->sectors[i].is_protected = 1;
620 pic32mx_info->probed = 1;
625 static int pic32mx_auto_probe(struct flash_bank *bank)
627 struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
628 if (pic32mx_info->probed)
630 return pic32mx_probe(bank);
634 COMMAND_HANDLER(pic32mx_handle_part_id_command)
640 static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
642 struct target *target = bank->target;
643 struct mips32_common *mips32 = target->arch_info;
644 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
648 device_id = ejtag_info->idcode;
650 if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
651 snprintf(buf, buf_size,
652 "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
653 (unsigned)((device_id >> 1)&0x7ff),
655 return ERROR_FLASH_OPERATION_FAILED;
657 for (i = 0; pic32mx_devs[i].name != NULL; i++)
658 if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
659 printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
662 if (pic32mx_devs[i].name == NULL) {
663 snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family\n");
664 return ERROR_FLASH_OPERATION_FAILED;
668 printed = snprintf(buf, buf_size, " Ver: 0x%03x",
669 (unsigned)((device_id >> 20)&0xfff));
675 COMMAND_HANDLER(pic32mx_handle_lock_command)
677 struct target *target = NULL;
678 struct pic32mx_flash_bank *pic32mx_info = NULL;
682 command_print(cmd_ctx, "pic32mx lock <bank>");
686 struct flash_bank *bank;
687 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
688 if (ERROR_OK != retval)
691 pic32mx_info = bank->driver_priv;
693 target = bank->target;
695 if (target->state != TARGET_HALTED)
697 LOG_ERROR("Target not halted");
698 return ERROR_TARGET_NOT_HALTED;
701 if (pic32mx_erase_options(bank) != ERROR_OK)
703 command_print(cmd_ctx, "pic32mx failed to erase options");
707 /* set readout protection */
708 pic32mx_info->option_bytes.RDP = 0;
710 if (pic32mx_write_options(bank) != ERROR_OK)
712 command_print(cmd_ctx, "pic32mx failed to lock device");
716 command_print(cmd_ctx, "pic32mx locked");
721 COMMAND_HANDLER(pic32mx_handle_unlock_command)
723 struct target *target = NULL;
724 struct pic32mx_flash_bank *pic32mx_info = NULL;
728 command_print(cmd_ctx, "pic32mx unlock <bank>");
732 struct flash_bank *bank;
733 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
734 if (ERROR_OK != retval)
737 pic32mx_info = bank->driver_priv;
739 target = bank->target;
741 if (target->state != TARGET_HALTED)
743 LOG_ERROR("Target not halted");
744 return ERROR_TARGET_NOT_HALTED;
747 if (pic32mx_erase_options(bank) != ERROR_OK)
749 command_print(cmd_ctx, "pic32mx failed to unlock device");
753 if (pic32mx_write_options(bank) != ERROR_OK)
755 command_print(cmd_ctx, "pic32mx failed to lock device");
759 command_print(cmd_ctx, "pic32mx unlocked");
766 static int pic32mx_chip_erase(struct flash_bank *bank)
768 struct target *target = bank->target;
773 if (target->state != TARGET_HALTED)
775 LOG_ERROR("Target not halted");
776 return ERROR_TARGET_NOT_HALTED;
779 LOG_INFO("PIC32MX chip erase called");
782 /* unlock option flash registers */
783 target_write_u32(target, PIC32MX_FLASH_KEYR, KEY1);
784 target_write_u32(target, PIC32MX_FLASH_KEYR, KEY2);
786 /* chip erase flash memory */
787 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);
788 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER | FLASH_STRT);
790 status = pic32mx_wait_status_busy(bank, 10);
792 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_LOCK);
794 if (status & FLASH_WRPRTERR)
796 LOG_ERROR("pic32mx device protected");
800 if (status & FLASH_PGERR)
802 LOG_ERROR("pic32mx device programming failed");
811 COMMAND_HANDLER(pic32mx_handle_chip_erase_command)
818 command_print(cmd_ctx, "pic32mx chip_erase");
822 struct flash_bank *bank;
823 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
824 if (ERROR_OK != retval)
827 if (pic32mx_chip_erase(bank) == ERROR_OK)
829 /* set all sectors as erased */
830 for (i = 0; i < bank->num_sectors; i++)
832 bank->sectors[i].is_erased = 1;
835 command_print(cmd_ctx, "pic32mx chip erase complete");
839 command_print(cmd_ctx, "pic32mx chip erase failed");
846 COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
848 uint32_t address, value;
853 command_print(cmd_ctx, "pic32mx pgm_word <addr> <value> <bank>");
857 COMMAND_PARSE_NUMBER(u32, args[0], address);
858 COMMAND_PARSE_NUMBER(u32, args[1], value);
860 struct flash_bank *bank;
861 int retval = flash_command_get_bank_by_num(cmd_ctx, args[2], &bank);
862 if (ERROR_OK != retval)
865 if (address < bank->base || address >= (bank->base + bank->size))
867 command_print(cmd_ctx, "flash address '%s' is out of bounds", args[0]);
872 status = pic32mx_write_word(bank, address, value);
873 if (status & NVMCON_NVMERR)
874 res = ERROR_FLASH_OPERATION_FAILED;
875 if (status & NVMCON_LVDERR)
876 res = ERROR_FLASH_OPERATION_FAILED;
879 command_print(cmd_ctx, "pic32mx pgm word complete");
881 command_print(cmd_ctx, "pic32mx pgm word failed (status = 0x%x)", status);
886 static int pic32mx_register_commands(struct command_context *cmd_ctx)
888 struct command *pic32mx_cmd = register_command(cmd_ctx, NULL, "pic32mx",
889 NULL, COMMAND_ANY, "pic32mx flash specific commands");
891 register_command(cmd_ctx, pic32mx_cmd, "lock",
892 pic32mx_handle_lock_command, COMMAND_EXEC,
894 register_command(cmd_ctx, pic32mx_cmd, "unlock",
895 pic32mx_handle_unlock_command, COMMAND_EXEC,
896 "unlock protected device");
898 register_command(cmd_ctx, pic32mx_cmd, "chip_erase",
899 pic32mx_handle_chip_erase_command, COMMAND_EXEC,
901 register_command(cmd_ctx, pic32mx_cmd, "pgm_word",
902 pic32mx_handle_pgm_word_command, COMMAND_EXEC,
907 struct flash_driver pic32mx_flash = {
909 .register_commands = &pic32mx_register_commands,
910 .flash_bank_command = &pic32mx_flash_bank_command,
911 .erase = &pic32mx_erase,
912 .protect = &pic32mx_protect,
913 .write = &pic32mx_write,
914 .probe = &pic32mx_probe,
915 .auto_probe = &pic32mx_auto_probe,
916 .erase_check = &default_flash_mem_blank_check,
917 .protect_check = &pic32mx_protect_check,
918 .info = &pic32mx_info,