1 /* src/flash/s3c2412_nand.c
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3 * S3C2412 OpenOCD NAND Flash controller support.
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5 * Copyright 2007,2008 Ben Dooks <ben@fluff.org>
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7 * This program is free software; you can redistribute it and/or modify
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8 * it under the terms of the GNU General Public License as published by
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9 * the Free Software Foundation; either version 2 of the License, or
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10 * (at your option) any later version.
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12 * Many thanks to Simtec Electronics for sponsoring this work.
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15 #ifdef HAVE_CONFIG_H
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19 #include "replacements.h"
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26 #include "s3c24xx_nand.h"
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29 int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
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30 int s3c2412_init(struct nand_device_s *device);
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32 nand_flash_controller_t s3c2412_nand_controller =
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35 .nand_device_command = s3c2412_nand_device_command,
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36 .register_commands = s3c24xx_register_commands,
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37 .init = s3c2412_init,
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38 .reset = s3c24xx_reset,
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39 .command = s3c24xx_command,
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40 .address = s3c24xx_address,
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41 .write_data = s3c24xx_write_data,
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42 .read_data = s3c24xx_read_data,
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43 .write_page = s3c24xx_write_page,
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44 .read_page = s3c24xx_read_page,
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45 .write_block_data = s3c2440_write_block_data,
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46 .read_block_data = s3c2440_read_block_data,
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47 .controller_ready = s3c24xx_controller_ready,
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48 .nand_ready = s3c2440_nand_ready,
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51 int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
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52 char **args, int argc,
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53 struct nand_device_s *device)
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55 s3c24xx_nand_controller_t *info;
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57 info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
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59 return ERROR_NAND_DEVICE_INVALID;
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62 /* fill in the address fields for the core device */
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63 info->cmd = S3C2440_NFCMD;
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64 info->addr = S3C2440_NFADDR;
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65 info->data = S3C2440_NFDATA;
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66 info->nfstat = S3C2412_NFSTAT;
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71 int s3c2412_init(struct nand_device_s *device)
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73 s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
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74 target_t *target = s3c24xx_info->target;
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76 target_write_u32(target, S3C2410_NFCONF,
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77 S3C2440_NFCONF_TACLS(3) |
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78 S3C2440_NFCONF_TWRPH0(7) |
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79 S3C2440_NFCONF_TWRPH1(7));
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81 target_write_u32(target, S3C2440_NFCONT,
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82 S3C2412_NFCONT_INIT_MAIN_ECC |
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83 S3C2440_NFCONT_ENABLE);
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