1 /* src/flash/s3c2440_nand.c
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3 * S3C2440 OpenOCD NAND Flash controller support.
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5 * Copyright 2007,2008 Ben Dooks <ben@fluff.org>
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7 * This program is free software; you can redistribute it and/or modify
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8 * it under the terms of the GNU General Public License as published by
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9 * the Free Software Foundation; either version 2 of the License, or
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10 * (at your option) any later version.
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12 * Many thanks to Simtec Electronics for sponsoring this work.
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15 #ifdef HAVE_CONFIG_H
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19 #include "replacements.h"
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26 #include "s3c24xx_nand.h"
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29 int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
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30 int s3c2440_init(struct nand_device_s *device);
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31 int s3c2440_nand_ready(struct nand_device_s *device, int timeout);
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33 nand_flash_controller_t s3c2440_nand_controller =
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36 .nand_device_command = s3c2440_nand_device_command,
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37 .register_commands = s3c24xx_register_commands,
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38 .init = s3c2440_init,
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39 .reset = s3c24xx_reset,
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40 .command = s3c24xx_command,
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41 .address = s3c24xx_address,
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42 .write_data = s3c24xx_write_data,
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43 .read_data = s3c24xx_read_data,
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44 .write_page = s3c24xx_write_page,
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45 .read_page = s3c24xx_read_page,
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46 .write_block_data = s3c2440_write_block_data,
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47 .read_block_data = s3c2440_read_block_data,
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48 .controller_ready = s3c24xx_controller_ready,
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49 .nand_ready = s3c2440_nand_ready,
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52 int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
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53 char **args, int argc,
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54 struct nand_device_s *device)
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56 s3c24xx_nand_controller_t *info;
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58 info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
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60 return ERROR_NAND_DEVICE_INVALID;
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63 /* fill in the address fields for the core device */
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64 info->cmd = S3C2440_NFCMD;
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65 info->addr = S3C2440_NFADDR;
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66 info->data = S3C2440_NFDATA;
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67 info->nfstat = S3C2440_NFSTAT;
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72 int s3c2440_init(struct nand_device_s *device)
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74 s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
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75 target_t *target = s3c24xx_info->target;
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78 target_write_u32(target, S3C2410_NFCONF,
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79 S3C2440_NFCONF_TACLS(3) |
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80 S3C2440_NFCONF_TWRPH0(7) |
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81 S3C2440_NFCONF_TWRPH1(7));
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83 target_write_u32(target, S3C2440_NFCONT,
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84 S3C2440_NFCONT_INITECC | S3C2440_NFCONT_ENABLE);
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89 int s3c2440_nand_ready(struct nand_device_s *device, int timeout)
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91 s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
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92 target_t *target = s3c24xx_info->target;
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95 if (target->state != TARGET_HALTED) {
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96 ERROR("target must be halted to use S3C24XX NAND flash controller");
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97 return ERROR_NAND_OPERATION_FAILED;
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101 target_read_u8(target, s3c24xx_info->nfstat, &status);
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103 if (status & S3C2440_NFSTAT_READY)
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107 } while (timeout-- > 0);
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113 /* use the fact we can read/write 4 bytes in one go via a single 32bit op */
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115 int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_size)
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117 s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
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118 target_t *target = s3c24xx_info->target;
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119 u32 nfdata = s3c24xx_info->data;
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122 INFO("%s: reading data: %p, %p, %d\n", __func__, device, data, data_size);
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124 if (target->state != TARGET_HALTED) {
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125 ERROR("target must be halted to use S3C24XX NAND flash controller");
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126 return ERROR_NAND_OPERATION_FAILED;
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129 while (data_size >= 4) {
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130 target_read_u32(target, nfdata, &tmp);
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133 data[1] = tmp >> 8;
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134 data[2] = tmp >> 16;
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135 data[3] = tmp >> 24;
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141 while (data_size > 0) {
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142 target_read_u8(target, nfdata, data);
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151 int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_size)
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153 s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
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154 target_t *target = s3c24xx_info->target;
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155 u32 nfdata = s3c24xx_info->data;
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158 if (target->state != TARGET_HALTED) {
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159 ERROR("target must be halted to use S3C24XX NAND flash controller");
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160 return ERROR_NAND_OPERATION_FAILED;
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163 while (data_size >= 4) {
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164 tmp = le_to_h_u32(data);
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165 target_write_u32(target, nfdata, tmp);
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171 while (data_size > 0) {
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172 target_write_u8(target, nfdata, *data);
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