git.sur5r.net Git - openocd/blob - src/flash/s3c2443_nand.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007, 2008 by Ben Dooks                                 *
   3  *   ben@fluff.org                                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 /*
  22  * S3C2443 OpenOCD NAND Flash controller support.
  23  *
  24  * Many thanks to Simtec Electronics for sponsoring this work.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "replacements.h"
  32 #include "log.h"
  33
  34 #include <stdlib.h>
  35 #include <string.h>
  36
  37 #include "nand.h"
  38 #include "s3c24xx_nand.h"
  39 #include "target.h"
  40
  41 int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
  42 int s3c2443_init(struct nand_device_s *device);
  43 int s3c2443_nand_ready(struct nand_device_s *device, int timeout);
  44
  45 nand_flash_controller_t s3c2443_nand_controller =
  46 {
  47         .name                   = "s3c2443",
  48         .nand_device_command    = s3c2443_nand_device_command,
  49         .register_commands      = s3c24xx_register_commands,
  50         .init                   = s3c2443_init,
  51         .reset                  = s3c24xx_reset,
  52         .command                = s3c24xx_command,
  53         .address                = s3c24xx_address,
  54         .write_data             = s3c24xx_write_data,
  55         .read_data              = s3c24xx_read_data,
  56         .write_page             = s3c24xx_write_page,
  57         .read_page              = s3c24xx_read_page,
  58         .write_block_data       = s3c2440_write_block_data,
  59         .read_block_data        = s3c2440_read_block_data,
  60         .controller_ready       = s3c24xx_controller_ready,
  61         .nand_ready             = s3c2440_nand_ready,
  62 };
  63
  64 int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
  65                                 char **args, int argc,
  66                                 struct nand_device_s *device)
  67 {
  68         s3c24xx_nand_controller_t *info;
  69
  70         info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
  71         if (info == NULL) {
  72                 return ERROR_NAND_DEVICE_INVALID;
  73         }
  74
  75         /* fill in the address fields for the core device */
  76         info->cmd = S3C2440_NFCMD;
  77         info->addr = S3C2440_NFADDR;
  78         info->data = S3C2440_NFDATA;
  79         info->nfstat = S3C2412_NFSTAT;
  80
  81         return ERROR_OK;
  82 }
  83
  84 int s3c2443_init(struct nand_device_s *device)
  85 {
  86         s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
  87         target_t *target = s3c24xx_info->target;
  88
  89         target_write_u32(target, S3C2410_NFCONF,
  90                          S3C2440_NFCONF_TACLS(3) |
  91                          S3C2440_NFCONF_TWRPH0(7) |
  92                          S3C2440_NFCONF_TWRPH1(7));
  93
  94         target_write_u32(target, S3C2440_NFCONT,
  95                          S3C2412_NFCONT_INIT_MAIN_ECC |
  96                          S3C2440_NFCONT_ENABLE);
  97
  98         return ERROR_OK;
  99 }