]> git.sur5r.net Git - openocd/blob - src/flash/s3c2443_nand.c
David Brownell <david-b@pacbell.net>:
[openocd] / src / flash / s3c2443_nand.c
1 /***************************************************************************
2  *   Copyright (C) 2007, 2008 by Ben Dooks                                 *
3  *   ben@fluff.org                                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20
21 /*
22  * S3C2443 OpenOCD NAND Flash controller support.
23  *
24  * Many thanks to Simtec Electronics for sponsoring this work.
25  */
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "s3c24xx_nand.h"
32
33
34 static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
35 static int s3c2443_init(struct nand_device_s *device);
36
37 nand_flash_controller_t s3c2443_nand_controller =
38 {
39         .name                   = "s3c2443",
40         .nand_device_command    = s3c2443_nand_device_command,
41         .register_commands      = s3c24xx_register_commands,
42         .init                   = s3c2443_init,
43         .reset                  = s3c24xx_reset,
44         .command                = s3c24xx_command,
45         .address                = s3c24xx_address,
46         .write_data             = s3c24xx_write_data,
47         .read_data              = s3c24xx_read_data,
48         .write_page             = s3c24xx_write_page,
49         .read_page              = s3c24xx_read_page,
50         .write_block_data       = s3c2440_write_block_data,
51         .read_block_data        = s3c2440_read_block_data,
52         .controller_ready       = s3c24xx_controller_ready,
53         .nand_ready             = s3c2440_nand_ready,
54 };
55
56 static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
57                                 char **args, int argc,
58                                 struct nand_device_s *device)
59 {
60         s3c24xx_nand_controller_t *info;
61
62         info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
63         if (info == NULL) {
64                 return ERROR_NAND_DEVICE_INVALID;
65         }
66
67         /* fill in the address fields for the core device */
68         info->cmd = S3C2440_NFCMD;
69         info->addr = S3C2440_NFADDR;
70         info->data = S3C2440_NFDATA;
71         info->nfstat = S3C2412_NFSTAT;
72
73         return ERROR_OK;
74 }
75
76 static int s3c2443_init(struct nand_device_s *device)
77 {
78         s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
79         target_t *target = s3c24xx_info->target;
80
81         target_write_u32(target, S3C2410_NFCONF,
82                          S3C2440_NFCONF_TACLS(3) |
83                          S3C2440_NFCONF_TWRPH0(7) |
84                          S3C2440_NFCONF_TWRPH1(7));
85
86         target_write_u32(target, S3C2440_NFCONT,
87                          S3C2412_NFCONT_INIT_MAIN_ECC |
88                          S3C2440_NFCONT_ENABLE);
89
90         return ERROR_OK;
91 }