git.sur5r.net Git - openocd/blob - src/flash/s3c2443_nand.c

   1 /* src/flash/s3c2443_nand.c\r
   2  *\r
   3  * S3C2443 OpenOCD NAND Flash controller support.\r
   4  *\r
   5  * Copyright 2007,2008 Ben Dooks <ben@fluff.org>\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10  * (at your option) any later version.\r
  11  *\r
  12  * Many thanks to Simtec Electronics for sponsoring this work.\r
  13  */\r
  14 \r
  15 \r
  16 #ifdef HAVE_CONFIG_H\r
  17 #include "config.h"\r
  18 #endif\r
  19 \r
  20 #include "replacements.h"\r
  21 #include "log.h"\r
  22 \r
  23 #include <stdlib.h>\r
  24 #include <string.h>\r
  25 \r
  26 #include "nand.h"\r
  27 #include "s3c24xx_nand.h"\r
  28 #include "target.h"\r
  29 \r
  30 int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);\r
  31 int s3c2443_init(struct nand_device_s *device);\r
  32 int s3c2443_nand_ready(struct nand_device_s *device, int timeout);\r
  33 \r
  34 nand_flash_controller_t s3c2443_nand_controller =\r
  35 {\r
  36         .name                   = "s3c2443",\r
  37         .nand_device_command    = s3c2443_nand_device_command,\r
  38         .register_commands      = s3c24xx_register_commands,\r
  39         .init                   = s3c2443_init,\r
  40         .reset                  = s3c24xx_reset,\r
  41         .command                = s3c24xx_command,\r
  42         .address                = s3c24xx_address,\r
  43         .write_data             = s3c24xx_write_data,\r
  44         .read_data              = s3c24xx_read_data,\r
  45         .write_page             = s3c24xx_write_page,\r
  46         .read_page              = s3c24xx_read_page,\r
  47         .write_block_data       = s3c2440_write_block_data,\r
  48         .read_block_data        = s3c2440_read_block_data,\r
  49         .controller_ready       = s3c24xx_controller_ready,\r
  50         .nand_ready             = s3c2440_nand_ready,\r
  51 };\r
  52 \r
  53 int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,\r
  54                                 char **args, int argc,\r
  55                                 struct nand_device_s *device)\r
  56 {\r
  57         s3c24xx_nand_controller_t *info;\r
  58         \r
  59         info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);\r
  60         if (info == NULL) {\r
  61                 return ERROR_NAND_DEVICE_INVALID;\r
  62         }\r
  63 \r
  64         /* fill in the address fields for the core device */\r
  65         info->cmd = S3C2440_NFCMD;\r
  66         info->addr = S3C2440_NFADDR;\r
  67         info->data = S3C2440_NFDATA;\r
  68         info->nfstat = S3C2412_NFSTAT;\r
  69         \r
  70         return ERROR_OK;\r
  71 }\r
  72 \r
  73 int s3c2443_init(struct nand_device_s *device)\r
  74 {\r
  75         s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;\r
  76         target_t *target = s3c24xx_info->target;\r
  77 \r
  78         target_write_u32(target, S3C2410_NFCONF,\r
  79                          S3C2440_NFCONF_TACLS(3) |\r
  80                          S3C2440_NFCONF_TWRPH0(7) |\r
  81                          S3C2440_NFCONF_TWRPH1(7));\r
  82 \r
  83         target_write_u32(target, S3C2440_NFCONT,\r
  84                          S3C2412_NFCONT_INIT_MAIN_ECC |\r
  85                          S3C2440_NFCONT_ENABLE);\r
  86 \r
  87         return ERROR_OK;\r
  88 }\r