1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 /***************************************************************************
22 * STELLARIS is tested on LM3S811
23 ***************************************************************************/
28 #include "replacements.h"
30 #include "stellaris.h"
31 #include "cortex_m3.h"
36 #include "binarybuffer.h"
43 #define DID0_VER(did0) ((did0>>28)&0x07)
44 int stellaris_register_commands(struct command_context_s *cmd_ctx);
45 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
46 int stellaris_erase(struct flash_bank_s *bank, int first, int last);
47 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
48 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
49 int stellaris_auto_probe(struct flash_bank_s *bank);
50 int stellaris_probe(struct flash_bank_s *bank);
51 int stellaris_erase_check(struct flash_bank_s *bank);
52 int stellaris_protect_check(struct flash_bank_s *bank);
53 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
55 int stellaris_read_part_info(struct flash_bank_s *bank);
56 u32 stellaris_get_flash_status(flash_bank_t *bank);
57 void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
58 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
60 int stellaris_read_part_info(struct flash_bank_s *bank);
62 flash_driver_t stellaris_flash =
65 .register_commands = stellaris_register_commands,
66 .flash_bank_command = stellaris_flash_bank_command,
67 .erase = stellaris_erase,
68 .protect = stellaris_protect,
69 .write = stellaris_write,
70 .probe = stellaris_probe,
71 .auto_probe = stellaris_auto_probe,
72 .erase_check = stellaris_erase_check,
73 .protect_check = stellaris_protect_check,
74 .info = stellaris_info
204 char * StellarisClassname[2] =
210 /***************************************************************************
211 * openocd command interface *
212 ***************************************************************************/
214 /* flash_bank stellaris <base> <size> 0 0 <target#>
216 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
218 stellaris_flash_bank_t *stellaris_info;
222 WARNING("incomplete flash_bank stellaris configuration");
223 return ERROR_FLASH_BANK_INVALID;
226 stellaris_info = calloc(sizeof(stellaris_flash_bank_t),1);
228 bank->driver_priv = stellaris_info;
230 stellaris_info->target_name = "Unknown target";
232 /* part wasn't probed for info yet */
233 stellaris_info->did1 = 0;
235 /* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
239 int stellaris_register_commands(struct command_context_s *cmd_ctx)
242 command_t *stellaris_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, NULL);
243 register_command(cmd_ctx, stellaris_cmd, "gpnvm", stellaris_handle_gpnvm_command, COMMAND_EXEC,
244 "stellaris gpnvm <num> <bit> set|clear, set or clear stellaris gpnvm bit");
249 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
251 int printed, device_class;
252 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
254 stellaris_read_part_info(bank);
256 if (stellaris_info->did1 == 0)
258 printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");
261 return ERROR_FLASH_OPERATION_FAILED;
264 if (DID0_VER(stellaris_info->did0)>0)
266 device_class = (stellaris_info->did0>>16)&0xFF;
272 printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
273 device_class, StellarisClassname[device_class], stellaris_info->target_name,
274 'A' + ((stellaris_info->did0>>8)&0xFF), (stellaris_info->did0)&0xFF);
278 printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik, flashsize: %ik\n",
279 stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+((stellaris_info->dc0>>16)&0xFFFF))/4, (1+(stellaris_info->dc0&0xFFFF))*2);
283 printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz, rcc is 0x%x \n", stellaris_info->mck_freq / 1000, stellaris_info->rcc);
287 if (stellaris_info->num_lockbits>0) {
288 printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", stellaris_info->pagesize, stellaris_info->num_lockbits, stellaris_info->lockbits,stellaris_info->num_pages/stellaris_info->num_lockbits);
295 /***************************************************************************
296 * chip identification and status *
297 ***************************************************************************/
299 u32 stellaris_get_flash_status(flash_bank_t *bank)
301 target_t *target = bank->target;
304 target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc);
309 /** Read clock configuration and set stellaris_info->usec_clocks*/
311 void stellaris_read_clock_info(flash_bank_t *bank)
313 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
314 target_t *target = bank->target;
315 u32 rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
316 unsigned long mainfreq;
318 target_read_u32(target, SCB_BASE|RCC, &rcc);
319 DEBUG("Stellaris RCC %x",rcc);
320 target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
321 DEBUG("Stellaris PLLCFG %x",pllcfg);
322 stellaris_info->rcc = rcc;
324 sysdiv = (rcc>>23)&0xF;
325 usesysdiv = (rcc>>22)&0x1;
326 bypass = (rcc>>11)&0x1;
327 oscsrc = (rcc>>4)&0x3;
328 /* xtal = (rcc>>6)&0xF; */
332 mainfreq = 6000000; /* Default xtal */
335 mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
338 mainfreq = 5625000; /* Internal osc. / 4 */
341 WARNING("Invalid oscsrc (3) in rcc register");
345 default: /* NOTREACHED */
351 mainfreq = 200000000; /* PLL out frec */
354 stellaris_info->mck_freq = mainfreq/(1+sysdiv);
356 stellaris_info->mck_freq = mainfreq;
358 /* Forget old flash timing */
359 stellaris_set_flash_mode(bank,0);
362 /* Setup the timimg registers */
363 void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
365 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
366 target_t *target = bank->target;
368 u32 usecrl = (stellaris_info->mck_freq/1000000ul-1);
369 DEBUG("usecrl = %i",usecrl);
370 target_write_u32(target, SCB_BASE|USECRL , usecrl);
374 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
378 /* Stellaris waits for cmdbit to clear */
379 while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
381 DEBUG("status: 0x%x", status);
385 /* Flash errors are reflected in the FLASH_CRIS register */
391 /* Send one command to the flash controller */
392 int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
395 target_t *target = bank->target;
397 fmc = FMC_WRKEY | cmd;
398 target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
399 DEBUG("Flash command: 0x%x", fmc);
401 if (stellaris_wait_status_busy(bank, cmd, 100))
403 return ERROR_FLASH_OPERATION_FAILED;
409 /* Read device id register, main clock frequency register and fill in driver info structure */
410 int stellaris_read_part_info(struct flash_bank_s *bank)
412 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
413 target_t *target = bank->target;
414 u32 did0,did1, ver, fam, status;
417 /* Read and parse chip identification register */
418 target_read_u32(target, SCB_BASE|DID0, &did0);
419 target_read_u32(target, SCB_BASE|DID1, &did1);
420 target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0);
421 target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1);
422 DEBUG("did0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%x",did0, did1, stellaris_info->dc0,stellaris_info->dc1);
425 if((ver != 0) && (ver != 1))
427 WARNING("Unknown did0 version, cannot identify target");
428 return ERROR_FLASH_OPERATION_FAILED;
433 WARNING("Cannot identify target as a Stellaris");
434 return ERROR_FLASH_OPERATION_FAILED;
438 fam = (did1 >> 24) & 0xF;
439 if(((ver != 0) && (ver != 1)) || (fam != 0))
441 WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
444 for (i=0;StellarisParts[i].partno;i++)
446 if (StellarisParts[i].partno==((did1>>16)&0xFF))
450 stellaris_info->target_name = StellarisParts[i].partname;
452 stellaris_info->did0 = did0;
453 stellaris_info->did1 = did1;
455 stellaris_info->num_lockbits = 1+(stellaris_info->dc0&0xFFFF);
456 stellaris_info->num_pages = 2*(1+(stellaris_info->dc0&0xFFFF));
457 stellaris_info->pagesize = 1024;
458 bank->size = 1024*stellaris_info->num_pages;
459 stellaris_info->pages_in_lockregion = 2;
460 target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
462 /* Read main and master clock freqency register */
463 stellaris_read_clock_info(bank);
465 status = stellaris_get_flash_status(bank);
470 /***************************************************************************
472 ***************************************************************************/
474 int stellaris_erase_check(struct flash_bank_s *bank)
478 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
479 target_t *target = bank->target;
487 int stellaris_protect_check(struct flash_bank_s *bank)
491 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
493 if (bank->target->state != TARGET_HALTED)
495 return ERROR_TARGET_NOT_HALTED;
498 if (stellaris_info->did1 == 0)
500 stellaris_read_part_info(bank);
503 if (stellaris_info->did1 == 0)
505 WARNING("Cannot identify target as an AT91SAM");
506 return ERROR_FLASH_OPERATION_FAILED;
509 status = stellaris_get_flash_status(bank);
510 stellaris_info->lockbits = status >> 16;
515 int stellaris_erase(struct flash_bank_s *bank, int first, int last)
518 u32 flash_fmc, flash_cris;
519 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
520 target_t *target = bank->target;
522 if (bank->target->state != TARGET_HALTED)
524 return ERROR_TARGET_NOT_HALTED;
527 if (stellaris_info->did1 == 0)
529 stellaris_read_part_info(bank);
532 if (stellaris_info->did1 == 0)
534 WARNING("Cannot identify target as Stellaris");
535 return ERROR_FLASH_OPERATION_FAILED;
538 if ((first < 0) || (last < first) || (last >= stellaris_info->num_pages))
540 return ERROR_FLASH_SECTOR_INVALID;
543 /* Configure the flash controller timing */
544 stellaris_read_clock_info(bank);
545 stellaris_set_flash_mode(bank,0);
547 /* Clear and disable flash programming interrupts */
548 target_write_u32(target, FLASH_CIM, 0);
549 target_write_u32(target, FLASH_MISC, PMISC|AMISC);
551 if ((first == 0) && (last == (stellaris_info->num_pages-1)))
553 target_write_u32(target, FLASH_FMA, 0);
554 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
555 /* Wait until erase complete */
558 target_read_u32(target, FLASH_FMC, &flash_fmc);
560 while(flash_fmc & FMC_MERASE);
562 /* if device has > 128k, then second erase cycle is needed */
563 if(stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
565 target_write_u32(target, FLASH_FMA, 0x20000);
566 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
567 /* Wait until erase complete */
570 target_read_u32(target, FLASH_FMC, &flash_fmc);
572 while(flash_fmc & FMC_MERASE);
578 for (banknr=first;banknr<=last;banknr++)
580 /* Address is first word in page */
581 target_write_u32(target, FLASH_FMA, banknr*stellaris_info->pagesize);
582 /* Write erase command */
583 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
584 /* Wait until erase complete */
587 target_read_u32(target, FLASH_FMC, &flash_fmc);
589 while(flash_fmc & FMC_ERASE);
591 /* Check acess violations */
592 target_read_u32(target, FLASH_CRIS, &flash_cris);
593 if(flash_cris & (AMASK))
595 WARNING("Error erasing flash page %i, flash_cris 0x%x", banknr, flash_cris);
596 target_write_u32(target, FLASH_CRIS, 0);
597 return ERROR_FLASH_OPERATION_FAILED;
604 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
606 u32 fmppe, flash_fmc, flash_cris;
609 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
610 target_t *target = bank->target;
612 if (bank->target->state != TARGET_HALTED)
614 return ERROR_TARGET_NOT_HALTED;
617 if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
619 return ERROR_FLASH_SECTOR_INVALID;
622 if (stellaris_info->did1 == 0)
624 stellaris_read_part_info(bank);
627 if (stellaris_info->did1 == 0)
629 WARNING("Cannot identify target as an Stellaris MCU");
630 return ERROR_FLASH_OPERATION_FAILED;
633 /* Configure the flash controller timing */
634 stellaris_read_clock_info(bank);
635 stellaris_set_flash_mode(bank,0);
637 fmppe = stellaris_info->lockbits;
638 for (lockregion=first;lockregion<=last;lockregion++)
641 fmppe &= ~(1<<lockregion);
643 fmppe |= (1<<lockregion);
646 /* Clear and disable flash programming interrupts */
647 target_write_u32(target, FLASH_CIM, 0);
648 target_write_u32(target, FLASH_MISC, PMISC|AMISC);
650 DEBUG("fmppe 0x%x",fmppe);
651 target_write_u32(target, SCB_BASE|FMPPE, fmppe);
653 target_write_u32(target, FLASH_FMA, 1);
654 /* Write commit command */
655 /* TODO safety check, sice this cannot be undone */
656 WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
657 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
658 /* Wait until erase complete */
661 target_read_u32(target, FLASH_FMC, &flash_fmc);
663 while(flash_fmc & FMC_COMT);
665 /* Check acess violations */
666 target_read_u32(target, FLASH_CRIS, &flash_cris);
667 if(flash_cris & (AMASK))
669 WARNING("Error setting flash page protection, flash_cris 0x%x", flash_cris);
670 target_write_u32(target, FLASH_CRIS, 0);
671 return ERROR_FLASH_OPERATION_FAILED;
674 target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
679 u8 stellaris_write_code[] =
684 r1 = destination address
685 r2 = bytecount (in) - endaddr (work)
688 r3 = pFLASH_CTRL_BASE
694 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
695 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
696 0x01,0x25, /* movs r5, 1 */
697 0x00,0x26, /* movs r6, #0 */
699 0x19,0x60, /* str r1, [r3, #0] */
700 0x87,0x59, /* ldr r7, [r0, r6] */
701 0x5F,0x60, /* str r7, [r3, #4] */
702 0x9C,0x60, /* str r4, [r3, #8] */
704 0x9F,0x68, /* ldr r7, [r3, #8] */
705 0x2F,0x42, /* tst r7, r5 */
706 0xFC,0xD1, /* bne waitloop */
707 0x04,0x31, /* adds r1, r1, #4 */
708 0x04,0x36, /* adds r6, r6, #4 */
709 0x96,0x42, /* cmp r6, r2 */
710 0xF4,0xD1, /* bne mainloop */
711 0x00,0xBE, /* bkpt #0 */
712 /* pFLASH_CTRL_BASE: */
713 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
715 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
718 int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
720 target_t *target = bank->target;
721 u32 buffer_size = 8192;
722 working_area_t *source;
723 working_area_t *write_algorithm;
724 u32 address = bank->base + offset;
725 reg_param_t reg_params[8];
726 armv7m_algorithm_t armv7m_info;
729 DEBUG("(bank=%p buffer=%p offset=%08X wcount=%08X)",
730 bank, buffer, offset, wcount);
732 /* flash write code */
733 if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
735 WARNING("no working area available, can't do block memory writes");
736 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
739 target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code);
742 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
744 DEBUG("called target_alloc_working_area(target=%p buffer_size=%08X source=%p)",
745 target, buffer_size, source);
747 if (buffer_size <= 256)
749 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
751 target_free_working_area(target, write_algorithm);
753 WARNING("no large enough working area available, can't do block memory writes");
754 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
758 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
759 armv7m_info.core_mode = ARMV7M_MODE_ANY;
760 armv7m_info.core_state = ARMV7M_STATE_THUMB;
762 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
763 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
764 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
765 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
766 init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
767 init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
768 init_reg_param(®_params[6], "r6", 32, PARAM_OUT);
769 init_reg_param(®_params[7], "r7", 32, PARAM_OUT);
773 u32 thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
775 target_write_buffer(target, source->address, thisrun_count * 4, buffer);
777 buf_set_u32(reg_params[0].value, 0, 32, source->address);
778 buf_set_u32(reg_params[1].value, 0, 32, address);
779 buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
780 WARNING("Algorithm flash write %i words to 0x%x, %i remaining",thisrun_count,address, wcount);
781 DEBUG("Algorithm flash write %i words to 0x%x, %i remaining",thisrun_count,address, wcount);
782 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
784 ERROR("error executing stellaris flash write algorithm");
785 target_free_working_area(target, source);
786 destroy_reg_param(®_params[0]);
787 destroy_reg_param(®_params[1]);
788 destroy_reg_param(®_params[2]);
789 return ERROR_FLASH_OPERATION_FAILED;
792 buffer += thisrun_count * 4;
793 address += thisrun_count * 4;
794 wcount -= thisrun_count;
798 target_free_working_area(target, write_algorithm);
799 target_free_working_area(target, source);
801 destroy_reg_param(®_params[0]);
802 destroy_reg_param(®_params[1]);
803 destroy_reg_param(®_params[2]);
804 destroy_reg_param(®_params[3]);
805 destroy_reg_param(®_params[4]);
806 destroy_reg_param(®_params[5]);
807 destroy_reg_param(®_params[6]);
808 destroy_reg_param(®_params[7]);
813 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
815 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
816 target_t *target = bank->target;
817 u32 address = offset;
818 u32 flash_cris,flash_fmc;
821 if (bank->target->state != TARGET_HALTED)
823 return ERROR_TARGET_NOT_HALTED;
826 DEBUG("(bank=%p buffer=%p offset=%08X count=%08X)",
827 bank, buffer, offset, count);
829 if (stellaris_info->did1 == 0)
831 stellaris_read_part_info(bank);
834 if (stellaris_info->did1 == 0)
836 WARNING("Cannot identify target as a Stellaris processor");
837 return ERROR_FLASH_OPERATION_FAILED;
840 if((offset & 3) || (count & 3))
842 WARNING("offset size must be word aligned");
843 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
846 if (offset + count > bank->size)
847 return ERROR_FLASH_DST_OUT_OF_BANK;
849 /* Configure the flash controller timing */
850 stellaris_read_clock_info(bank);
851 stellaris_set_flash_mode(bank,0);
854 /* Clear and disable flash programming interrupts */
855 target_write_u32(target, FLASH_CIM, 0);
856 target_write_u32(target, FLASH_MISC, PMISC|AMISC);
858 /* multiple words to be programmed? */
861 /* try using a block write */
862 if ((retval = stellaris_write_block(bank, buffer, offset, count/4)) != ERROR_OK)
864 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
866 /* if block write failed (no sufficient working area),
867 * we use normal (slow) single dword accesses */
868 WARNING("couldn't use block writes, falling back to single memory accesses");
870 else if (retval == ERROR_FLASH_OPERATION_FAILED)
872 /* if an error occured, we examine the reason, and quit */
873 target_read_u32(target, FLASH_CRIS, &flash_cris);
875 ERROR("flash writing failed with CRIS: 0x%x", flash_cris);
876 return ERROR_FLASH_OPERATION_FAILED;
882 address += count * 4;
891 if (!(address&0xff)) DEBUG("0x%x",address);
892 /* Program one word */
893 target_write_u32(target, FLASH_FMA, address);
894 target_write_buffer(target, FLASH_FMD, 4, buffer);
895 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
896 /* DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
897 /* Wait until write complete */
900 target_read_u32(target, FLASH_FMC, &flash_fmc);
902 while(flash_fmc & FMC_WRITE);
907 /* Check acess violations */
908 target_read_u32(target, FLASH_CRIS, &flash_cris);
909 if(flash_cris & (AMASK))
911 DEBUG("flash_cris 0x%x", flash_cris);
912 return ERROR_FLASH_OPERATION_FAILED;
918 int stellaris_probe(struct flash_bank_s *bank)
920 /* we can't probe on an stellaris
921 * if this is an stellaris, it has the configured flash
924 if (bank->target->state != TARGET_HALTED)
926 return ERROR_TARGET_NOT_HALTED;
929 /* stellaris_read_part_info() already takes care about error checking and reporting */
930 return stellaris_read_part_info(bank);
933 int stellaris_auto_probe(struct flash_bank_s *bank)
935 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
936 if (stellaris_info->did1)
938 return stellaris_probe(bank);